JPS5918992A - Power source voltage generation circuit for liquid crystal display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply voltage generation circuit for a liquid crystal display device.

Liquid crystals are driven by alternating current to extend their lifespan.

When driving a liquid crystal display device having a plurality of pixels (segments) arranged in a matrix, the voltage averaging method 1/a is used as a method for providing optimal driving conditions according to the number of scanning lines n.
Bias methods are known.

According to the voltage averaging method, on the premise that the optical change of the liquid crystal depends on the effective value of the voltage applied to it, the driving voltage is varied so as to keep the effective value of the driving voltage applied to all pixels constant. It will be done.

FIG. 1 shows a configuration diagram of a liquid crystal display device having a dot matrix configuration. In the figure, the plurality of pixels SG are arranged at the intersections of the plurality of common electrodes COM1 to COM16 and the plurality of segment electrodes S1 to Sl. In order to display a desired pattern by the plurality of pixels SG, the common electrodes COM1 to COM16 are sequentially scanned (selected) in an appropriate order. Segment electrode S1
to S2 are set to the selected or non-selected level in synchronization with the scanning of the common electrode, according to the pattern to be displayed.

FIG. 2 shows an example of a voltage waveform applied to a liquid crystal display according to the voltage averaging method. In the figure, n=16,
It is a timing diagram of selection and non-selection in the case of 1/5 bias.

The drive voltage applied to the pixel SG has a bias value of 1/5 of the peak value V0 except during the selection period. That is,
The driving voltage is appropriately weighted depending on the number of scanning lines provided in the display device and whether pixels are selected or not.

Now, in general, assuming that the number of scanning lines is n and the bias is 1/a, the effective values VS·VNS of the voltages applied to selected and non-selected pixels are given by the following equations (1) and (2).

Here, V0 is a drive voltage (peak value).

In order to obtain a display with good contrast, a is determined so that the ratio α between VS and VNS is maximized. That is, from the above equations (1) and 2, the ratio α is expressed as the following equation (3).

It is.

For example, when the number of scanning lines n is 16 and pixels are driven with a duty of 1/16, a becomes 5 and αma
x is approximately 1.29.

Therefore, in this case, the voltage applied to the scanning line and the display driving voltage are respectively set appropriately so that the driving voltage applied to the pixel has a waveform as shown in FIGS. 2A and 2B.

Note that FIGS. 2C and 2D show voltage waveforms applied to the common electrodes (scanning lines) COM1 and COM2, respectively, as shown in FIG. 1. The selection level of the common electrode is V0 or 0, and the non-selection level is 4V0/5 or V
It is considered to be 0/5. Accordingly, according to FIG.
1. Similarly, common electrode COM2 is selected during period γ2. As described above, the level of the segment electrode is determined by the operation of the common electrode and the data to be displayed. The selection level of the segment electrode is 0 or V0, and the non-selection level is 2V0.
/5 or 3V0/5. FIG. 2E shows a pixel (segment) coupled to the segment electrode S1 in FIG.
An example of the voltage waveform applied to the segment electrode S1 when only the pixel SG11 is to be selected (displayed) among SG11 to SG161 is shown. Pixel S to be selected
A voltage having a waveform as shown in FIG. 2A is applied to G11, and a voltage having a waveform as shown in FIG. 2B is applied to the unselected pixel SG21.

The driving voltage V0 is determined according to the characteristics of the liquid crystal display device. If the drive voltage V0 is increased too much, the effective value of the voltage applied to the pixel that should be unselected is increased accordingly. As a result, all pixels are selected. Conversely, if the driving voltage V0 is made too small, the effective value of the voltage applied to the pixel to be selected will be an insufficient value. As a result, no pixels will be selected.

FIG. 3 shows the pixel drive voltage V0 vs. relative reflection brightness B characteristic. The characteristic curve CVS shows the characteristics of the pixel to be selected, that is, the pixel to which a voltage having the waveform as shown in FIG. 2A is applied, and the characteristic curve CVNS is
It shows the characteristics of a pixel to be made non-selected, that is, a pixel to which a voltage having the waveform as shown in FIG. 2B is applied.

The following becomes clear from the characteristic curves CVS and CVNS. In other words, if the lower limit of allowable reflected brightness in non-selected pixels is 80%, and the upper limit of allowable reflected brightness in selected pixels is 40%, then the possible range of drive voltage V0 is as follows: It is limited to the shaded range (V60≦V0≦V40) in the figure.

In other words, the shaded range is considered to be the operating voltage range with substantially no crosstalk. Therefore, the driving voltage V0
is preferably set to a central value determined by the maximum allowable value V60 and the minimum allowable value V40. Note that the above operating voltage range becomes narrower as the number of scanning lines n increases from the above equation.

The threshold characteristics of such liquid crystals have viewing angle dependence. Considering this viewing angle dependence, the range of the operating voltage V0 becomes narrower. Furthermore, the optimum range of the driving voltage V0 has relatively strong concentration dependence depending on the characteristics of the liquid crystal material. FIG. 4 shows an example of temperature versus drive voltage characteristics. For example, some liquid crystals have negative temperature coefficients such that their optimal drive voltage varies by about 0.11 volts for relatively narrow temperature changes such as from 0° to 25°C. In addition, the optimum drive voltage range varies relatively widely, for example, V40' and V60', depending on manufacturing variations of display devices.

Therefore, an object of the present invention is to provide a power supply voltage generation circuit for a liquid crystal display device having a temperature guarantee function and a variation compensation function for liquid crystal.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 5 shows a circuit block diagram of an embodiment of the present invention.

The illustrated circuits 1 to 4 are formed on one semiconductor chip using known CMOS integrated circuit technology. The power supply voltage for each circuit is output from a power supply E coupled between external terminals P1 and P0.

The symbol 1 indicates a level setting regulator. This regulator 1 includes, but is not particularly limited to, a voltage comparator circuit CL1 and a variable impedance means M.
It is composed of OSFETQ1.

The voltage comparator circuit CL1 includes a pair of MOSFETs whose gate electrodes are made of silicon of opposite conductivity types and whose channel conductivity types are the same. The voltage comparator circuit CL1 calculates an offset voltage VO determined by the threshold voltage difference between the pair of MOSFETs (see FIG. 7).
Has F1. The pair of MOSFETs have channel formation regions made to have the same impurity concentration and gate insulating films made of the same material and thickness using semiconductor integrated circuit technology. Therefore, the threshold voltage difference between the pair of MOSFETs, ie, the offset voltage VOF1, is made equal to the Fermi level difference between p-type silicon and n-type silicon. By setting the conductivity-determining impurities in p-type silicon and n-type silicon to a high concentration approximately equal to the saturation concentration, the offset voltage VOF1 becomes a value substantially equal to the bandgap of silicon.

A ground potential (0 volts) is applied to the non-inverting input (+) of the voltage comparison circuit CL1. External power supply voltage supply terminal P1
A MOSFET Q1 is provided between the inverting input (-) and the inverting input (-). At the gate of this MOSFETQ1,
The output voltage of the voltage comparison circuit CL1 is applied. As a result, the MOSFE
The impedance of TQ1 is controlled. As a result, the voltage VOL1 becomes a constant voltage according to the offset voltage VOF1. In this case, the offset voltage VOF1 is set to a value approximately equal to the silicon bandgap as described above, and variations in device characteristics such as relatively large variations in absolute values of the respective threshold voltages of the pair of MOSFETs are avoided. Since it is an extremely stable voltage (approximately 1.1 volts) that is substantially unaffected and has virtually no temperature dependence, the voltage VOL1 is also an extremely stable constant voltage. This constant voltage VOL1 is divided by a variable resistor R. The divided voltage VR obtained through the variable resistor R can be set to any level within the range of the constant voltage VOL1.

What is designated by symbol 2 is a temperature compensation regulator. This regulator 2 includes, but is not particularly limited to, a voltage comparator circuit CL2 and a control MOS as a variable impedance.
FETQ2.

According to this embodiment, the drive voltage supplied to the liquid crystal display is varied based on the threshold voltage versus temperature characteristics of the MOSFET. In this case, since the threshold voltage of a MOSFET configured as a semiconductor integrated circuit device has a negative temperature coefficient, the driving voltage supplied to the liquid crystal display device is reduced as the operating temperature rises. That is, the driving voltage is suitably changed as the temperature changes.

The voltage comparator circuit CL2 has an offset voltage VOF2 whose temperature coefficient corresponds to the temperature coefficient of the liquid crystal to be driven, in order to compensate for the temperature of the liquid crystal display device.

This offset voltage VOF2 is formed by a level shift circuit using the threshold voltage of a MOSFET.

The output voltage VR of the level setting regulator 1 is applied to the non-inverting input (+) of the voltage comparison circuit CL2.

Control MOSFET Q2 is provided between external power supply voltage supply terminal P1 and its inverting input (-), and the output voltage of voltage comparison circuit CL2 is applied to its gate.

As a result, the impedance of MOSFETQ2 is controlled in the same way as MOSFETQ1 of the regulator 1, and as a result, the voltage VCL2 at the inverting input (-) of the voltage comparison circuit CL2 is equal to the sum of the voltage VR and the offset voltage VOF2. Becomes a value.

The output voltage of the temperature compensation regulator 2, that is, the voltage V
OL2 is transmitted to a booster circuit indicated by symbol 3. The booster circuit 3 includes a plurality of capacitors such as a charge pump capacitor C1, and a smooth container C, although the detailed circuit configuration is not shown in the drawings.
Multiple capacitance and multiple switch MOSFETs such as n
It is equipped with

The booster circuit 3 uses the voltage VOL2 as an input voltage to drive the liquid crystal display device with, for example, the above-mentioned 1/5 bias voltage.
2 and its 2x, 3x, 4x, and 5x boosted values (2V
to 5V (=0)). For example, the capacitor C1 has one terminal supplied with the voltage VOL2 via the switch MOSFET and the circuit ground voltage supplied with the other terminal during the first period of the boost operation that is regularly repeated. Ru. As a result, the capacitor C1 is charged to the voltage VOL2. During the second period of the boost operation, voltage VOL2 is supplied to the other terminal of capacitor C1, and as a result, a voltage boosted to approximately 2·VOL2 is output to one terminal of capacitor C1. The voltage 2·VOL2 boosted by the capacitor C1 is supplied to the smoothing capacitor Cn via a suitable switch MOSFET. By repeating such boosting operation, the charging voltage of the smoothing capacitor Cn becomes the voltage VO
It is maintained at a value approximately twice that of L2. Similarly, a triple boosted voltage is obtained by a circuit operation that uses the double boosted voltage obtained from the smoothing capacitor On and the input voltage VOL2, and a circuit operation that uses the double boosted voltage and the triple boosted voltage generates a 4× boosted voltage.
A double or five-fold boosted voltage can be obtained. Although not particularly limited, the capacitances such as capacitors C1 and Cn required for boost operation are as follows:
Due to its relatively large capacity, it is used as an external component of semiconductor integrated circuit devices. That is, the capacitances C1 to Cn are
It is coupled to external terminals P4 and P5 of the semiconductor integrated circuit device. An appropriate clock signal for operating the booster circuit 3 is outputted from a control circuit as described later in the drive circuit 4, although it is not particularly limited.

The output voltage of the booster circuit 3 is supplied to the drive circuit 4. Although the details are not shown, the drive circuit 4 is connected to the liquid crystal display device 5.
RAM (
Random access memory), a pattern generation circuit consisting of a ROM (read only memory) that forms appropriate pattern data by receiving a data signal output from the RAM, a latch circuit that holds the output of the pattern generation circuit, or a register, a first voltage selection circuit that selects the voltage to be supplied to the segment electrodes of the liquid crystal display device 5 based on the pattern data signal output from the latch circuit and an appropriate timing signal; It consists of a second voltage selection circuit for selecting the voltage to be supplied to the common electrode of the device 5, and a control circuit for controlling the operation of these circuits. The data to be written to the RAM in the drive circuit 4 is sent to the external terminal P.
The data is supplied from an information processing device such as a microcomputer (not shown) via P7 to P8.

A drive signal output from the drive circuit 4 is supplied to the liquid crystal display device 5 via external terminals P9 and P10.

According to this embodiment, the CM in which circuits 1 to 4 are formed
The OS integrated circuit device and the liquid crystal display device 5 are placed, for example, in one case and placed under the same ambient temperature. As is well known, the CMOS integrated circuit device in which the circuits 1 to 4 are formed has extremely low power consumption characteristics, and the temperature rise in its operating state is sufficiently small. Since the temperature rise of the CMOS integrated circuit device is sufficiently small, the operating temperature of the temperature compensation MOSFET provided in the temperature compensation regulator 2 is set to a value that is substantially equal to that of the liquid crystal display device 5. . Since a large temperature change substantially equal to a change in ambient temperature can be applied to the temperature compensation MOSFET, a voltage with an appropriate temperature coefficient can be outputted from the temperature compensation regulator 2.

According to the above configuration, the level of voltage VCL2 can be adjusted by adjusting voltage VR without undesirably changing the temperature coefficient of voltage VCL2. Therefore, it is possible to realize level adjustment and temperature compensation commensurate with the characteristics and manufacturing variations of the liquid crystal display device to be driven.

When a booster circuit is used as in this embodiment, there is an advantage that relative level adjustment and temperature compensation can be automatically performed even between each bias voltage V to 5V.

FIG. 6 shows a specific example circuit of the above-mentioned regulators 1 and 2.

MOSFETs Q1 to Q23 in this example are:
As described above, it is formed on a single semiconductor substrate together with the MOSFETs forming circuits 3 and 4 of FIG. 5 by known complementary MOS integrated circuit technology.

The voltage comparison circuit CL1 of the level setting regulator 1 is constituted by various circuit elements.

The p-channel actuated MOSFETs Q3, Q4 have a threshold voltage difference substantially equal to the silicon bandgap;
That is, it is configured to have an offset voltage VOF1. Therefore, MOSFETQ3 has a gate electrode composed of a polysilicon layer containing p-type impurities at a high concentration of 1016 cm-3 or more, and MOSFETQ4 has
The gate electrode also contains n-type impurities at 1018 cm-3.
It is composed of a polysilicon layer containing a high concentration as described above. Accordingly, the ID-
The IG characteristics have a certain difference as shown in FIG. This difference is equal to the offset voltage VOF1.

The drains of the differential MOSFETs Q3 and Q4 are connected to an n-channel MOSFET Q5, which constitutes a current mirror circuit.
Q6 is provided as a load.

On the common source side of the differential MOSFETs Q3 and Q4,
A p-channel MOSFET Q7 is provided as a low current source.

Furthermore, MOSFETs Q8 to Q11 constitute a constant current bias circuit. The above-mentioned MOSFET Q7 and MOSFET Q12, which will be described later, are caused to operate at a constant current by this constant current bias circuit.

A power supply voltage is supplied to the voltage comparison circuit CL1 having the above configuration from an external power supply voltage terminal P1.

MO, which is the non-inverting input (+) of the voltage comparison circuit CL1,
The gate of SFETQ3 is grounded.

A MOSFET Q1 is provided between the gate of the MOSFET Q4, which is the inverting input (-), and the power supply terminal P1. The output voltage of the voltage comparison circuit CL1 is applied to the gate of this MOSFETQ1. Constant current M
OSFETQ12 is provided to allow an appropriate bias current to flow through the MOSFETQ1.

In this embodiment, although not particularly limited, in order to prevent an undesirable increase in the number of external terminals of the IC, a voltage dividing circuit for level setting includes an internally provided fixed resistor R1 and an external terminal P2.
and a variable resistor R2 provided externally via a variable resistor R2. The level of the divided voltage VR can be easily adjusted by adjusting the variable resistor R2.

On the other hand, the voltage comparison circuit CL2 of the temperature compensation regulator 2 is the same as the voltage comparison circuit CL1 described above except for the following differences.

The differential MOSFETs Q13 and Q14 are not particularly limited, but from the relationship with the level setting range of the divided voltage V1,
Specifically, the voltage value of output voltage VOL2 is set to -1.2 to -1.
．． In order to be adjustable over a range such as 5 volts, there is a threshold voltage difference to obtain the following offset voltage VOF'.

That is, MOSFETQ13 has a gate electrode of M
Like that of OSFETQ4, MOSFET14 is composed of a polysilicon layer containing a high concentration of n-type impurities.
The gate electrode is made of an intrinsic polysilicon layer, ie, substantially free of conductivity type determining impurities. In this case, the ID-IG characteristic of MOSFET Q14 becomes as shown by the dotted line in FIG.

Therefore, the difference between the two (approximately 0.48 volts) appears as the offset voltage VOF2'.

The MOSFET Q14 on the inverting input side is a diode-type MOSFET whose gate and drain are commonly coupled.
A level shift circuit using ETQ23 is provided.

In order to make the threshold voltage VthN of this MOSFETQ23 have a predetermined negative temperature coefficient, this MOSFETQ2
3, a bias current of an appropriate value (approximately 10 nA) is passed through constant current MOSFET Q23. The above MOS
The threshold voltage VthN of FETQ23 is, for example, 0.4.
It is said to be around 5 volts. As a result, voltage comparator circuit CL
2 has an offset voltage VOF2 of substantially the order of about 0.93 volts.

Since the voltage comparator circuit CL2 has an offset voltage of approximately 0.93 volts, in order to set the voltage range of the output voltage VOL2 to approximately -1.2 to 1.5 volts, the voltage VR must be set to -0. It may be varied within the range of 3 to 0.8 volts. This voltage VR is the constant voltage VOL1 (approximately 1.1
can be obtained by dividing the voltage (volts). The output voltage VOL2 is given a temperature coefficient that matches the negative temperature coefficient of the threshold current VthN of the MOSFET Q23.

As a result, the output voltage VOL2 becomes 0 as described above.
For a temperature change from 0C to 25C, an appropriate voltage change such as -70mV (millivolts) can be set.

The invention is not limited to the above embodiments.

For example, in order to provide an offset voltage with an appropriate temperature coefficient to the voltage comparison circuit CL2, if necessary, the voltage division voltage V
MOSFE through the level shift circuit as described above.
It may be arranged to enter the gate of TQ13.

In addition, an offset voltage VOF is applied to this voltage comparison circuit CL2.
2 can take various embodiments depending on the output voltage VOL2 to be obtained. for example,
As mentioned above, when obtaining a voltage in the range of about 1.2 to 1.5 volts, depending on the thickness, film quality, channel length, etc. of the gate insulating film of MOSFETQ23, the above threshold voltage Vth is required. Voltage (about 0.9 volts)
It is also possible to form a .

Furthermore, the conductivity types of the MOSFETs used may be combined in various ways depending on the polarity of the required voltage.

MOSFETs Q17 and Q22 as shown in FIG. 6 may be biased by a bias circuit consisting of MOSFETs Q8 to Q11. In this case, the MOSFE
The bias circuit consisting of TQ15 to Q21 can be omitted.

The regulator 1 shown in FIG. 5 may be of any type as long as it is accurate in itself and can form an output voltage that does not substantially change in level even with temperature fluctuations, and the regulator 1 shown in FIG. It is not limited to specific circuits. The voltage output from regulator 1 has a level equal to that of the MOSFET.
Instead of being determined by the difference in the fermi levels of the silicon layers serving as the gate electrodes of Q3 and Q4, it may be determined by the difference in work function of gate electrodes made of different metal materials.

The circuit for determining the level of voltage VR is not limited to only variable resistors as shown in FIGS. 5 and 6. FIG. 8 shows another circuit for changing the level of voltage VR. The resistance values of the resistors R31 to R33 are appropriately weighted. These resistors R31 to R33 are connected substantially in parallel to resistor R2 when MOSFETs Q30 to Q32 are turned on by the output of the counter 6. External terminal P
9 is maintained at a negative potential (logic "0") by the pull-up resistor R4 when the switch KS is not turned on. The gate circuit G is therefore closed and the contents of the counter 6 are kept in their previous state. switch K
When S is closed, external terminal P9 is closed accordingly.
1'', the gate circuit G is opened and the clock signal φ is supplied to the counter 6. As a result, the contents of the counter 6 are updated. As a result, the level of voltage VR is changed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a liquid crystal display device with a dot matrix configuration. Figure 2 is a waveform diagram of the driving voltage applied to the liquid crystal display. Figures 3 and 4 are characteristic curve diagrams of the liquid crystal display. , FIG. 5 is a block diagram showing an embodiment of the present invention, FIG. 6 is a circuit diagram of a specific embodiment thereof, and FIG. 7 is a diagram showing ID-V of a differential MOSFET used in the voltage comparison circuit.
G characteristic diagram, FIG. 8 is a circuit diagram of the voltage adjustment circuit. 1... Regulator for level setting, A... Regulator for temperature compensation, 3... Boost circuit. Agent Patent Attorney Toshiyuki Kawakawa

Claims (6)

[Claims] 1. The first and second MOSFETs include first and second MOSFETs whose gate electrode materials have different work functions.
By using OSFET, the first and second M
A first voltage generation circuit generates a voltage based on the work function difference between the gate electrodes of the OSFET, and a substantial offset voltage having temperature characteristics commensurate with the temperature characteristics of the liquid crystal display device to be driven is connected to the input terminal and the output terminal. a second voltage generating circuit having a voltage between the voltage generating circuit and the output voltage of the first voltage generating circuit is supplied to the input terminal;
1. A power supply voltage generating circuit for a liquid crystal display device, comprising: a voltage generating circuit, and obtaining an output voltage from the second voltage generating circuit. 2. 2. The power supply voltage generation circuit for a liquid crystal display device according to claim 1, wherein the liquid crystal display device is driven by the output voltage and a multi-level voltage multiplied by n times the output voltage. 3. 2. The voltage generating circuit for a liquid crystal display device according to claim 1, wherein the voltage applied to the input terminal of the second voltage generating circuit has a level set by a voltage level changing circuit. 4. The voltage level changing circuit is comprised of a voltage dividing circuit, and is configured to output a voltage to be supplied to the second voltage generating circuit by receiving the output voltage of the first voltage generating circuit. A power supply voltage generation circuit for a liquid crystal display device according to claim 3. 5. 5. The power supply voltage generating circuit for a liquid crystal display device according to claim 4, wherein the voltage dividing circuit is entirely or partially constituted by an external variable resistor. 6. The second voltage generation circuit includes a level shift MOSFET whose gate and drain are coupled, and the offset voltage is at least partially connected to the level shift MOSFET.
6. A power supply voltage generating circuit for a liquid crystal display device according to claim 1, characterized in that the circuit includes a threshold voltage of a FET.