JPS59188954A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59188954A
JPS59188954A JP58064065A JP6406583A JPS59188954A JP S59188954 A JPS59188954 A JP S59188954A JP 58064065 A JP58064065 A JP 58064065A JP 6406583 A JP6406583 A JP 6406583A JP S59188954 A JPS59188954 A JP S59188954A
Authority
JP
Japan
Prior art keywords
bonding pad
pad
bonding
lead wire
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58064065A
Other languages
Japanese (ja)
Inventor
Masaaki Inada
稲田　正明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58064065A priority Critical patent/JPS59188954A/en
Publication of JPS59188954A publication Critical patent/JPS59188954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the generation of the failure that a lead wire and the periphery of a semiconductor substrate come in contact and are then electrically conducted by a method wherein a sub bonding pad higher than a bonding pad is provided outside this bonding pad. CONSTITUTION:The sub bonding pad 5 higher than the bonding pad 3 is provided on a semiconductor substrate 1 outside the pad 3. Thereby, the lead wire 4 is supported by the pad 5 so as to lift up, even when the lead wire 4 is pushed downward in the compression bonding of said lead 4 and the pad 3 by means of a tool at the time of bonding. As a result, the contact of said wire 4 with the periphery of the substrate 1 does not generate.

Description

【発明の詳細な説明】 本発明は、半導体基板上に設けられたリード線接続用の
ポンディングパッドの構造改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structural improvement of a bonding pad for connecting lead wires provided on a semiconductor substrate.

ＩＣ，ＬＳＩ等の組立工程において、インナーリードポ
ンチインク法にょフ組立を笑顔する場合は、一般に、半
導体基板上に厚く（〜２０μｍ）配置したボンティング
パッドに熱圧Ｎ、超音波等の方法によりリードＭ１に接
続するのが一般的である。In the assembly process of ICs, LSIs, etc., when using the inner lead punch-ink method, it is generally necessary to attach bonding pads placed thickly (~20 μm) on the semiconductor substrate using methods such as hot pressure N or ultrasonic waves. It is generally connected to lead M1.

この場合のポンディングパッドとリード線との優続時に
、ポンプイングツフルにより圧着するが。In this case, when the pounding pad and lead wire are connected, they are crimped by the pumping tuffle.

この時又框使用中ｙｌ（＋７−ド線が半導体基板周辺部
に接触する可能性が非常に大きく、接触したならば電気
的に導通してしまう為不良となってしまう〇又、ポンデ
イングパッド間の距離を小さくシ、パッド密度金大きく
するために、ポンディングパッドの厚さを薄くしようと
すると、さらにリード線が半導体基板周辺部に験触する
可能性は大きくなってくる。At this time, there is a very high possibility that the yl (+7-) wire will come into contact with the peripheral area of the semiconductor substrate while the frame is in use, and if it does, it will become electrically conductive, resulting in a defect. Also, the ponding pad If an attempt is made to reduce the thickness of the bonding pad in order to reduce the distance between the bonding pads and increase the pad density, the possibility that the lead wires will come into contact with the peripheral area of the semiconductor substrate increases.

本発明の目的は、上記のような従来技術の欠点を取除い
た半導体装！全提供するにある〇本発明の半導体装置で
１Ｘ、、ポンディングパッドの外側に該ボンティングパ
ラ）゛よりも高さの高い副ポンディングパッドがもうけ
られているので、リード線と半導体基板周辺部が妥触し
電気的に導通する不良の′廃生が防止されている。The object of the present invention is to provide a semiconductor device that eliminates the drawbacks of the prior art as described above! In the semiconductor device of the present invention, as shown in FIG. This prevents the occurrence of defects that occur due to interference between parts and electrical continuity.

以下１本発明を図面全参照して説明する〇第１図に従来
のボンティングパッド構造において、ボンディング、し
た場合の様子を示す断面図である。第１図（：Ｉ？いて
、ボンディング時のツールによるリード線４とボンティ
ングバッド３との圧着の際ｒこ、リード線４が下部方向
に押しやられてしまい、リード線４と半導体基板ｌとが
吸触してしまう不良が時々発生する。The present invention will be described below with reference to all the drawings. FIG. 1 is a sectional view showing the state of bonding in a conventional bonding pad structure. When the lead wire 4 and the bonding pad 3 are crimped by the tool during bonding, the lead wire 4 is pushed downward, and the lead wire 4 and the semiconductor substrate l are pressed together. Occasionally, a defect occurs in which the material is absorbed into the product.

第２図は本発明の一実施例の部外断面図である。FIG. 2 is an external sectional view of one embodiment of the present invention.

第２図において、ボンティング時のツールによるリード
線４とボンティグバッド３との圧着の際に。In FIG. 2, when the lead wire 4 and the bonding pad 3 are crimped by a tool during bonding.

リード線４が下部方向に押しやられたとしても。Even if the lead wire 4 is pushed towards the bottom.

ボンティングパッドよりも高さの高い副ポンディングパ
ッド５が、ポンディングパッド３の外側の基板上に設け
られているので、リード線４μ副ポンデイングパツドに
持ち上けるように支えられている結果、リード線４と半
導体基板１０周辺との啜触が発生しない。Since the sub-bonding pad 5, which is higher in height than the bonding pad, is provided on the substrate outside the bonding pad 3, it is supported so as to be lifted up by the lead wire 4μ on the sub-bonding pad. As a result, no contact occurs between the lead wire 4 and the periphery of the semiconductor substrate 10.

次に本発明のポンディングパッド形成方法の一例につい
て、第３図（ａ）、　（ｂ）、　（Ｃ）により説明する
。Next, an example of the method of forming a bonding pad according to the present invention will be explained with reference to FIGS. 3(a), 3(b), and 3(c).

まず第３図（ａ）のようニ、トランジスタ等の各素子拡
散領域１１が形成された半導体基板ｌの上に。First, as shown in FIG. 3(a), a semiconductor substrate 1 is formed on which each element diffusion region 11 such as a transistor is formed.

絶縁膜２を介して約３０００λ厚さのＴｉ／Ｐｔ膜１２
を形成する。つぎに、第３図（ｂ）のように、　’Ｊ、
’ｉ／Ｐｔ膜１２の上部に、配線層となる部分に約２μ
ｍ厚の金の配線層１３とポンディングパッド１４’に形
成する。つキニ、第３図（Ｃ）のように、副ボンディン
グとなるべき部分のみに公知の方法により約５（細）厚
の金を被着し副ポンディングパッド１５を形成する。以
上の工程によりボンティングパッド１４よジも高さの高
い副ボンディングバット１５が形成できる。A Ti/Pt film 12 with a thickness of approximately 3000λ is placed through an insulating film 2.
form. Next, as shown in Figure 3(b), 'J,
'On the top of the i/Pt film 12, approximately 2μ
A gold wiring layer 13 with a thickness of m and a bonding pad 14' are formed. Next, as shown in FIG. 3(C), a sub-bonding pad 15 is formed by depositing gold approximately 5 (thin) thick only on the portion to be sub-bonded by a known method. Through the above steps, it is possible to form the sub-bonding butt 15 which is taller than the bonding pad 14.

上記のような方法で形成した本発明にかかる金属電極構
造において、ボンディング？笑顔すれば。In the metal electrode structure according to the present invention formed by the above method, bonding? If you smile.

ボンティングツールによジボンティングパッドとリード
線を圧着してリード線が下部万同Ｖ′ｃ変形し。The bonding pad and lead wire are crimped using a bonding tool, and the lead wire is deformed to the lower part V'c.

半導体基板ｖｃ咲触しようとしても、ボンティングパッ
ドよりも厚さの厚い副ポンディングパッドによりリード
線が強制的に押し上げられてしまう為に、ボンディング
工程においてリード線が半導体基板に襞触するというこ
とは全く発生しなくなり。Even if you try to touch the semiconductor substrate VC, the lead wires are forced up by the sub-bonding pad, which is thicker than the bonding pad, so the lead wires come into contact with the semiconductor substrate during the bonding process. no longer occurs at all.

歩留りが同上する。Yield is same as above.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装ｔｊｌｔにおけるリード線と基
板との慶触を説明するための断面図、第２図μ本発明の
一実施例（係るリード線ボンティング部の断面図、第３
図（ａ）、　（ｂ）、　（Ｃ）ぼ本発明の一実施例に係
る半導体装置のボンティングバッド形成工程を説明する
ための工程ｊ順の断面図でらる。 ｌ°°°牛導体基板、２・・・絶縁膜、３．１４・・・
ポンディングパッド、４・・・リード線、５．１５・・
・副ボンティングパッド、１１・・・トランジスタ素子
拡散領域、１２・・・Ｔｊ／Ｐｔ膜、１３・・・配線層
。 ２３０FIG. 1 is a sectional view for explaining the contact between the lead wire and the substrate in a conventional semiconductor device, FIG. 2 is a sectional view of an embodiment of the present invention (a sectional view of the lead wire bonding part),
Figures (a), (b), and (c) are cross-sectional views in the order of process j for explaining the bonding pad forming process of a semiconductor device according to an embodiment of the present invention. l°°°Cow conductor substrate, 2... Insulating film, 3.14...
Ponding pad, 4...Lead wire, 5.15...
- Sub bonding pad, 11... Transistor element diffusion region, 12... Tj/Pt film, 13... Wiring layer. 230

Claims (1)

【特許請求の範囲】[Claims] リード線接続用リボンディングパッドを上面に有する半
導体基板を含む半導体装置において、前記ボンティング
パッドの外側に、このボンティングパッドよ！ｌｌ高く
して前記リード線を支える副ポンディングパッドが前記
基板上に設けられていることｔ″特徴する半導体装置。In a semiconductor device including a semiconductor substrate having a rebonding pad for connecting lead wires on the upper surface, this bonding pad is placed on the outside of the bonding pad! 11. A semiconductor device characterized in that a sub-bonding pad is provided on the substrate to support the lead wire.
JP58064065A 1983-04-12 1983-04-12 Semiconductor device Pending JPS59188954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58064065A JPS59188954A (en) 1983-04-12 1983-04-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58064065A JPS59188954A (en) 1983-04-12 1983-04-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59188954A true JPS59188954A (en) 1984-10-26

Family

ID=13247315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58064065A Pending JPS59188954A (en) 1983-04-12 1983-04-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59188954A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091772A (en) * 1989-05-18 1992-02-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091772A (en) * 1989-05-18 1992-02-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and package

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