JPS59188208A - Power amplifier - Google Patents

Abstract

PURPOSE:To reduce the distortion of a push-pull Darlington-connected amplifier by compensating variation in the base-emitter voltages of transistors (TR) by using current mirror circuits. CONSTITUTION:The push-pull power amplifier consisting of driving TRs Q3 and Q4 and output TRs Q1 and Q2 is provided with current mirror circuits 1 and 2 and the bias compensating circuit composed of TRs Q5 and Q6, diodes D1 and D2, etc. The bias compensating circuit adds the sum of the difference voltage between the base-emitter voltages of the TRs Q3 and Q4 and the difference voltage between the base-emitter voltages of the TRs Q1 and Q2 to a bias voltage as the voltage drop across a resistance R31 or R32 to compensate variation in base-emitter voltage.

Description

[Detailed description of the invention] The present invention relates to improvements in power amplifiers.

The configuration of the power amplification stage of an audio power amplifier is generally as follows:
As shown in FIG. 1, the first drive transistor Q3 on the positive side, the first output transistor Q1, the second drive transistor Q4 on the negative side, and the first drive transistor Q2 of the second output transistor Q2 are connected in two stages. , second output transistor Q
l, emitter resistor r with Q2 emitters/res connected in series
, r, and connect the midpoint between the emitter resistors r and r to the load RL as an output terminal.
bias voltage VBt, negative side second bias voltage VB
2 is applied to each.

In the above configuration O, the output voltage Vo is: (1) Class A operation region (when the first and second output transistors Q1 and Q2 are in the active state) the first and second output transistors Ql;
, Qz emitter voltage ■1, ■2 is Vt=VS-1-VB-VBE3-VEEIV2=
V S -V R4-V BE4-1- V BE Matatashi ■S Two-person voltage VB = Bias voltage (VB = VB1 = VB2) V
BEn: Base-emitter voltage of transistor Qn (
n-1 to 4).

Here, Therefore, the output voltage ■0 is -VBE4)...(2) However, r: emitter resistance kL: load becomes.

(2) B drive operating region (when the first output transistor ql is on and the second output transistor q2 is off) Output' voltage ■0 is input voltage ■S, first bias voltage VBI (-VB) and the first drive transistor Q
3. The base-emitter voltage VBE3 and VBEI of the first output transistor q1 are connected to the emitter resistance r and the load R.
Since it is the result of dividing the pressure by

As is clear from the above equations (2) and (3), in the class A operation region and the B drive operation region, the output voltage Vo is a function of the base-emitter voltage VBEn of each transistor Qn, and each The base-emitter peak pressure VBEn has non-linear characteristics with respect to the emitter current, and the emitter current of the first and second output transistors Q1 and Qz has a large change due to the influence of the other transistors. Since the changes in their base-emitter voltages BEz and VBE2 are also large, the distortion component becomes large.For example, the bias voltage applied between the bases of the first and second drive transistors Q3 and Q4 Since VB1+VB2 is constant,
In response to a positive direction input, the emitter current of the first output transistor Q1 increases, and accordingly, the base-eminter pressure V BEI increases, and inversely, the base of the second output transistor Q2 increases. - Although the emitter voltage VBE2 decreases, these base-emitter voltages change non-linearly with respect to the emitter's current and the change is large, so the distortion component becomes large. In addition, the transfer characteristics are different in the A-class operating region and the B-drive operating region, and are discontinuous in the boundary region, making it difficult to set 7<Iasumi flow.
Even if an optimal bias current was set, the occurrence of crossover distortion was unavoidable due to the reasons mentioned above. Furthermore, since the output voltage Vo depends on the load impedance ttL, it is easily affected by the load, and furthermore,
@1, if the switching speed of the second output transistors Q1 and Qz is slow, there are drawbacks such as a switching deviation occurring with respect to a high-frequency input signal and notching distortion.

The present invention improves on such conventional drawbacks, and will be explained below with reference to FIG. 1. In the figure, parts equivalent to those of the conventional example shown in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

Hereinafter, an example will be described in (S1).

In FIG. 2, a first current mirror circuit (1) is formed by connecting both emitters of a pair of transistors Q7 and Qs, whose bases are connected together, to a positive power supply +VCC via a resistor k and a wire. Similarly, a second current mirror circuit (2) is formed by connecting the emitters of a pair of transistors Q9 and Q10, whose bases are connected together, to a negative power supply - to lCC via resistors R and lζ, respectively. These first and second Karen l--.

input side transistors Qs of error circuits (1) and (2),
Ql.

The collectors of are connected to both ends G of the resistors R1 and Rt connected in series through the first and second transistors Q5 and Q6, respectively, and the connection midpoint P1 of the resistors R1 and R1 connected in series is connected.
emitter resistors r and r connected in series via resistor ■ζ2
The bases of the first and second transistors Qs and Q6 are connected to the bases of the first and second drive transistors Q3 and Q4, respectively. Then, the output side transistors Q7 and Q of the first and second current mirror circuits (1) and (2)
9 are connected to each other, while the bases of the first and second drive transistors Qs and Q4 are connected to each other. The first and second resistors R31 are connected between the second bias voltages VBI and VB2.
, and the anodes of two diodes D2 in the same direction are connected to the bases of the first and second drive transistors Q3 and Q4, respectively.
The connection midpoint of the diodes Dz and D2 is connected to the output side transistor Q? , Q9'), respectively.

Hereinafter, this embodiment will be described with reference to the first and second output transistors Ql.
, Q2 is in the most active state, that is, in the class A operation region, its output voltage will be analyzed (hereinafter, its operation will be explained).

The current flowing through each branch is designated as 11 to ■4 as shown in the diagram,
Further, since the emitter resistance r is selected to be sufficiently small compared to the resistances R1 and R21, the output voltage 0 is determined under the following conditions: R1, R2':>r II , 12>I3-I4.

Now, if we consider the case when a positive signal is input as the human power ``seeing pressure VS'', the output voltage ``0'' is positive, so the ``1st and 2nd
output transistor Q+, emitter current of Q2 ■l,
I2, and the emitter current I3.14 of the first and second transistors Q5 and Qs is 11 > I2
There is a relationship of I3 > I4.

Therefore, the first and second current mirror circuits (1),
The collector currents of the output side transistors Q7 and Q9 in (2) also become I3.14, and the difference current l3-I4 flows to the first resistor 31 through the first diode D1,
At both ends of this first resistor 1 (31), △V = R31 (I
3-I4) A voltage is generated.

I will analyze it below.

Calculating the voltage of each part, Vl=VS +VB 10△V -VBEI -VBE3
...-(1) V2 = vs -V
B +VBE2 +VBE4 ---
- (2) However, ■1, ■2: Emitter voltage of the first and second output transistors Q1 and Q2 ■S: Input voltage VB = bias voltage (VB = VBx = VB2)△
■: Voltage VBEn generated across the first resistor R31: ) Pressure between the base and emitter of transistor Qn. Voltage ■0 is (△V-VBE1-1-VBE2 VBE3-)VB
E4) ......(3).

Also, each voltage and each current are V5=VS-1-VB+△V-VBE5
・・・・・・(4) V6=MS −VB+VBE6
−(5)1 However, vs, ■6: First and second transistors Qs
, Q6 emitter voltage ■3: Voltage at connection midpoint P1 of resistor R+, λl I3, I4: Relationship between the 11th and 2nd transistors Qs and the emitter current of Q6. is also 13-1.1, so VB -V.

I a-14=□・・・・・・(7)
It is 2.

From formulas (6) and (7), substituting formulas (3), (4), and (5) into this formula yields (R1+2Rz)(r-4-2RL)...(9) becomes. Also, by substituting equations (3) and (9) into equation (7), r Ia-I4= VS(R1+
2Rz) (r-4-2RL) (11) Here, since the voltage generated across the first resistor R31 is AV - R31 (I 3 - I 4 ), (
From formula 11), (R1+2R2-IL3t) r+2(Rt+2R2)
RL(VBEI-VBE2-1-VBE3-VBE4
) ... becomes A (12). Substituting this formula into formula (3) and rearranging it, (Rt-1-2R2-R3t)
r+2(Rt+2R2)Rr.

(R1+2R2-R31)r+2(Rt+2R2)RL
(VBEI-VBE2-1-VBE3-VBE4)
...-...(13).

In equations (12) and (13), if each constant is selected so that R31=Rt +2R2, equations (12) and (13) become as follows, respectively.

-1-(VBEt=VBg2+VBE3-VBE4)
−・−・(14) Vo=vs−−(VBEs−VB
E6) ...(15) On the other hand, since the emitter current factor 2 of the second output transistor Q2 is 12==-(VO-V2), it follows from equations (2) and (15).

Here, the emitter currents of the first and second transistors Q5 and Q6 are sufficiently small compared to the emitter currents of the other transistors, and the change in current is also small (VBEs-VEE
6) Since kiO, equation (16) is ■2 in - (VB2VBE2e/BE4)
...(17).

Generally 1. In order to flow a bias current of 1u to the second drive transistor Q4 and the second output transistor Q2, VB=VBE2+VBE4+H/B (△:Vs
)o) (Since the bias voltage vB is determined,
126-△VB>0.

That is, the second output transistor Q2 has an input voltage of
Regardless of S or load RL, it always maintains an active state,
It turns off and performs class A operation.

As is clear from the above operation analysis, the second output transistor Q2 always maintains an active state regardless of the input voltage VS or the immediately preceding state, that is, performs class A operation, and its output voltage Vo is (15 ), Vo = vS--VS in (VBE5-VBE6), which is independent of the emitter resistor r1 load RL and the base-emitter voltage VBgn of each transistor Qn.

For example, for a positive direction input, the first drive transistor Q3. The emitter current of the second output transistor Q1 increases, and as a result, the base-emitter voltage VB
E3, VBEI increases, and the emitter voltage ■1 of the first output transistor q1 decreases, but a current (I3 -I4) to the first resistor 1 (31), that is, as expressed by equation (14), a voltage (first term) proportional to the input voltage VS and the first and second drive By adding it to the first bias voltage VBI as the base-emitter compensation voltage of transistors Q3 and Q4, components that depend on the base-emitter voltage of each transistor, emitter resistance and load that appear in the output voltage VO (conventional example) (This dependent component is removed.

Next, when a negative signal is input as the input voltage VS (
12) When It, I4 > 13), it can be analyzed in the same way, and the current of (14-13) flows through the second diode D2.
The voltage flows through the second resistor R32 through the resistor R32, and a voltage of Δ:V=R32(I4-I3) is generated across the resistor R32.

That is, △V knee VS + (VBE2 - VBEI + VBE4 - VB
E3) l(L) or the second bias voltage V as the bias compensation voltage.
It is added to B2.

As mentioned above (according to this embodiment, the output voltage is independent of the emitter resistance, the load, and the base-emitter voltage of each transistor, and class A operation is performed.
The distortion component caused by the nonlinearity of the base-emitter voltage of each transistor can be significantly reduced, and since there is no discontinuity in the boundary region between the class A and 133 drive regions as in the conventional case, bias setting is easy. , crossover distortion and notching distortion characteristic of B drive operation are also significantly reduced. Furthermore, the fact that the output voltage is constant regardless of the load impedance means that the output impedance is zero, which means that it is an ideal constant voltage source and is not easily affected by the load. There is an effect.

FIG. 3 shows another embodiment in which a current mirror circuit is used in place of the first and second diodes Dz and D2 in the embodiment of FIG.

In Figure O, connect the emitter to the positive power supply through the resistor &amp;
The base 8 of the transistor Q1+ connected to CC is connected to the base 8 of the transistor Q8 of the first current mirror circuit (1) to form a third current mirror circuit (3), and similarly, the emitter is connected to the negative terminal through the resistor k. Power supply of -V
A fourth current mirror circuit (4) is formed by connecting the base of the transistor Q12 connected to the base of the transistor Q12 of the second current mirror circuit (2). Current mirror circuit (3)
, (4), the collectors of the output side transistors Qll, Q12 are connected to the bases of the first and second drive transistors Q3, Q4, respectively, and the emitters of the output side transistors Q11, Q12 are connected to the second drive transistors Q11, Q12. , are connected to the collectors of the output side transistors Q9 and Q7 of the first current mirror circuits (2) and (1), respectively.

Next, to explain the dynamic r', as in the embodiment shown in FIG.
If Ichihara I3-14 is flowing through the resistor R2, then the first and second current mirror circuits (1)
, (2), a current I3.14 flows through the collector of the output side transistor Q7, (29), and a current I3.14 flows through the emitter of the output side transistor Q11 of the third current mirror circuit (3), Only the current 4 flows into the collector of the transistor Q9.Therefore, a current 15-14, which is the difference between the currents I3 and I4, flows into the collector of the output transistor Qll, and this current flows into the collector of the transistor Q9.
31, and △■-
Technique 51 (I3-I4) A voltage is generated. On the other hand, the resistor k connected to the emitter of the transistor Q i 2 is connected to the transistor Q7.
Current ■3 is supplied from the collector of , and the voltage drop I
AR is occurring. This voltage drop is caused by transistor QI
The voltage drop due to the resistor k connected to the emitter of O is L4. Since R is larger than R, transistor Q12 is in the cut-off state.

For input in the negative direction, I4>13, and the current mirror circuits (1) and (3) are replaced with current mirror circuits (2) and (4), and the current mirror circuits (2) and
Similar results can be obtained by replacing (4) with current mirrors (1) and (8).

That is, the third and fourth current mirror circuits (3), (
4) uses the subtraction function of the magnetic currents 13 and 14 together with the subtraction function of the first and second diodes D1 and D2 in FIG.

FIG. 4 shows a specific circuit example of a power amplifier to which the embodiment of FIG. 2 is applied.

As described above, the present invention provides a positive side first drive transistor Q3, a first output transistor Qz, a negative side second drive transistor Q<, a second
The first and second output transistors Ql and Q2 of the output transistor Q2 are connected in series via resistors r and r, and the midpoint of the connection of the series-connected resistors r and 1° is connected to the output terminal. In a configuration in which positive and negative first and second bias voltages VBI and VB2 are applied to the bases of the first and second drive transistors Q3 and Q4, respectively, a voltage proportional to the human power cycle pressure VS is applied. , the first and second drive transistors Q3, Q'40 voltage of the difference in magnetic pressure between the base and eminter, and the first and second output transistors Ql.
, the voltage of the sum of the voltage difference between the base and emitter voltages of Q2 is set as the bias compensation voltage, and when the bias compensation voltage is positive, the bias m compensation *pressure is negative. In the case of the above second bias voltage VB
The output voltage with respect to the input voltage is independent of the emitter resistance, the load, and the base-emitter voltage of each transistor, and since it operates in class A, there is no crossover distortion. In addition, it not only operates as an ideal constant voltage source, but also reduces the distortion components caused by the nonlinearity of the base-emitter voltage of each transistor, especially the output transistor. Has excellent advantages.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the main part configuration of a conventional power amplifier, FIG. 2 is a diagram showing the main part structure of the power amplifier of the present invention, and FIG. 3 is a diagram showing the main part structure of another embodiment of the same. , FIG. 4 is a diagram C showing a specific example of the circuit. Ql, Q2, Q3, and Q4 are transistors, r is a resistor, and VBI and VB2 are bias voltages. Part 1, Figure 2, f 4 ' Figure 3 Procedural amendment (voluntary) June 104, 1980 Dear Commissioner of the Patent Office 1 Indication of the case 1981 Patent Application No. 62583 2 Name of the invention Power amplifier 3 , Relationship with the case of the person making the amendment Patent applicant Address 572 Sho 1 Temple! 6'g1N #Nunogaichi 1-1 Name (027) Onkyo Co., Ltd. Representative
Takeshi Godai 4, Agent Address: 2-1-7 Nisshinmachi, Neyagawa City, Osaka Prefecture 572
Contents of amendment f+) "(VBEl-VBE2+VB--VBE4)(13)" from page 12, line 14 to line 20 of page 12 of the specification
is corrected as follows. "-(VBE□-VBE2+VBE3-VBE4)
-(+3) J(2) As noted in the copy of the attached drawing, the sign of the resistor connected to the emitter of the first transistor Q5 in FIG. 4 is corrected to "R1" instead of "Pl". that's all

Claims (1)

[Claims] The first drive transistor Q3's on the positive side connected in multiple stages in Darlington, the first output transistor q1, the second drive transistor Q4 on the negative side, and the first and second output transistors of the second output transistor Q2. Ql, Q
2 are push-pull connected through series-connected resistors r and r, and the connection midpoint of the series-connected resistors r and r is used as an output terminal, and the positive side of the bases of the first and second drive transistors Q3 and Q4 are connected to each other. , negative side first and second bias voltages VBI
, VB2 are applied, the force city pressure v
A voltage proportional to S and the first and second drive transistors Q
3, the voltage of the difference between the base and emitter open voltage of Q4, the first
, the phase voltage with the voltage difference between the base-emitter voltages of the second output transistors Ql and Q2 is set as a bias compensation voltage, and if the bias compensation voltage is positive, the bias compensation is applied to the first bias voltage VBt. A voltage amplifier characterized in that when the voltage is negative, it is added to the second bias voltage VB2.