JPS59187230U

JPS59187230U - solid state delay element

Info

Publication number: JPS59187230U
Application number: JP7813483U
Authority: JP
Inventors: 和夫山中
Original assignee: キンセキ株式会社
Priority date: 1983-05-26
Filing date: 1983-05-26
Publication date: 1984-12-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の固体遅延素子本体の構造を示す正面図、
第２図は端子台を示す斜視図、第３図は素子本体を端子
台に支持した様子を示す斜視図、第４図は本考案の一実
施例に用いるフレキシブルプリント基板の構造を示す斜
視図、第５図は素子本体を示す斜視図、第６図および第
７図は素子本体をフレキシブルプリント基板に取り付け
た様子を示す斜視図、第８図は端子台に支持した様子を
示す斜視図、第９図は断面図である。１１・・・遅延媒体、１２・・・入力用トランスジュー
サ、１３・・・出力用トランスジューサ、１５・・・リ
ード端子、１６・・・端子台、２１・・・圧電セラミッ
ク板、２２・・・電極、４１・・・フレキシブルプリン
ト基板、４６・・・プリント配線。Figure 1 is a front view showing the structure of a conventional solid-state delay element body;
Fig. 2 is a perspective view showing the terminal block, Fig. 3 is a perspective view showing how the element body is supported on the terminal block, and Fig. 4 is a perspective view showing the structure of a flexible printed circuit board used in an embodiment of the present invention. , FIG. 5 is a perspective view showing the element body, FIGS. 6 and 7 are perspective views showing the element body attached to a flexible printed circuit board, and FIG. 8 is a perspective view showing the element body supported on a terminal block. FIG. 9 is a sectional view. DESCRIPTION OF SYMBOLS 11... Delay medium, 12... Input transducer, 13... Output transducer, 15... Lead terminal, 16... Terminal block, 21... Piezoelectric ceramic plate, 22... Electrode , 41...Flexible printed circuit board, 46... Printed wiring.

Claims

[Scope of utility model registration request]

A solid-state delay element in which a plate-shaped delay medium to which an input transducer and an output transducer made of piezoelectric transducers are fixed is supported on a terminal block equipped with lead terminals, and both of the transducers and the lead terminals are electrically connected. A flexible printed circuit board is arranged so as to wrap around at least three sides of the delay medium, including both sides, and electrical connections between the two transducers and the lead terminals are made by printed wiring on the board. solid state delay element.