JPS59184870A - Bit pattern generating device - Google Patents

Abstract

PURPOSE:To improve a bit pattern generating speed by a simple constitution by updating a buffer memory in which a pattern data is stored, asynchronously from a bit pattern operating means. CONSTITUTION:A pattern data from an MT (magnetic tape) controller 131 is stored in a buffer memory 136 through an FIFO (first in first out) memory 147 and an FIFO address register 148. A CPU137 executes an access to the memory 136, decides whether its pattern ends generation and becomes unnecessary or not by basing on a present value of a Y axis, and stores its address in the register 148 in case said pattern is unnecessary. In case it is necessary to generate a pattern, the start point and the end point of a bit pattern are calculated, sent to a bit train converting part, and the bit pattern is outputted. The memory 136 is updated with a data of the memory 147 based on an address of the register 148 when the CPU137 does not use the memory 136.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention detects the presence or absence of pattern defects such as scratches and aging on the first mask used in the manufacture of semiconductors such as ICs and LSIs by using design data. The present invention relates to a mask inspection device for comparing and inspecting design data, and also relates to a device that automatically generates a bit pattern from design data.

[Background of the invention]

FIG. 1 is a schematic configuration diagram of a mask inspection device, which is a subject of the invention. The present invention relates to the bit pattern generator shown in FIG. The position of the bit pattern generator in the following will be clarified, and then the conventional technology of the bit pattern generator and its problems will be explained.

FIG. 1 is a schematic block diagram of a mask pattern inspection apparatus for determining defects in a photomask by comparison with design data. In FIG. 1, the pattern on the mask 109 to be inspected is formed by the objective lens 108' by the transmitted illumination source 118.
The video signal 105a is provided as a pattern image on the COD linear sensor 105 through the F, and the video signal 105a is binarized by the binarization circuit 106. Now, assuming that the pattern that falls within the scanning width (one page) of this CCI) linear sensor 105 is as shown in FIG. 2, the reference signal to be compared is also
In synchronization with the scanning of the COD linear sensor 105, it is necessary to generate a so-called Jt pattern, which is a binary time series such that a certain part of the pattern is "l" and the background is rOJ. Therefore, as shown in FIG. 1, pattern design data 100a as shown in FIG. ...Only the vertex coordinates of Pn are written) as a temporary buffer memo! J
The stored data is read out at high speed and input to the bit pattern generator 102. The bit string pattern synchronized with the COD linear sensor 1051 described above is generated in real time by this bit pattern generator 102.
I can pass. The mask detection bit string pattern 106a that is the output of the binarization circuit 106 and the reference bit string pattern 102a that is the output of the bit pattern generator 102 are
are cut out by pattern cutting circuits 107 and 103, respectively,
A comparator 104 determines whether the pattern of the mask 109 to be inspected is good or bad.

In FIG. 1, 8, 110, 111, and 112 are an X-axis moving stage, a Ys moving stage, and a θ (rotation) axis moving stage, which are driven by an X motor 113, a Y motor 114, and a θ motor 115, respectively. The position of the mask 109 to be inspected is arbitrarily set. Further, 116 and 117 are respectively X-axis moving stages 110
and Y@ is a laser length measuring device that measures the amount of movement of the moving stage 111.

Now, the pattern design data 100a supplied from the magnetic tape 100 is a word PWl whose valley word has a data width of 16 bits as shown in FIG. 3(a).
It has a data format in which 5 words of data consisting of -P
Vertex coordinate values XI, X2, Xa, Yl, Y2 for the axis pattern and diagonal pattern as shown in C), respectively.
.

Ya, angle A with respect to the X axis, etc.

Therefore, especially in a diagonal pattern as shown in FIG. need to be calculated.

Conventionally, such processing has been realized using a hardware configuration as shown in FIG. In other words, the pattern P1 to be generated. The processing for each of P2...Pn is performed by assigning it to one of the logic circuit boards 1201, 1202... 120n. When (a)) is input, the processing for that pattern alone is executed exclusively until the generation of that pattern Pl is completed, and the start point address Xs and end point address Xe for the Y axis are calculated.

All functions as the bit pattern generator 102 are performed by a substrate 1202 that is the same as this substrate 1201.
Pattern P1. which needs to be generated during scanning of CD linear sensor 10501. This can be satisfied by preparing as many as P2...Pn and operating them all.

Each board includes a register 121 for storing pattern data for one pattern, and a register 121 for storing pattern data for one pattern.
By moving the axis, the start point address Xs or the end point address Xe
Addition/subtraction operator 122 for calculating or subtracting the value of
and the address Xs.

COD scan clock 105 bit pattern between Xe
It was roughly composed of a timing gate 123 for outputting in synchronization with b. Although such a configuration has the advantage of being simple in concept and easy to understand, on the other hand, the pattern data width is as large as 16 bits, resulting in a relatively large logic circuit scale and a large board size. Shi7! J) also
As the degree of integration of LSIs increases and patterns become increasingly finer, the number of patterns that must be generated during CCDI scanning continues to increase. In fact, in the conventional method shown in FIG. 4, the number of substrates is one to one with the number of patterns, so several hundred substrates are required.

This not only increases the scale of the equipment below the bar, but also imposes restrictions on speed during data transfer.
The amount of adjustment man-hours required to get the equipment up and running is unacceptable.

Furthermore, since only one pattern that carries a tumor is processed using the function of one substrate, when another pattern is generated during one CCD scan, the execution efficiency is extremely low, as it idles without any function. was.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art described above, increase the bit pattern generation speed, and provide a bit pattern generation device that is compact, can be realized at low cost, and does not require adjustment man-hours, and has high execution efficiency. be.

[Summary of the invention]

The present invention comprises three storage means, four calculation means and a conversion means,
That is, a first storage means that stores several pieces of data 8a defining a pattern, receives the pattern data stored in the first storage means, and determines whether the generation of the pattern has ended or will eventually become unnecessary. If the determination result is completed or unnecessary, the generation point data and end point data of the pattern are calculated, and if the determination result is completed or unnecessary, the address of the first storage means storing the pattern is calculated. a second storage means for storing the address outputted by the calculation means; and a second storage means for storing new data to be input into the space in the first storage means based on the determination result of the calculation means. 3 storage means, and a conversion means for converting the data into a plurality of bits based on the calculation results of the generation point data and end point data of the pattern by the calculation means l, and the calculation means has a first storage means. When the means are not in use, the data in the first storage means and the third storage means are simultaneously read out and the data stored in the second storage means are stored at a predetermined address of the first storage means in the third storage means. It is characterized by being configured to input data.

[Embodiments of the invention]

The present invention will be explained in detail below with reference to embodiments shown in the drawings.

FIG. 5 shows a schematic configuration diagram of a bit pattern generator according to the present invention. In order to achieve compactness, which is one of the purposes of the present invention, it is constructed using a multi-CPU module system, and the n CPU modules share and process patterns to be generated during the CCDI scanning period. .

The pattern data 100a in the magnetic tape 100 is the first
The pattern data bus 139 is output from the MT controller 131 including the buffer memory 101 shown in the figure.
, control bus 1401Y (Y@position coordinate value of the moving stage 111 in FIG. 1) bus 141 and X (position coordinate value of the X-axis moving stage 110 in FIG. Modules 132-134f are transferred. CPU module--
All of the files 132 to 134 have the same configuration, and buffer memory stores the number of generated pattern data to be processed. J136, UPU 137 that calculates the bit string pattern output start point address Xs and end point address Xe of the generated pattern from the stored data, and the scanning clock 105b of the CCD linear sensor 105 using the addresses Xs and Xe.
Among the pattern data in the bit string converter 1383 and buffer memory IJ 136 that outputs a bit string pattern in synchronization with the pattern generation, the pattern data that is no longer needed after pattern generation is replaced with new data to be generated and processed next. , and a data update unit 135 that receives new data and updates the same data in the buffer memory.

The CPU 137 has tauA and CotA calculations required for processing the diagonal pattern shown in Figure 3 (C).
Taking into account the fact that the angle A is limited to a certain extent, the contents can be changed to -j"-'
) Toshi”'C-written ROM (Read 0nly
MemOry) 8 are provided.

The pattern data from the MT controller 131 is randomly distributed to the CPU modules 132 to 134 having exactly the same configuration, as shown in FIG. 3(b).

As shown in (C), the calculation of the addresses Xs and Xe necessary to generate a bit pattern at Yi is completed within one scanning line of the COD IJ near sensor of Yi-1.
Must be. Therefore, by reducing the number of processing steps as much as possible, the number of patterns that can be handled by one CPU module increases, and the number of CPU modules can also be reduced.

Under the constraint of processing many patterns during one scanning time of the COD linear sensor, the most important requirement is to remove unnecessary data in the buffer memory 136 from the CPU.
' This means replacing the data with new data without incurring the burden of 137.

In other words, the number of steps for updating buffer memory data can be eliminated, and the buffer memory can be updated without CPU management.
It is necessary to be able to update on days and evenings within 36 days.

The key point of the present invention is that it is realized by a CPU module composed of components that satisfy these conditions. Hereinafter, the buffer memory data update unit 135, which is the main point, will be explained in detail.

In FIG. 6, data sent from the MT controller 131 is stored in a first-in first-out memory (generally F
O: First Ih First Out (hereinafter abbreviated as FIFO).
They are temporarily stored so that they can be retrieved in the order in which they were input. now,
This is referred to as F I F O-D 147.

The buffer memory 136 is shown in a link form to represent that it is always addressed in a circular manner to process the stored data.

At this time, the CPU 137 accesses the pattern data through the processing pointer 56 (this pointer is a concept).
Based on that data and the current Y-axis value Yi, it is determined whether the pattern has finished generating and is no longer needed, and if the data is no longer needed, the pattern data is stored. The address of the buffer memory 136 that is being stored is stored as data in the FIFO-A 148.

On the other hand, if the data requires the generation of a long pattern, calculation processing for the start point and end point addresses Xs and Xe of the bit pattern is executed. The bit string converter 138 uses these addresses Xs and Xef to output the bit pattern 102a in synchronization with the CCD scanning clock 105b. Note that the address data of the buffer memory 136 stored in the FIFO-A 148 corresponds to a kind of vacant room number of the buffer memory 136.

As described above, the memory address and new data for data update of buffer memo 'J136 are stored at each /rFI.
This means that it has been i-recorded in Fo-A 148 and FIFO-D 147. And when updating data, both FIFOs
By appearing at the same time, F I F O-A 1
21 buffer memory 136 directed to address 48
0 At this address, new pattern data of the FIFO-D 147 is stored, which can be written through the MA pointer 55. Kokote some DM A
(Abbreviation for Direct MemoryAcceSS, which means block transfer of data between memories or other devices without CPU management).

In general, a method called DMA is used to transfer or receive data without the control of the CPU 137, but this is mainly used to transfer or receive data of a certain size (the size of the data does not matter). ) This is a method of sending data using something called an iDMA controller, and when data is being transferred from memory, the CPS registers the start address and amount of data, and monitors the status signal to see if the transfer has been completed or not. It is. However, in the configuration for achieving the object of the present invention, as the COD scan moves from top to bottom, pattern generation starts from A→B-)C, as seen in the example of pattern generation in Figure 87. However, the timing at which the pattern generation ends is A −+ C−>
They are in the order of B. The buffer memory 136 of the CPU module 132 and all other CPU modules shown in FIG.
Assuming that the buffer memories of the PU modules 133 and 134 are all filled to capacity, the pattern data to be generated next, Q, is changed from Alp to P or , C must be discarded and replaced with R. In this way, the timing at which data must be discarded and the address of the buffer memory 136 where the data to be discarded are stored are scattered here and there in the buffer memory 136 in a so-called worm-eaten state, making it difficult to judge. When attempting to handle such processing, the conventional DMA system requires many CPU management plans.

However, since the data from the MT controller 131 is in a multi-CPU module format, it is difficult to know when and how many children will be sent.
Since it is not possible to input more data into the PIFO-D 147 than the number of data registered in the FO-A 148 (the number of vacant rooms), the data must be managed.

This means that if more data than necessary is accepted, the data to be processed will not be stored in the buffer memory 136, and the processing of patterns that should be generated in synchronization with CCD scanning will not be completed in time. This means that a tube burial will be required.

In addition, in general 1) MA controllers, the registers that can register the data transfer start address and data register are configured with the intention of handling one block of data. If we try to use this forcefully, considering the case where all the patterns are updated at once, the number of patterns that should be generated during one CCD scan, that is, hundreds of controllers will be required, which is unrealistic. becomes.

FIF solves the problems of the conventional DMA method as described above.
The problem is completely solved by using the two in combination. In other words, FIFO takes advantage of the fact that stored data can be retrieved at any time in the order in which it was stored, regardless of the amount of data. The only external hardware required is one that simply knows the number of data stored in the FIFO-A I48 and controls so that no more data than that is input to the FIFO-JJ147.

In the example of FIGS. 6 and 7, when the CCD scan is at the YiO point, the pattern data of A and C are now the new data P and R.
It represents the state just before it is about to be updated. iI
' IFO-A 148 stores the addresses (0) and (2) of patterns A and C that are no longer needed in the order in which they become unnecessary, and
bar turn data P and R are stored in the order in which they should be generated next.

As can be seen from the above explanation, the CPU 137 performs the work to update buffer memory data in the process of always accessing the memory for data processing. , sending that address being accessed to the FIFO-A 148 is no longer required.

I believe that the present invention lies in its ingenuity in that it is constructed using a method that can efficiently rewrite such data.

FIG. 8 illustrates an example 8 of a pattern to be generated in synchronization with the detected pattern signal. Now, A, B, C and 1), E, F 3 and L, M as shown in Fig. 8(a).

When considering that the pattern of M machine images synthesized by each of N images is generated in synchronization with the COD linear sensor 105 within one page width of CCD scanning, the pattern to be generated is as follows.
The pattern must be similar to the bit pattern generator total output 102a shown in the same figure (el) synchronized with the CCD scanning clock 105b as shown in FIG. The background is 'O"
This is a bit string pattern such that However, it is not a big problem whether the inside is 11" or the background is 10"; it is a matter of expression, and the reverse is also possible.

In the example of Figure 8, the first CPU module handles patterns A, E, and F as shown in Figure (b), and the second CPU module, 7 Joules, handles patterns A, E, and F as shown in Figure (C). The n-th CPU module takes charge of patterns C, D, L, and N as shown in FIG.
and M. If the outputs of all CPU modules are wired (D)L, the total output will be (
e) is obtained.

FIG. 9 is a detailed configuration diagram of FIG. 6. In the figure, M at the upper left
The T controller 131 controls the buffer memory 101, F
It is composed of an IF 0143, a FIFO controller 145, and a driver 144 for transferring pattern data to each CPU module 132-134.

The data update unit 135 of the CPU module 132 uses a data receiver 146 that receives pattern data sent from the driver 144 through the CPU module external bus 130, and temporarily stores the data in the order of input (F
The IFO-D 147 temporarily stores the address where unnecessary data is stored in the buffer memory 136 as data.
Number of stored data in 8 or LL'ii;'0-A 148
'0-' on Fi using the output data as the address
D Do you have pattern data for 147? F'IFO controller 14 that controls memory 136
It consists of 9.

On the other hand, the 'CPU 137 is divided into a data processing section centered on the processing sequence shown in the upper right part of FIG. 9, and the ALU 158 in the center right part.
I get kicked.

First, the sequence controller writes a pine pink memo 1J151 that instructs the entry point of the instruction register 150 and microblock memory 153.
, a sequencer 152 that generates a 10-crum sequence 1frlJ11ii1 according to the status signal and each building judgment condition.
, a microprogram memory 1538 that stores blocks for executing arithmetic processing for each pattern, and a vibe line register 1 used to increase execution speed.
54.

On the other hand, the data processing section is an A that performs arithmetic and logical operations.
L U 158 , the status controller 157 generates a signal that changes the flow of the sequence as a status 173 and passes it to the sequencer 152 , as shown in FIG. Angle table OM 1 provided so that jan and cot data for angles can be obtained as a table
60, a dedicated multiplier 159 provided because it takes too much processing time in software, a buffer memory 155 for use as a working register during arithmetic processing, etc.;
A memory address controller 156 for accessing the buffer memory 136 storing pattern data and the buffer memory 155, CCs the start point address Xs and end point address Xe of the bit pattern as shown in FIG.
L) XSL/Jister Xs R161 generated in synchronization with the scanning clock 105b and sent to the bit string f conversion unit 138;
Xe register XekL162Xs, Xe f XS)
+1, set to XeR in bit string converter 1
F/F (flip-flop) 163 that generates a Ready signal 174 to signal 38 and four gates 168, 169 that control data input to two internal data buses, namely A bus 164 and B bus 165.
, 170, 171, and a gate 16 that switches between two inputs: the address input to the buffer memory 136 @FIFO-h14B and the memory address controller 156.
It is set in 7.

Y1 read by laser length measuring device 117! @The coordinate position is
Gate 168%fi is input as Y@ coordinate data by laser gauge counter 182 to B bus 165≦
When the Y@ coordinate data at that time is Yc, based on that data YC, search for data that is no longer needed after pattern generation has finished from the storage gauge of the first buffer memory 136, and find the address where that data exists. ni' I FO-
A 148 is written, and pattern data within the number of convoluted data is received at '0-D 147 on the FI.

-Then, C1-'U137 or Buffer Memo'J136
When the bladder is out or not, the FO controller 149
Under the control of FIFO-A148. FIFO-D14
7 at the same time and use the output data of FIFO-A 148 as an address to read FIFO-D 147.
＋Receive the pattern data received earlier "EnfaMemo I"
It is written to J136.

In addition, FIGS. 3(a), 3(b) and 3(C) respectively show the data format for one pattern from the magnetic tape 100. It was explained that it is a diagonal pattern with an angle A to the other hand. Here, for diagonal/N11 turn ζ as shown in Fig.
The formula for calculating the bit number turn start point address Xs and end point address Xe when Y = Yi in the D scan is as follows.

YN = Yl + (Xt - Xa) tanAl
Y) Ya: Xe =X1±(Ya-Yl)tanA-
(Y-Ya) cotA In the axis pattern as shown in Figure 3 (b), when Y is between Yl and Y2, Xs = X1+' Xe
= X2, whereas in the diagonal pattern as shown in FIG. 2C, Xs and Xe must be calculated for each value of Y using the above-mentioned formula. Xs, Xe obtained here
must be sent to the bit string converter 138 in FIG. 9, so the processing in FIG. 3 must be performed on Y one step before actually outputting the bit string pattern (Yi-1
).

FLG in Fig. 3(a) is expressed by 1 bit, and FLG=
1, the axis pattern as shown in the same figure (b), and FLG
When =0, a diagonal pattern as shown in FIG.

FIG. 10 is an actual processing flowchart for (b) and (C) in FIG. Among these, in the diagonal pattern, each vertex of the rectangle is represented by two bits.

Furthermore, since YN is not sent as data in order to reduce the number of pattern data, it is calculated at the beginning of the process.

Figure 11 shows the X58 of CPU 137 shown in Figure 9.
X5178.161 sent from XeR162. Xe
FIG. 179 is a detailed configuration diagram of a bit string conversion unit 138 that generates a bit string pattern output 10 addition to the original bit string pattern. However, F
The handshake circuit with CPU 13.7 through /F163 is omitted.

In FIG. 11, 10-bit width data X5178. Xe179 Temporarily memorized S
- register 184 and E-register 185 are provided at the input section. Comparator (S) 186a and comparator (
E) xs6b is the upper 6 bits of S-register 184
10 operated by 5H198 and counter CLK209
Upper 6 bits of bit binary counter 197 1-XC
Upper 6 bits of NT2O8 and E-register 185
Compare the size of eH2O0 and the above XCNT2,118, and find respectively XSH = XCNT2O2 and ) (6H) XCN
T2O3f) (!: Outputs output signal 11".A N
D 187 is the lower 4 bits of the S-register 184
5L199 is provided with a gate at X5n=XCNT202, and when XSH:=:XCNT, XSL remains as *'kc OM2B5 lower address AO to A3 input AL 204, but
In XcNr, all 4 bits of AL are '0'.

On the other hand, OR188 is configured to give an OR input to each of the lower 4 bits XeL201 of E-register 185 with XeH>XCNT2O3, and Xen>XCNT
.

When the OR output output H205 is all 4 bits 11'', it is given as the upper address A4 to A70 input of the ROM 189.On the other hand, if XeL≦XCNT, ' is Xe
L201 continues through Obon 188 and 1. )j, OM is given to A4 to A7 as upper address input AH.

) (, OM 189 has 8 bits of address input and 1 output
It has a 6-bit configuration, and data as shown in FIG. 13 is written in advance. In Figure 13, everything is expressed in hexadecimal codes, and blank spaces are not used (
(not accessed) part. ROM output data 20
6 is written to RAM (1) 191 and RAM (2) 192 through zero 190. This is because when writing data to RAM(1) 191, data can be read from KAM(2) 192, and vice versa.

RAM(1)191. The output of RAM (2) 192 is the register (1) 193, register (2) 19
4, and the data is temporarily stored in C by switch S3.
The signals are alternately switched for each CDI scan and input to the parallel to serial shift register 195. ROM 189
Since the output data directly represents the obit string output pattern, the bit string pattern output 102a is obtained via the output buffer 196 by serially reading out the shift register 195.

OR190 is provided so that patterns can be overwritten through switch S2z.

The counter output XCNT2O8 is Y=Yi-1, which is one point before the Y coordinate Y=Yi where the pattern is actually generated.
In order to create the occurrence pattern at i, RAM(1)
191. It is also used as address data for RAM(2) 192. On the other hand, RAM reading at Y=Yi is synchronized with the CCD linear sensor 105.
The upper 6 bits 183° of the OD scan address are stored in RAM (1
) 191 and kLAM(z) 192, and can be switched to XCN 7208 by switches 84 and 85, respectively.

The operating principle of FIG. 11 is shown in FIG. 812. Xs, Xe,”
Since the CCDI scanning width is currently considered to be 1024 bits, each data is 10 bits long. So 1024
- When divided into 164 blocks (6 bits),
Both s and Xe are located somewhere in the 64 blocks. It is possible to create a bit string pattern like the one shown in (see top of page). Note that X5L19 of pattern (A) in Figure 12
9 is 'B'', i.e. )l, the lower address AL to OM 189 is 'B'', and Xer-20115''
, that is, the upper address to the ROM 189, address 8H, is an example of 15''.Furthermore, at this time, blocks 5 and 6 are all 1.
1", blocks O~3.8~63 are all 10
If filled with ", the pattern output shown in the center of FIG. 12 (A) is obtained. At this time, the boundaries of the valleys of Xe
Both are given by the lower 4 bits of the 10 bits, so
This 4-bit data '0''~%p//<hexadecimal notation) is used as Xs in the block.

FIG. 13 shows the patterns that Xe can take.

However, as shown in Fig. 12, if Xs and Xe are not in the same block and there are adjacent blocks or several blocks in between, it is necessary to fill that block with '1'. What is realized is OR18 in Figure 11.
8 and A N D 187.

That is, since the above-described processing only needs to be started from a certain block of Xs, X5H198 is written to the upper 6 bits of the counter 197 as a block of Xs. At this time, since XSH=XCNT, the lower 4 bits of Xs, which have more detailed positional information within the block of Xs,
9 is input as is as the lower address AL of the ROI block 189.

Now, if Xe is in the same block as Xs, comparator (B)
186b, XeH>XCNT is output,
The lower 4 bits of Xe are also input as is as the upper address AH of the OM 189. Therefore, the output pattern from the ROM 189 at that time is AL,
A pattern of hoΔ4 addresses determined by AI() is output.

On the other hand, in the example of FIG. 12, since XeH>XCNT, the ratio M
a-CB) 186b and U Oli, 188 (1)
The 4 bits of the action AH are all 11", and the 13th
From the figure, we get X8L = B / ri: 1 as F2O3 (hexadecimal display) as the value of 4 blocks, and then the counter increases by 197, and when Xeu = XcNr, it becomes 186b. Since Xei+>XCNT is not output, Xer becomes the 77AH data.

On the other hand, the comparator (S) 186a
Since T is also not output, Xsr and data are AND18
7, all are prohibited, and all ALs are 10".

Now, if we set XeL==5 as in the example in Figure 12, the first
From FIG. 3, 003F (in hexadecimal notation) can be accurately obtained as the value of the seventh block. and block 5.6
, AL is all %o", AH is all '1'/c!: Therefore, it becomes FFFF (hexadecimal display), and all are filled with 11", and the (A) pattern output in Figure 12 is obtained. That will happen.

Similarly, processing can be performed for pattern (B) in FIG. 12, but (A) pattern @ RAM (t) 19
1 or g A M (2) After writing in 192, (1
3) If the pattern data is written as is, '0' will be written from the beginning of the 6th block where Xs of the pattern (h') exists to the bit where X8L exists, and '1' written with the pattern (A) “Since the information will be rewritten, in order to prevent this, the data is returned to the OR190 through the 11th switch S2, and the previously written '1''
It is configured so that information is not deleted. At the beginning of scanning the CCD 17, the contents of the RAM (1) 191 or RAM (2) 192 to be written from now on are all cleared to 10''.

) L A M (1) 191, k! JA M (2)
192 each have a capacity of 16 x 64 = 1024 bits, and while outputting one RAM data to the shift register 195, data necessary for the next CCDI scan is written to the other 1 (IAM).

By wiring the bit string pattern output of the CPU module obtained with the above configuration with the output of another CPU module, the output as the bit pattern generator of the mask inspection device described in this embodiment can be obtained. That will happen.

In the mask inspection equipment, C and CD are scanned at high speed.
The design data must be generated by converting it into a bit string pattern in synchronization with the linear sensor, and in order to miniaturize the pattern generator, the processing content becomes complex, so arithmetic processing by the CPU 'U is required. . In order to increase the speed under these conditions, it is essential not only to reduce the number of pattern calculation processing steps inherent in the CPU, but also to configure the peripheral circuits so as to reduce the burden on the CPU as much as possible. In general, as in this embodiment, the number of patterns that can be processed by one CPU module within one CCD scanning time directly determines the required side and number of CPU modules, and the equipment size and equipment cost are determined. affect.

Regarding this purpose, the role played by the present invention in the third embodiment is important in realizing an apparatus with high processing speed and small scale.

[Effects of the Invention] By adopting the present invention, the conventional bit pattern starting method is improved, and the bit pattern/generation speed is improved by 5.
The equipment size is approximately 8,000 yen, the equipment cost is approximately 3,000 yen, and the number of adjustment man-hours required for the equipment 8 years has been reduced.Furthermore, since it uses CPU processing, it is impossible to do it with the conventional /"%-doware fixed processing. It has become possible to deal with changes in the format of pattern data, and the 6T VTE has become a highly functional bit pattern generator that generates bit patterns in real time in synchronization with CCD foot movements.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of the subject of the present invention and a schematic diagram of the inspection device, Fig. 2 is an example of the scanning pattern of the CD IJ near sensor, and Fig. 3 (a), r (b), and (C) are respectively Design data format - Axis pattern and diagonal pattern diagrams; Figure 4 shows the S factor of a conventional bit pattern generator; Figure 5 is a schematic diagram of the bit pattern generator of the present invention; Figure 6 is a diagram of the present invention. A conceptual diagram explaining the memory data update unit, which is an important 7.1" element in constituting the invention, FIG. 7 is a diagram showing different patterns with different termination orders, and FIG. 8 is a diagram showing the bits that should be generated during the CCDI scanning period. An explanatory diagram showing a pattern output format and a pattern shape example, FIG. 9 is a specific embodiment of the present invention, and a detailed block diagram of the inside of the CPU module in FIG. 5, and FIG. 10 is an axial or diagonal pattern X
Processing flowchart for calculating s, Xe, aL,
Figure 1 is a block diagram of the configuration of a bit string converter that generates a bit string pattern from Xs and Xe data in synchronization with the CCD scanning clock in an embodiment of the present invention.
An explanatory diagram explaining the functions and operations in Figure 1, Figure 13 is the same as Figure 11.
ROM 18 that generates the bit string conversion pattern shown in the figure
9 shows a conversion pattern data diagram. 102...Bit pattern generator 105...COD linear sensor 131...MT controller 132-134...CPU module 135...Data update unit 136...Neutsfer memory 137...CPU 138...・Bit string converter 139...Pattern data bus 147, 148...FIFO 149...FIFO controller

Claims (1)

[Claims] 1. A first storage means for storing a plurality of data defining a pattern, and receiving the pattern data stored in the first storage means, and determining whether the generation of the pattern has ended or will become unnecessary at some point. , If the judgment result is that the pattern is finished or unnecessary, calculate the generation point data and ending point data 8 of the pattern, and if it is finished or unnecessary, output the address of the first storage means storing the pattern. a calculation means, a second storage means for storing the address outputted by the calculation means, and a third storage for storing new data to be stored in the space in the first storage means based on the determination result of the calculation means. and converting means for converting the data into a plurality of bits based on the calculation results of the pattern starting point data and ending point data by the calculating means,
When the arithmetic means is not using the first storage means, the data in the second storage means and the third storage means are simultaneously read out and the data stored in the second storage means are stored at a predetermined address in the first storage means. A bit pattern generator having an 8-% resemblance to that configured to input data of a storage means of medicine 3.