JPS59181888A - Picture recording and reproducing device - Google Patents

Abstract

PURPOSE:To make a picture and an audio signal coincident with each other by recording a picture signal color change control signal to a prescribed position on an audio magnetic tape and reading this signal at reproduction so as to change display color of a reproduced picture of a color picture display device. CONSTITUTION:The 1st tape recorder 31a is selected to the reproducing mode and the 2nd tape recorder 31b is selected to the recording mode. Then, the user gives a color change control signal adding command to a color change control signal adding circuit 80 at a desired position while monitoring by a receiver 36 and a speaker 37. Thus, this circuit 80 adds the color change control signal to a digital data read from a memory 45 and outputs the result. The digital data has a delay for 4 picture elements' share by this addition, but the delay is cancelled by a silence part between lines because this is coincident with the count difference between a write counter 50 and a read address generating circuit 51. Thus, both signals are outputted to a tape recorder 31b.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention is applicable to, for example, an audio tape recorder.
An image signal consisting of a plurality of image information and an audio code with a fixed timing relationship of y-9r are recorded together with the specific image information of this image signal, and the specific image information is displayed on the image display device name. The present invention relates to an image recording main device which displays a state in which an image and an audio signal match each other on a screen of an image display system. [Technical background of the invention and its problems] Recently, image signals have been digitalized and recorded on magnetic tape for recording and reproducing audio signals, and this can be reproduced on a television receiver to produce static images at a very low cost. Still image recording and reproducing devices that allow users to enjoy images have been developed. Such a still image recording and reproducing apparatus (-Jl) is configured, for example, as shown in FIG. Each pixel of the video signal is digitized by an analog/digital converter (hereinafter referred to as ADC) 12 and stored in a memory 13. According to the control signal, the data of the ADC 13 is stored and the stored data is output from the output section to the input section of the recording section control circuit. For example, the well-known FS converts the data from parallel to serial.
The signal is recorded on a magnetic tape (not shown) by a tape recorder 16 for playing back audio recordings via a K (frequency shift keying) type modulation circuit 15. 1
9. This unit 1 control circuit 14 stores the digitized data of one frame of the video code in the memory 13 while detecting the operation of the image recording unit (not shown). The recorder 16 is put into a recording state and the data in the memory 13 is recorded on the magnetic tape of the FSKS Armed Forces.In contrast to the above-mentioned recording system, the playback system uses the playback signal taken out by the boot 0 recorder or the FSKS Armed Forces demodulation circuit. 17, it is converted into a serial digital data and supplied to the reproduction capital fl control circuit 18.The reproduction section control circuit I8 is configured to convert the data into a serial digital data and supply it to the reproduction capital fl control circuit 18.
Write for 9? ! In addition to outputting the j'J control signal,
By converting serial/parallel data and supplying the fcr total data, the digital data is made available. The memory 19 is controlled by the reproduction phase s'i+'l control circuit 18P (in other than the digital data writing state, the output state is 1), and all 7 digital data are outputted at high speed φC. This is the output 1 to a converter/analog converter (hereinafter referred to as DAC) 20.This DAC 20i converts the digital data 20 into analog information and outputs it to the receiver 2. As a result, the still image information of the magnetic chip f IIC is transferred to the received image t.
3U 21K is reproduced. This stillness ii! The recording format in the Deso recorder 6 of the II image recording and reproducing device is, for example, as shown in FIG. After being
- A plurality of image 1 code blocks that divide a still image into a number of frames, and correction information code blocks for error correction corresponding to these m·1 image signal blocks, and ρ＼ alternately record accents. It consists of In the apparatus shown in FIG. 1, the synchronization signal generation and error correction signal are generated by the recording section control circuit 14 and processed by the section control circuit 18. By the way, such a still image recording (the raw part 11'31
: If the tape recorder 16 is capable of stereo recording, both signals can be simultaneously recorded by recording one signal on the still image channel and recording the audio signal on the other channel. It is i'able to reproduce. Therefore, an example of the direct use of such a still image recording and reproducing device is to record the lyrics of a CS desire as an image/1 hour report on the main channel of a tape recorder7, and then record the melody corresponding to the lyrics as an audio signal on the tape. I decided to record it on the other channel of the recorder in advance.
;9.It is extremely suitable for use in so-called karaoke, which is popular among people. The user can sing along with the melody that is being played while referring to the lyrics that appear on each image, so there is no need for a lyric card, which was considered safe up until now, and it is very convenient. It will be good. However, such a still image recording and reproducing device has an extremely large amount of information, and the circuits 4 and 4 not only become a nuclear notification, but also
- It takes a lot of time to completely produce a still image. Therefore, if such l) one still image recording and reproducing device is applied as is for so-called karaoke,
For example, there are problems such as not being able to keep up with the display of lyrics for melody, and problems such as simply playing back text and 1t5 information, which is expensive. In order to reproduce text information,
Character information recording F in which the brightness level and color tone of each pixel display are roughened and error correction processing is omitted.
An image recording and reproducing device for live use was developed, and it became possible to display the lyrics at a sufficiently high speed compared to the playback speed of (-i melody). It is sufficient that the contrast is sharp, and even if some errors occur in the reproduction, the reproduced characters are sufficiently L/(1:f6-). And, as mentioned above, it is a record of both images that are insulting because of [']. The expression is a・lle(, which is used in Japanese, etc.), and it is expressed as ρ': '+34. This vertical text string crawling operation is used by Nagisa 7.
This is done gradually at an appropriate time to make it easier to see. By the way, the above-mentioned image recording and reproducing apparatus used for so-called karaoke is designed to make it easier to sing songs in the playback state. It would be convenient to have a singing display function that displays the beginning of the song. As such a function to display the beginning of a song, a method using a marker display has been considered. In other words, this method of marker display can be used, for example, to display the lyrics at the bottom of the receiver's screen. Display multiple 1114 band-shaped markers corresponding to the number of lines shown, and the autumn words are 1 for each line.
The above markers are displayed sequentially depending on the month when the first member is displayed, and when all the markers are displayed, the song starts singing ((This is what I did. Also, by the method of showing the office marker as in J-, 1] the f+jy territory ID D'j'
It is very difficult to match the timing of the number of lines and the timing of the beginning of singing. Therefore, this method 1'f Vb recording tape is not suitable for Vb recording tape. Therefore, II.
1Iji is composed of R and can be easily sung and shown.
<4 I was down. [The eye of invention is this?] , bright was created in consideration of the user's own needs.For example, it is suitable for so-called karaoke, and the timing of the image and audio signal corresponding to specific image information among multiple image information reproduced from a tape recorder is It is an object of the present invention to provide an extremely good image recording and reproducing device which has a simple configuration and can easily display a coincident state on a screen. [Summary of the invention] That is, both image records according to this invention 11) The raw equipment beach is
h1 for the audio signal and the audio No. 411
A means for recording on an audio magnetic tape a plurality of image signals to be displayed on a color image display device at a certain timing, and an audio signal and an image signal as separately described are recorded by this recording means. 1IiI, comprising a reproducing means for reproducing the audio signal and image No. 43 from an audio magnetic tape;
In the i-production recording and reproducing apparatus 1F', a first means for adding a color change control code to the image code at a predetermined location and recording it on the audio magnetic tape; a second means for extracting the color change signal during playback of an audio magnetic tape recorded by the means; and a color change read out by the second means. (According to the Go4 Car Issue 1) The reproduction of the B era color image display device is a sign that the color display of the Jlij statue will be changed. [Invention Dog] f11≦・Before explaining one embodiment of the present invention, an image recording and reproducing apparatus B to which the invention is applied will be explained below with reference to FIG. The output terminals of an encoder 32 and a signal source 33 are connected to the recording input terminals of two channels, L and R, of a tape recorder 31 capable of recording and reproducing data in a Z-L6 manner. Here, the encoder 32 is configured with a TV camera, and the text information (including color information such as text color, background color, etc.) obtained as a video signal from the TV camera is transferred to the tape. The image signal is converted into an image signal that can be recorded on the recorder 31. ,! , Tado Kihaku - Gen 33
An example is something that generates an audio signal such as music, such as a record player or tape recorder playback output section. As a result, each output signal of the encoder 32 and the IB signal source 33 is caused by the recording circuit 311 to run at a constant speed in the direction of arrow B in the figure via the recording heads 312 and 313 corresponding to the L and R channels. This is recorded on the a-capacity tape 314. The image signals recorded on the magnetic theno 314 (6L) are taken out by playback heads 315 and 316 corresponding to each of the L and R channels, and are reproduced by a playback circuit 317, for example. The reproducing output terminals corresponding to the L and R channels of this reproducing circuit 317 are respectively connected to the input sections of the decoder 34 and the amplifier 35, respectively. The decoder 34 converts the image signal obtained through the reproduction circuit 317 into a video signal (displayable) that can be reproduced (displayed) on a television receiver (hereinafter simply referred to as a receiver) 36. The shield/spanner 35 amplifies the audio signal obtained from the reproducing circuit 317 and drives the nubby car 37. Next, as shown in FIG. Without reference, the above encoder 32 will be explained.In other words, the video signal obtained by the TV left camera is sampled every period corresponding to one pixel and sent to the ADC.
42, then serial/-'1'
By parallel conversion circuit (hereinafter referred to as S/P circuit) 43, Hentai J moxibustion is fired by Larel de nocle data. Then,
The output data of the S/P circuit 43 is outputted to a write circuit 44 for a predetermined number of pixels and then stored in a memory 45 by the cutting circuit 44. The write address of the memory 45 is specified by a write address generation circuit 46 and is supplied to the address input section of the memory 45 via an address switching circuit 47. Then, the write clock outputted by the crawling clock generator 48,
The signal is from the synchronization signal generation circuit 49 of the TV Noyon E.
, the write counter 50 and the clock input terminals of the 872 circuit 43. The write counter 50 drives the wide write circuit 44 in a state in which digital data of a predetermined number of pixels is supplied from the 872 circuit 43 to the write circuit 44, and transfers these r' nockle data to the input section of the memory 45. It is designed to be supplied to The first half synchronization signal generation circuit 49 supplies a synchronization signal of the television signal to the TV left camera and first input address generation circuit 46. On the other hand, by selectively supplying the address generated by the memory address switching circuit 47 to the read address generation circuit 5 to the address input section, A digital signal of 1 to 1 is output to the fWa 13 circuit 520 corresponding to a predetermined number of pixels. The readout 1 output path 520 supplies the supplied 7' nockle data to the parallel/serial conversion circuit (hereinafter referred to as P/S circuit) 52 for each 1;a-order pixel. The serial digital data output from the p7s col kl'r, 52 is converted to the FS by the transformer circuit 53.
It is modulated by K and connected to the recording input terminal of the tape recorder 33 through the output terminal OP at 7"L. A read clock signal is supplied to each read clock signal by a read clock generator 54. The address switching circuit 47 is configured to switch to a corrupt address generating circuit by the flit control 1^ of the ?t'11 circuit 55. 46 and the read address generation circuit 51, respectively, and supply the same to the address input section of the memory 45.The write/read control circuit 55 also controls the difference circuit 44 and the read address generation circuit 51, although it is not shown in the figure. The digital data controlling circuit 52 can be read and read. Next, the decoder 34 will be explained with reference to FIG. That is, the demodulation circuit 56pζ is supplied with the image code reproduced by the tape recorder 31 via the input terminal Ip. This image (g) is subjected to FSK decoding, for example, by the demodulation circuit 56, and then S/P
The data is converted into seven-channel digital data via a circuit 57 and supplied to an input section of a memory 58. In the memory 58, a storage area is specified by address data generated by a write address generation circuit 59 and supplied through an address switching circuit 60'f; The stored digital data is written to a predetermined storage area. In this case, the S/P circuit 57 and the write address generation circuit 59 are supplied with a predetermined frequency of BLACK, RI, and 1 from the IS adjustment circuit 56.
The above-mentioned foot address generating circuit 59, the above-mentioned S/P circuit, and the above-mentioned S/P circuit 57 carry out the serial conversion of the digital data to a redundant state.
b: + control circuit 6) (in response to which the status/1o-4 indicating completion of serial/parallel conversion of the digital data is output. , 14
Including! It is controlled by the control circuit 1 thread 67, and the address data of the i5'c output address generation circuit 62 and the address data of the i5'c output address generation circuit 62 and the 'funagomi address valve generation circuit 59 It is generated by the address switching circuit 63 based on the r[li positive data that is reclaimed, and is designated via the address switching circuit 60 to the tj:rF area of the memory. Then, the digital data read from the memory is subjected to parallel/serial conversion and O/denochle/analog Y conversion via the P//Sl path 64 and the DAC (i5), and then to the mixing circuit 66 (described later). The address 4 generation circuit 62 is designed to be supplied to one input terminal of the synchronous signal generation I.
A predetermined address data cycle is generated based on the clock signal ζ], which is supplied from the first path 67. Further, the synchronization signal generation circuit 67 supplies the horizontal synchronization 4gg generation circuit 68 and the mixing circuit 66 to the television IK number Ii? Directly; υ [go is to be offered. The above-mentioned horizontal synchronization A No. 8 iF56B uses the horizontal synchronization (2'"Q) of the television signal based on the clock (No. 8) provided by the clock generation circuit 69 to the address switching circuit 6θ, the read layer control circuit This allows the mixing circuit 66 to supply a video signal (a TV signal) to, for example, the receiver 36 via the output terminal Ov. This is the same as ?'1.
8, the address switching I←l j'460 i''1111 is switched from the address correction circuit 63 to the address r output by the write address generation circuit 59, Is the above reading 5 included?
The path 61 is in a state of being ready to store digital data in the memory 58. This conjunctive eye, the memory π included is carried out in the 1st day of the effective image 100ga display period of the above-mentioned Uke 1 Elegance Handling 36, so the above-mentioned passive, 4 Ishinoro's 1 Kofff1i (+ the noise will not live) ,. In addition, "-Note P/S iI:・1roC) 4 and ()・
No. 110111 Ino "1 mi regeneration 4% 67 is set to ζ so that the clock signal which becomes 26! and τ' , J mixing circuit (i (i K is color synchronization (g + rack 6 raw mouth), which will be described later; the color synchronization signal is supplied to route 70, and S) is generated. By the way, as is well known, in video No. 48 played back on the receiver 36, not all pixel signal components are displayed on the screen of the receiver 36. , a part of which is off the screen and not displayed. For example, the effective screen of a cathode ray tube in a color television receiver is 320 meters in length when the video signal is an NTSC standard television signal. If it is divided into pixels, approximately 224 pixels will be effective, and the scanning line will be approximately 384 pixels.
The book is valid. Here, if approximately the same digital data is used for even fields in interlaced scanning, by storing 224 pixels per horizontal period and storing digital data for 192 periods per image, as shown in FIG. The self-made i-recording and reproducing device is capable of recording and reproducing good images. However, the device shown in FIG. 3 is designed to display a character string in Japanese or the like as described above. Therefore, if the decoder 34 is to display seven lines of character strings on the screen of the receiver 36, it is necessary to store a total of eight lines of character strings in one frame of the video signal. Therefore, the said memo in FIG. 5') 58 i'i,
It is designed to memorize 256 pixels for each of the 192 pixels corresponding to the effective screen size. In addition, the memory 58 is configured such that denotational data corresponding to four pixels is allocated to a storage area of one address, for example, in consideration of the access time. For this reason, the address number 1 of the memory 58, etc.
For example, as shown in FIG. 6, the storage area of the memory 58 is 192
6/4 = 12288, so there are 12288 addresses (for example, from address 0000 to 2 in hexadecimal 2 mode)
From the left, facing the top line of the effective screen, address oooo to 003F, the next line to address 0040 to 007Fl, and so on, each line corresponds to a predetermined address, and the bottom 2FC the side line
It is made to correspond to addresses 0 to 2FFF. Then, each line is divided into eight equal parts, the first row from the left,
This is done to correspond to the second line, . . . , and the eighth line. In this way, the digital data read from the memory 58 of FIG. After that, the signals are sequentially output from the first line and converted into digital analogs. As shown in FIG. 7, the pixel signals corresponding to the first to eighth rows output from the DACes are mixed with the horizontal synchronizing signal generated by the horizontal synchronizing signal generation path 68. become. For example, the TV left camera 1 of the encoder shown in FIG. It looks like this. . Accordingly, the encoder of FIG. 4 receives a plurality of pieces of image information and sequentially transmits digital data corresponding to each row stored in the memory 45, starting from the first row, by means of the skew address generating circuit 5I. For example, these data records are recorded using the FSK system as they are read out. As shown in Figure 58, the record menu of the encoder is as follows: (digital data of each row)
Naka(((1 row of 1 line without line) of about 0.5 seconds between 4 intervals, so that it is almost continuous.
Don't leave the image, continue

[: Even in the case of self-injection, the digital data section of the first line of the next image 1) and the 11th image (1)
Interposed in the digital data section of the last line of the block; l+c
The intervals between the signal portions are set to 0.5 seconds. When one continuous image is recorded continuously as a block, the intervals between the blocks are such that, although it is not shown in the figure, there is a no-signal period of about 1 second. ing. For example, as shown in FIG. 9, each row of digital data is recorded approximately in correspondence with the scanning line of the receiver 36, and for example, 32 consecutive pixels of digital data are continuously recorded as one line. The first to 192nd lines are recorded substantially continuously through one no-signal portion having a recording interval of 4 pixels. In addition, each non-Cj part in the above Noma, G is,
As will be described later, this signal is used as various synchronizing signals in the decoder shown in FIG. Also, as mentioned above, the V digital data is 1'/IJ
For example, it is FSK modulated and recorded on the i-movement tape 314 by the take 0 recorder 31 in FIG. Correspondingly, as shown in FIG. 10, 2 x 7 Hz and fHz recording (recorded and reproduced as Fj number) is performed.Next, referring to FIG. We will explain in detail the main parts of 7.1.
In Figure 1, parts that are the same as those in Figure 5 are designated by the same reference numerals.
Also omit p. That is, the write adreno 4. The raw circuit 59 is supplied with the image and [C] through the input terminal Ip, and a line-interval detection circuit 59) that detects the no-signal HUB portion between the lines, and a line-interval detection circuit that detects the no-signal portion between the lines. circuit 5
92 and the block 11 for detecting the no-signal portion between the Glock and the clock. +i elemental digital data is transferred from the take 0 recorder 31 (IJJ equal to liJ) is supplied to the clock input terminal (ckl').
It has a counter of 594. The first counter 594 is, for example, a 5-bit counter, and is used to calculate -I'' the number of pixels of the image N supplied to one circuit 56. The most significant output bits α3 to α5 from the output bits are passed correspondingly close to the first to third bits of the input section of the address switching circuit 60, and are connected between the lines via the OR circuit 59a. The line-to-line detection signal outputted from the detection circuit 59 resets the d and several f lines. The line-to-line detection signal is supplied to the clock input terminal (ckz) of the second counter 595. This second counter 595 is, for example, an 8-bit counter, and outputs the output bits β1 to β from the lowest to the highest.
8 is connected to the 7th to 14th bits of the input section of the address switching circuit 60. The output bits .beta.7 and .beta.8, which are the upper two bits of the second counter 595, are logically summed by an AND circuit 59b. This AND circuit 59b is adapted to reset both the first counter 594 and the second counter 595 via the OR circuit 59a and the OR circuit 59c correspondingly. The second counter is also configured to be counted by the line spacing detection signal outputted from the line spacing detection circuit 592 via the OR circuit v659c. Further, the output signal of the most significant output bit β8 of the second counter 595 is supplied to the clock input terminal (ck3) of the third counter 596. This third counter 596 is a 3-bit counter, and the output bits γ to γ3 from the lowest to the highest are outputted to the input terminal of the address switching circuit 6θ through inverters 59d to 59f, respectively. It is connected to the 4th to 6th bits. This third counter 596 calculates i? based on the inter-block detection signal output from the inter-block detection circuit 593. The dial is now reset by a number. The signals supplied to the first to fourteenth bits of one input section of the address switching circuit 60 are selectively applied to the memory 58 during the horizontal synchronization signal generation period of the horizontal synchronization signal generation circuit 68. The bits are supplied correspondingly to the least significant bits to the most significant bits of the address input section of the address input section. In this way, the skin address generating circuit 59 has l,
The memory 58 is configured such that the digital data obtained by the MiJ recording/demodulation circuit 56 and the S/P circuit 57 is read in the 8th line, then written in the 7th line, and then sequentially written from the 6th line to the 1st line. (See Figure 6). Next, the read address generation circuit 62 of FIG. 5 will be explained with reference to FIG.
Components that are the same as those in the figures are given the same reference numerals and their explanations will be omitted. The address generation circuit 62 is connected to the synchronization signal generation circuit 6.
The clock input terminal (ck4) of the fourth counter 62) has a period approximately equal to the display period of 7 to 1 pixel.
It is designed to be supplied and counted. The fourth counter 62 is, for example, an 8-bit counter, and the output bits a6 to a8, which are three tenth bits, are sent to the fourth output bit of the other input section of the address switching circuit 60 via the address correction circuit 63. The output pins a3 to a5, which are the lower three bits, are connected to the first to sixth bits of the other input section of the address switching circuit 60.
to the third bit. The output signal of the most significant output bit a8 of the fourth counter 62 is a JK-type 7-lip flop 622.
The clock input terminal ck is supplied to the clock input terminal ck of the clock. The clock input terminal (ck
s) and one input terminal of the AND circuit 624, and the input terminals J and K are commonly pulled up to a high level by the power supply +Vc voltage. The output signal of the seventh output a7 of the fourth counter 62 is supplied to the other input terminal of the notebook AND circuit 624, and when the output signal becomes high level, the fourth counter 62 and the above-mentioned fritsunoflow y 7' 622 via the inverter 625.
is designed to be reset. The fifth counter 623 is an 8-bit counter, and the first to eighth output bits b1 to b8 are the 7th to 14th bits of the input part of the other power of the address cutting circuit 6o. KJi5 will be continued. Note that the first input section of the other input section of the address switching circuit 6o
The Japanese symbols supplied to the fourteenth bits to 14th bits correspond to the lowest to most significant bits of the address input section of the memory 58 outside the horizontal synchronizing signal generation period of the horizontal synchronizing signal flash generation circuit 68 (l-supply As a result, the fourth counter 62)
This specifies the address of 256 pixels to be displayed in one horizontal period of the lower 6 bits of 8.
0, - then the output sle level to the clock input terminal ck of the above-mentioned frill rough 0 frog 622 is set to high level color low level, and the output 9m Q
k is set to high level. Then, when the seventh output bit b7 of the fourth counter 621 goes high, the AND circuit 624 resets the fourth counter 62 and the flip counter 622. As a result, the clock input D of the fifth counter 623: '$ (cl<5) Kf zu, television 1'! - 1 horizontal spacing of i (corresponding to 193201iij element) jυ
” ml is supplied with i and i of jl. The fifth counter 623 is 25.
The horizontal jυ of G is changed to 7.7, which means 2.
Please point 21 the address of Jiin at 192 on the left. ・This (from ・ζ, read address like this) 7. Rebirth 6 ” l'l A lJt: Self-synchronization signal generation time:::'fl Same as Chronograph No. 5 of 67, 1 is added to the memory 58 i/(: f note 1. The part consisting of the horizontal synchronizing signal generation circuit 68 will be explained in detail with reference to FIG. 13.However, in FIG. The same parts as in FIG. The horizontal IFIJ period signal generation circuit 68 is connected to one input terminal of an AND circuit 68 forming 17i.The output terminal of this AND circuit 681 is connected to the clock input terminal (c
ks). The sixth counter 682 is a 6-bit counter, and each of the output bits cl to c6 from the lowest to the highest is a reset input terminal P of a seventh counter 683, which will be described later.
1 to P6 and each input terminal of a 6-man NAND circuit 684 are connected in a single-core manner. The output terminal of the six-man powered NAND circuit 684 is connected to the other input terminal of the AND circuit (i/?l). The seventh counter 683 is a presettable 7-bit counter, and the maximum ''The second output bit d7 is connected to the clock input terminal C1 of a monostable multi-bi break 685 (to be described later). The circuit is connected to a predetermined terminal, and the input terminal A is connected to the source Vc together with one end of the resistor RO, and the output terminal Q is connected to a predetermined input terminal of the mixing circuit 66. multi vibrator 685
(r"1. When the clock signal rises due to the resistor Ro and the capacitor Co, a PALNU with a PALNU width approximately equal to that of the horizontal synchronizing signal of the television signal is output. 683 is a clock input terminal (ck
7) is connected to the output terminal of the clock generation circuit 69,
It is designed to perform a division operation of the clock signal. The clock generation circuit 69 is configured to output a clock signal having a frequency approximately twice that of the clock signal that the synchronization signal generation circuit 67 supplies to the read address generation circuit 62, for example. When the seventh counter 683, the upper two bits of the fourth counter 62 of the read address generation circuit 62, and the output bit a7.a@ of the read address generation circuit 62 both fall, the sixth counter A pair of input terminals are connected to the fourth counter 62 so as to reset the count value of 682.
The output ends of the AND circuits 686 respectively connected to the 1 output bits 84+a& are connected to the low P terminal LDK for preset control. Furthermore, the seventh counter 683 is connected to the clock input terminal of the fifth counter 623 so that it can operate when the output terminal Q of the 7-lip float 7° 622 of the read address generation circuit 62 is at a high level. (ck5)
The middle point of the connection between the output terminal Q of the FURITUNO FUROTUNO 622 is connected to the Tyranoid enable terminal CE. Incidentally, the 1-inclusive address generation circuit 59 has been omitted in the above description for the sake of clarity, but in addition, it includes a four-man powered AND circuit 7, AND circuits 72 and 73, which will be described later.
8th counter 74, JK type flip-flop 7.5
, 76, D-type 7-lip front f77.78'ff: That is, the four-man powered AND circuit 71 has the first and second
, the third input terminal is connected to the output bits γ3, γ2, and γ1 of the third counter 596, and the fourth input terminal is connected to the inverting output terminal Q of the JK type 7 lip-flop fys. ing. The output terminal of the four-person circuit 7 is the clock input terminal c of the 7-lip 70 tube 75.
connected to k. The input terminals J and K of the fritsuno flop 75 are both connected to the power supply +Vc, and the output terminal Q is commonly connected to the input terminals of the -powers of the AND circuits 72 and 73. The other input terminal of the AND circuit 72 is connected to the most significant output bit β8 of the second counter 595, and the output terminal is connected to the clock input terminal ckK of the JK-type fritsuno flop 76. The flip-flop 76 has an input terminal J connected to the input terminal K, an input terminal K grounded, an output terminal Q connected to the other input terminal of the AND circuit 73, and an inverted output terminal member. It is connected to the reset terminal R6 of the sixth counter 682. The output terminal of the AND circuit 73 is connected to the eighth counter 7.
4 clock input terminal ek, [connected. The eighth counter 74 has a 3-bit down (that is, subtraction)
It is a counter, and each output bit e1 from the lowest to the highest
The address correction circuits 63 to which e3 correspond, respectively.
is connected to each bit of the other input section of . Further, the reset terminal R8 of the eighth counter 74 is connected to the output terminal of the inter-block detection circuit 593 together with the reset terminal R of the flip-flop 75, so that they are both reset by the inter-block detection signal. On the other hand, the output terminal of the line spacing detection circuit 592 is connected to the clock input terminal ck of the above-mentioned flip-flop, F077. The input terminal of the flip-flop 077 is connected to the power supply +Vc, and the output terminal Q is connected to the input terminal of the flip-flop f78. The flip-flop 78 has a clock input terminal ck connected to an output terminal from which a vertical synchronizing signal is derived from the synchronizing signal generating circuit 67, and an inverted output terminal point of the JK-type flip-flop, l, 7'76, and D-type flip-flop 7. '7
AK is connected to each negative logic reset slope n of 7. Note that the address +i+positive circuit 63 (c), for example, is 441i performed by an adder circuit. Furthermore, the inter-block detection signal of the inter-block detection circuit 593 is used to clear all storage areas of the memory 58 (not shown). In other words, the decoder 34 having the above configuration is connected to the read address generation circuit 62.
This is raw I! Based on the clock signal supplied from the circuit 67, the memory 58 is transferred via the address switching circuit 60.
The appropriate rapanotal data 'j:' is read out approximately in response to the running speed of the MfJ criminal image iso 36 approximately λJ. Further, when the sixth counter 682 of the horizontal synchronizing signal optical main circuit 68 is in the reset state by the y1 or the f-flop 76, the output data, that is, all the output bits C1 to MC6 are at a low level. It has become. In this state, when the output bits a4 and as of the fourth counter 621 of the sixth sale address generation circuit 62 both fall, the AND circuit 686 outputs the signal to the seventh counter 683.
The output data of the sixth counter 682 is loaded (
In other words, it will be preset). Then, the read address generation circuit 62 is, for example, 256
Every time the designation of the address corresponding to 1iIi is completed, the output terminal Q of the flip-flop 622 is set to the no-y level, and the seventh counter 683 is activated. As a result, the 'l'th counter 683 starts the G1 degree number of the clock number I0 supplied from the clock generation circuit 69, and if it is 64% C old number in decimal notation, it is earth 1. [View] (The stable multivibrator 685 is connected to Tomito and υ2 to supply a signal to the mixing circuit 66, which becomes a horizontal periodic signal. In the dog state in which the counter 74 of No. 8 is reset, the output pin of the read address generation circuit 62 is
6 to C7 are often supplied to the address input section of the memory 58 via the -i-+ address extraction circuit 63 and address switching circuit 60. In this state, pixel signals based on digital data stored in the second to eighth rows of the memory 58 in FIG. 6 are presented to the effective screen of the receiver 36. On the other hand, as described above, the decoder 36 inputs the first digital gutter of the painter signal Glock to the memory corresponding to the 8th line shown in FIG. 58 Addresses IV
Sound ((f1>2), so that every time the next 1-j digital gutter is transferred, the rabbit, 7. 6th... , the storage area corresponding to the second line ((operates to write these digital garters.) The storage area of the digital garters for the memory 58 is as described above. Self-do H + - +) 1 Rokeru is made between the horizontal doryoku sword number output 51 of the regeneration 67. In this way, the 7th line 1' digital gata ( In other words, when the writing of (corresponding to the second line of FIG. The output bits γl to γ3 both fall from a high level to a low level, and the output terminal level of the four-man AND circuit 71 falls from a high level to a low level.Therefore, the flip-flop circuit 75 Above AND circuit 7
The input terminals ☆11 of each of 2 and 73 are set to a high level, and the fourth input terminal of the AND circuit 71 is set to a low level. Then, the digital data on the 8th line is the 2nd line of the 61st line.
When the output bit .beta.8 of the second counter 595 rises in a state in which data is written to the storage area of the memory 58 corresponding to the row, the output .psi.1j of the AND circuit 72 becomes the no level. As a result, the inverted output terminal 6 of the flip-flop 76 becomes low level, releasing the reset state of the sixth counter. As a result, the sixth counter 682 outputs the output of the NAND circuit 684 (IM is set to high level, so
Each time the 1,000V1 synchronizing signal of the synchronizing signal generating circuit 67, which is supplied to the clock input terminal ck6 via the AND circuit 681, falls, the argument value is incremented to zero. In addition, the seventh counter 683 increases the value reset in the sixth counter 682, so the timing of the horizontal synchronization signal output from the monostable multivibrator 685 gradually advances. 3. As a result, the screen of the receiving aircraft 36 gradually moves to the right. When the count value of the sixth counter 682 counts 63 in decimal notation, the other input terminal of the AND circuit 681 becomes low level and the sixth counter 682 counts the horizontal open JtJ'' signal by V'c. is prohibited. Also, in this state, the receiver 36
On the effective screen, the vertically written character strings in the 2nd to 8th lines, the front 5 self-memory 5sKHr21 which corresponds to the 1st to 7th lines in Figure 6, are displayed. The pixel number is displayed. This means that the clock signal G, which has a frequency approximately twice that of the clock signal supplied from the synchronization signal generation circuit 67 to the read address generation circuit 62, is sent from the clock generation circuit 69 to the seventh counter 68.
/ζ due to being supplied to 3. When the digital data has been stored in the storage area of the memory 58 corresponding to the 8th row (that is, the 1st row in FIG. 6), the row spacing detection coefficient of the row spacing detection circuit 592 causes the flip 70 to The output terminal Q of the knob 77 is set to high level. After that, when the vertical synchronization signal is outputted from the synchronization signal generating circuit 67, the inverted output terminal point of the free luff 0 float knob 78 is set to low level, and the above-mentioned flip flop 7
6 and 77 together. By being reset, the -hs self-flip 0 floff 076 causes the -hs self-eighth counter 74 to count down by 1, and also resets the sixth counter 682. As a result, the seventh counter 683 counts 64 clock signals supplied from the clock signal generation circuit 69 as before, and then drives the stable multi-pie break 683 to generate a horizontal synchronization signal. It is something. At the same time, the eighth counter 74il''i works together with the address ÷jJ positive circuit 63, and converts the digital data in the memory 58 from the second row to ~' in FIG. 6, for example.
This prevents the storage areas corresponding to the λ8 row and the first row from being read in a circular manner. In this way, vertical text strings are crawled. By the way, the vertical synchronization IPA signal frequency of the NTSC system is l
",'s 60 Hz, the second counter 59
5, β8 becomes high level, and the front receiver 36
The period required from when the screen starts to move until crawling is performed is approximately 1 second. Furthermore, when the image signal of the next row is supplied to the Shun3 circuit 56, the digital data (-i) is stored in the storage area of the memory 58 corresponding to the first row in FIG. , when the output bit βB of the second counter 595 becomes high level, the screen of the receiver 36 moves to the right as described in 11) from the third line to the ninth line. Yagura, 6: 'IIJJ character string will be displayed. Next, when the line spacing of the image signal is detected from the 11th row of the F city record line (bird output circuit, 5921/(), the sixth counter 682 is reset as in the case of the pigeon house described above, and the J-
5 self? The counter 74 of A8 is counted down and the crawling is performed again. Similarly,
Next line ll! Scrolling is performed while the II image signal is supplied to the IIJ recording and demodulating circuit 56. Such a scrolling operation is performed by the iJ'J receiver 3.
Since the character string on the screen of 6 is gradually moved in the horizontal force direction e, the image on the receiver 36 becomes extremely easy to see. For example, even if so-called karaoke lyrics are displayed on the receiver 36, the user will not lose sight of a single lyric and it will be very convenient. That is, this invention is applied to the above-described image recording and reproducing apparatus, and the main parts of one embodiment of this invention will be explained in detail below with reference to the drawings. is the color changing side @l (
iJ! (=j indicates the addition means. However, in Figure 14, 11j is added to Figure 3 and Figure 4 (i4 r8f).
;,: -24+ number 7 is attached and shown l~, 7 Ml'r,
'j Omit the month. In other words, in Figure 14, 3 Z a kl first Kane 0 recorder, r+iJh 5 stone statues r 金, 6 (bundling tongue also portrait, by 'C11!i statue・;C; issue and i-
The 11th issue of B'B is 1414 digits long (the master tape, ?l -1tx is 2 -1 tx). It is output from the tape recorder 31 r+ of B and is addressed to Otsumae. Audio i Ago (d, 'Zeng + i Kinuki, 1j, (supplied and played back to Nubica 37 via 35,
“It is supplied to the single-power recording input terminal of the second cheap record 31b, which will be described later. The image is displayed on the TV receiver 36 and is also supplied to the encoder 32 via the decoder 34. In this encoder 32, instead of the output image of the TV left camera 1 described above, The image signal from the decoder 34 is supplied to the ADC 42 and digitalized.This digitalized image signal is sent to the S/P circuit 4.
3, it is converted into parallel digital data, and a predetermined 1iiji prime number (in this case, one row of Vi) is converted into parallel digital data by the input circuit 44.
It is written to the memory 45 every time. The digital data written in this memory 45 is read out by the readout circuit 520 at around pj, and the color change 1h1] signal signal is added 'll''?5
80. This color change control signal addition circuit 80 outputs a count value to the address generation circuit 51 based on a color change control signal addition command given from the outside. tjll +1TI
The I bias signal is supplied, and the read address for the memory 45 is counted in increments of 2ii4II undivided for two lines of data. Then, when the readout circuit 520 supplies 2 lines of data from the memory 4, the data section VC color change control signal for the 2 pixels is black (for example, the corresponding data (2,4kHz) to 1
: It is output with a lot of information. The digital data to which the color change control signal has been added in this way is supplied to the P/S circuit 52, where it is converted into serial digital data pixel by pixel. This serial digital data is subjected to FSK modulation by the modulation circuit 53, and is supplied to the other recording input terminal of the second cheap recorder 31b via the output ☆1"Op.This second tape recorder 31b The output signal (image signal) from the encoder 41 and the audio signal from the first and second tape recorders 31a are recorded onto the arsenic tape 314b to create a board tape. The operation and usage of the configured color change: ti: control signal adding means will be explained below.
bf: Set to recording state. As a result, the image signal and audio signal recorded on the master tape 314a are played back by the receiver 36 and the speaker 37, respectively, and are also recorded on the magnetic tape 314hK by the second tape recorder 31b. . The recording format of the encoder 41 at this time is as shown in No. 81 and FIG. 9. In this state, the user can change the color at a desired location while monitoring the above images and the output of the image using the 6 and the speaker 37. Issue 1" Force 1" 4 order tfff Fj self color change change jij'1 work) 1 yo 5- issue I month force 11 When islanded in circuit 8θ, the color change jf+', l whispertit l1r-: issue The additional circuit 80 is 7 as described above: Uni Memory 45 to ii
A color change control number 111 is attached to the digital screen to be outputted. This color change y-shadow 1
・The signature format of 1j elevation signal addition 1iHj path 8o is as shown in FIG. 15(A). That is, the recording mat of the digital data supplied to the color change te 5.1 118 addition circuit 80 is after the nutat part (S) (first line M1 to 192nd line M192).
The first line of digital data consisting of data is recorded, and the second line of digital data, which is the same as the first line of digital data, is recorded with a silent part G of about 05 seconds,
From then on, the same goes for one line of digital data ji4J (
(It is recorded with a silent part G. Nshi, Q4 n Yukimi's third line data of the digital data M 3 K cut (7 and color change) When the i-control command 11 command is given,
As described above, the count control information is supplied to the fji'i output address generation circuit 5, and the count is increased by two pixels for In3 and the fourth line data M, ?, M4. (B) As shown in the enlarged K, two pixels of color change control (U4) are added after the 3rd and 4th line data.In this way, the 4th line data ((crossing) is added. The reason why color change control signals corresponding to four or more cumulative numbers are added is to take into account the 1. 'by
The dirt digital data will have a delay of four pixels, but this delay will match the count difference between the write counter 50 and the read address generation circuit 51. This count difference continues until one line of digital data is sent, but it is erased by the silent part G provided between the lines. As a result, the silent part G of 0.5 seconds is shortened by 4 pixels, but the time for one pixel is 200 μsec, which is 8 pixels in total.
Since the time is as short as 00 μsec, no problem occurs. Therefore, if the user issues a color change control command at a desired point in the image signal to be photographed, the image signal to which the color change control signal has been added is outputted to the second tape recorder 31bK, and the magnetic chip is outputted along with the audio signal. f314b. Next, the decoder 34.b has a color change control signal reading circuit for reading a color change control signal from the image signal recorded on the magnetic tape 314bK. This will be explained with reference to FIG. However, in FIG. 16, the same parts as in FIGS. 5 and 11 are designated by the same reference numerals, and the explanation thereof will be omitted. That is, the first counter 597 of the general-purpose atrea generation circuit 59 is the same as the first counter 597 shown in FIG.
94 is replaced by a 6-bit counter, and the third output bit to the fifth output bit α3 to α5
are connected correspondingly to the first to third bits of the single input part of the address switching circuit 60 as in the conventional case, and the most significant output bit α6 is connected to the clock input of the D&7 bit f70 knob 81. This D-type fritsunoflo f81i is connected to the line spacing detection No. 48 output from the line spacing detection circuit 592 or reset Ft'.
9.1/hi, the input terminal is connected to the starvation source +Vc, and the output terminal Q is connected to the clock input terminal ck of the type flip clock 082. ing. This Jk-type flip f70 flip 082 is configured such that the clock block detection signal output from the block block detection circuit 593 can be supplied to the reset terminal RK, and
Input 1) 1 Yumiko J and K are commonly connected to the power supply +Vc,
The output terminal Q is connected to the input terminal of the color synchronization signal generation circuit 70. The operation of the decoder 34 having a color change control signal reading circuit configured as shown in FIG. The image code supplied to the input terminal rp is demodulated by the demodulation circuit 56 and divided into digital data and clock signals by 1'4 (t. Of these, the digital data Vi=iJ as mentioned above is KS/
DA via P circuit 57, memory 58, and P/S circuit 64
Fully supplied to C circuit 65, m Ne endogenously generated at receiver 36 -1
The output signal is converted into a functional image signal and supplied to one input terminal of the mixing circuit 66. - Okay, the clock No. 18 is supplied to the first counter 597. This first counter 597 takes as an argument the 1iiiIi prime number of the lock number, that is, the above-mentioned image I'M,
If the color change control signal is not added to one line data of the image signal, if the 32-pixel bundle argument is used, the line output from the line-to-line detection circuit 591 will be reset by the bar 1 detection signal, and the top , and α6 are not output. When a color change control signal is added to one line data, the first counter 597 (d) outputs the output of the most significant output bit α6 to the D-type fritsuno 70.]
It is supplied to the clock input terminal clc of 81° and inverted at the output 114 f7/invert t of the output terminal Q of the flip 7° flof 08 of the D%. By which inversion, output rli:! The output input signal of the child Q becomes high level and the h1J color IWj period A is the 1st generation circuit 7θ.
7L is supplied to the input terminal of the preset color synchronization (No. 4 power/mixing circuit 66) from the nuclear synchronization circuit 70.Thereby, the above-mentioned mixing circuit 66
Then, the image signal and color synchronization signal are supplied to the receiver 76 through the IJi output terminal Ov, and the color of the screen, for example, the color of the characters or one of the backgrounds, can be changed. Note that the above-mentioned 7-ritsuno float 81 is reset by the line spacing/detection number 4.4 output from the line spacing detection circuit 592, but the JK type flip 70 f82 is reset by the block output from the block spacing detection circuit 593. Since it is not reset until the interval detection signal is input, the color is not changed even if a number of color change control signals are added to one line of digital data of the image borrowed material. In other words, if you change the row and add the color change control signal, the output signal of the output terminal Q of the above-mentioned knob 70 and knob 81 will become high level again. Since the output signal of the output terminal Q of 82 becomes low level and is supplied to the color synchronization signal generation circuit 70, the color of the reproduced screen returns to its original color again. This means that, for example, when used for karaoke, 1
For multiple lyrics, which are two consecutive image signals,
The beginning of the song can be displayed by changing the color at the beginning of each song. Therefore, by adding a color change control signal to a desired location when recording an image signal and an audio code, it becomes possible to easily display the song starting with a simple configuration during playback. As shown in FIG. 17, a plurality of JK-type 7-lip-flops and 8-lip-flops are installed after the above-described 7-lip-flop
2a, 82b, . By switching the output (・ζ), the color of the playback screen can be changed one after another. obvious and other 1
It goes without saying that various modifications and applications are possible without departing from the scope of the present invention. [Effects of the Invention] As detailed above, according to the present invention, among images displayed on an image display device from an image signal that is suitable for, for example, so-called karaoke and that is reproduced from a tape recorder and has a plurality of image information, It is possible to provide an extremely good image recording and reproducing device which has a simple structure and can easily display on both sides a state in which the timing of an image corresponding to specific image information and an audio number coincide with each other.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional still image recording and reproducing product. Fig. 2 is a diagram showing the format of the image signal of the device shown in Fig. 1. FIG. 4 is a block diagram showing the 11' circuit of the encoder of device 6 in FIG. 3; FIG.
The figure is a block diagram showing the decoder of the device of No. 31 No. 1, 8
Figure t86 is a diagram used to explain the relationship between the memory address in Figure 4 and the receiver screen in Figure 3.
B] Figure 7 is a diagram showing the television code for one horizontal period of the decoder in Figure 5, Figures 8 and 9 are explanatory diagrams of the format of the image signal of the apparatus shown in Figure 3, and Figure 10 is FSK
Figure 11 is a block diagram showing the main parts of the write counter in Figure 5, and Figure 12 is a block diagram showing the main parts of the write counter in Figure 5.
13 is a block diagram showing a portion including the horizontal synchronizing signal generation circuit of the decoder shown in FIG. 5, and No. 141gl shows an embodiment of the image reproducing device according to the present invention. Change the color! A block diagram showing the tii control color code addition means, FIG. 15 is the same implementation f! 10
Explanatory diagram of frost:inclusive format of color change control signal, No. 16
The figure is a block diagram showing nine parts of the encoder in the same embodiment, and FIG. 17 is a program diagram showing another embodiment related to this explanation. 3 No. 7'Record 1", 32...Encoder,
33... Signal source, 34... Deco Kudag 35... Layer width device,
36...Uke(&u;i, 37...Nubika, 41・T
V left camera 42・ADC, 43...S/P circuit, 44・
-Each side circuit, 45...Memory, 46...1 address generation circuit, 47...Address switching circuit, 48...Write clock detector, 49...Synchronization signal generation circuit, 5θ
...Write counter, 5...JCC child address generation circuit 520...Read circuit, 52...P/S circuit, 53
. . . Modulation circuit, 54 . . . Readout clock I1': stopper, 55 . 58...Memory, 59
... Cutting address generation circuit, 60... Address switching circuit, 61... Read/write control circuit, 62... Read address generation circuit, 64... I)75 circuit, 65...
DAC, 66... Mixing circuit, 67... Synchronization signal generation circuit, 68... Horizontal synchronization signal generation circuit, 69...
Clock generation circuit, 70... Color synchronization signal generation circuit, 5
9 line + 'if1 detection circuit, 592...Line spacing detection circuit 1 omitted, 593...Block spacing detection circuit, 594...
First counter, 595...Second counter, 59G...
...Third counter, 59a, 59c...OR circuit,
59b...AND circuit, 59d to 59f...Inverter, 62...Fourth counter, 622...Nori,
Zofurotsuno, 623...Fifth counter, 624...
AND circuit, 625...inverter, 681,686
...AND circuit, 682...Sixth counter, 683
...Seventh counter, 684...NAND circuit, 68
5... Monostable multi-by break, 8゛0... Color change 2, 1" both signals I1" addition circuit, 81.82... Flig 7I: IyNO. Applicant's agent Roshi I1 Suzue Yohiko Figure 1 Figure 3

Claims (1)

[Claims] a recording means for recording on an audio magnetic tape an audio signal and an image signal obtained by converting a plurality of image information to be displayed on a color image display device into digital data at a predetermined timing with respect to the audio signal; In an image recording and reproducing apparatus having a reproducing means for reproducing audio signals and image signals from an audio magnetic tape on which audio encoding and image signals have been recorded, a color change control signal is added to a predetermined portion of the image signal. a first means for recording the color change control signal on the audio magnetic tape by the first means; and a second means for reading the color change control signal during reproduction of the audio magnetic tape recorded by the first means.
An image recording and reproducing apparatus characterized in that the display color of the reproduced image of the color image display device is changed by the color change control signal read by the second means. Device.