JPS59181654A - Terminal plate for semiconductor module - Google Patents

Terminal plate for semiconductor module

Info

Publication number
JPS59181654A
JPS59181654A JP5601983A JP5601983A JPS59181654A JP S59181654 A JPS59181654 A JP S59181654A JP 5601983 A JP5601983 A JP 5601983A JP 5601983 A JP5601983 A JP 5601983A JP S59181654 A JPS59181654 A JP S59181654A
Authority
JP
Japan
Prior art keywords
terminal
plate
electrode terminal
plate thickness
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5601983A
Other languages
Japanese (ja)
Inventor
Masaru Ando
勝 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5601983A priority Critical patent/JPS59181654A/en
Publication of JPS59181654A publication Critical patent/JPS59181654A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain the titled plate of high quality and high dimensional accuracy without the generation of such an inconvenience as the stripping of a thin plate from the main body of said plate by a method wherein a main electrode terminal and a signal electrode terminal of different plate thickness respectively are formed into an integral body by means of a piece of metallic plate. CONSTITUTION:The terminal plate 21 is made of a piece of metallic plate coincident with the fixed plate thickness on the side of the main electrode terminal 22. In other words, the main body of said plate 21 is formed by punching from the metallic plate having the fixed plate thickness. The main body of this terminal plate 21 is punched in a prescribed shape equipped with the main electrode terminal 22 and the signal electrode terminal 23. The tip of said terminal 23 of said plate 21 is crushed to a thin plate by press-forming, thus being formed to a fixed plate thickness. This terminal plate 21 is treated with surface plating. The fixed plate thickness required to each of said terminal 22 and said terminal 23 can be obtained by only performing press working to the side of said terminal 23, since the plate thickness of the metallic plate serving as the material is coincident with the fixed plate thickness of said terminal 22.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、例えは、家庭用クーラのモーターの制御用
装置として使用される半導体モジュールの端子板に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a terminal board of a semiconductor module used, for example, as a control device for a motor of a household cooler.

〔発明の技術的背景〕[Technical background of the invention]

1つ 一般に、家庭用クーラ等のモーター制御ゞは、半導体モ
ジュールが使用される。第1図はこの半導体モジュール
を示すもので、このモジュールは複数の#=嗜体素子1
1a、llbを備えている。この半導体素子11a、I
lbは例えは周波数を変換するもので、この半導体素子
11a、llbの入出力電極を、複数の端子板12a〜
12eで等比する。この端子板12a〜12eは、lo
J図1(B)に示すように、電力を非出する主電極端子
13aおよび上記半導体素子11a、llbの制御信号
を棉比する信号電極端子13bからなるもので、このそ
れぞれの端+31) 子13ψ先端を固定板J4で固定し、上記半導体素子1
1a、llb′!i11′松脂ケース15内に設置して
構成している。
Generally speaking, semiconductor modules are used to control motors in household coolers and the like. FIG. 1 shows this semiconductor module, which includes a plurality of #=physiological elements 1
It is equipped with 1a and llb. This semiconductor element 11a, I
For example, lb converts the frequency, and the input/output electrodes of the semiconductor elements 11a and llb are connected to a plurality of terminal plates 12a to 12a.
12e to make an equal ratio. These terminal boards 12a to 12e are lo
As shown in FIG. 1(B), it consists of a main electrode terminal 13a that outputs no power and a signal electrode terminal 13b that outputs control signals for the semiconductor elements 11a and 11b, each of which has terminals +31). The tip of 13ψ is fixed with a fixing plate J4, and the semiconductor element 1
1a,llb′! i11' It is installed inside the rosin case 15.

第2図はこの半導体モノニール用の端子板12 a −
12eのうちの1つの端子板121f示すもので、この
端子板12は主電極端子13aおよび信号電極端子13
bを備えている。このそれぞれの電極媒子13a、13
bには、図示しない受は側端子との関係から、それぞれ
所定の板厚が要求されるもので、端子板12本体の板厚
を信号電極端子13b側の所定の板厚に合わせた場合、
第2区1(A)に示すように主電極端子13aには、金
属の薄板14aを巻きつけプレス加工して所定の板厚を
得るようにしている。
FIG. 2 shows a terminal plate 12a for this semiconductor monoyl.
12e, one terminal plate 121f is shown, and this terminal plate 12 has a main electrode terminal 13a and a signal electrode terminal 13.
It is equipped with b. These respective electrode media 13a, 13
In b, the receivers (not shown) are required to have a predetermined thickness from the relationship with the side terminals, and when the thickness of the terminal board 12 body is matched to the predetermined thickness of the signal electrode terminal 13b side,
As shown in the second section 1(A), a thin metal plate 14a is wrapped around the main electrode terminal 13a and pressed to obtain a predetermined thickness.

また、同図(B)に示すように、上記主電極端子13a
(二は、薄板14bを重合してプレス加工し、所定の板
厚を得るように構成することもある。このような端子板
12には、通猟、上記薄板14aまたは14bのプレス
加工後にめっき処理′lL:施すものである。
In addition, as shown in FIG. 3(B), the main electrode terminal 13a
(Secondly, the thin plate 14b may be polymerized and pressed to obtain a predetermined thickness. Such a terminal plate 12 may be formed by passing through the plate or plating after pressing the thin plate 14a or 14b. Processing 'lL: to be applied.

〔背景技術の問題点〕[Problems with background technology]

しかし、このように構成される端子板12では、主電極
端子1’ 3 aの所定の板厚を・得るために、薄板1
4aまたは14bをそれぞれ%さつけたり、重合したり
して構成しているので、この尚板14aまたは14bと
端子板12本体との間に間隙が生じたり、端子板12か
ら薄板が剥れたりする恐れがある。また、薄板プレス加
工後のめつき処理時において、端子板12と薄板との重
合部にめっき液が浸透し、端子板12自体の品質が低下
する恐れかある。
However, in the terminal board 12 configured in this way, in order to obtain a predetermined thickness of the main electrode terminal 1' 3a, the thin plate 1
4a or 14b are attached or polymerized, respectively, so that a gap may occur between the plate 14a or 14b and the main body of the terminal plate 12, or the thin plate may peel off from the terminal plate 12. There is a fear. Furthermore, during the plating process after the thin plate press working, the plating solution may penetrate into the overlapping portion of the terminal plate 12 and the thin plate, which may deteriorate the quality of the terminal plate 12 itself.

〔発明の目的〕[Purpose of the invention]

この発明は、上記のような問題点を解決するためになさ
れたもので、端子板本体から薄板が剥れてしまうような
不具合が生じることなく、高品質で寸法狛度の高い半導
体モジュール用端子板を提供すること2目的とする。
This invention was made in order to solve the above-mentioned problems, and provides a high quality and highly dimensionally consistent terminal for semiconductor modules without causing defects such as the thin plate peeling off from the terminal board body. The two purposes are to provide boards.

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係る半導体モジュール用端子板は、
それぞれ板厚の異なる主電極端子と信号電極端子と!、
一枚の金属板体で一体成形するものである。
That is, the terminal board for a semiconductor module according to the present invention is
Main electrode terminal and signal electrode terminal with different plate thickness! ,
It is integrally molded from a single metal plate.

〔発明の実施例〕[Embodiments of the invention]

以下図面によりこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第3図はこの半導体モソユール用端子板の外観ン示すも
ので、この端子板21は、主電極端子22側の所定の板
厚に合致した図示しない一枚の金属板体から形成する。
FIG. 3 shows the external appearance of this semiconductor module terminal board. This terminal board 21 is formed from a single metal plate (not shown) having a predetermined thickness on the main electrode terminal 22 side.

すなわち、まずはじめに、上記所定の板厚を有する金属
板体から、端子板21本体!打ち抜き形成する。この端
子板21本体は、上記主電極端子22部と信号電極端子
23部とを伽えた規定形状で拐ち抜かれるもので、この
端子板2ノの信号電極端子23の先端部をプレス成形に
て薄板状に潰し、所定の板厚に形成する。そして、端子
固定孔24a。
That is, first of all, from the metal plate having the above-mentioned predetermined thickness, the main body of the terminal plate 21! Form by punching. This terminal board 21 body is cut out in a prescribed shape that separates the main electrode terminal 22 part and the signal electrode terminal 23 part, and the tip part of the signal electrode terminal 23 of this terminal board 2 is press-molded. crush it into a thin plate shape and form it into a predetermined thickness. And a terminal fixing hole 24a.

24bや面取り部25a、25bビ外形の仕上げ抜き加
工により形成し、前記第1図における半導体素子11a
、llbの入出力電極部に対する接続部分26に直角に
折り曲げて、端子板21を形成する。この端子8+、2
1には、表面めっき処理を施すようにする。
24b and the chamfered portions 25a, 25b are formed by finishing punching of the outer shape of the semiconductor element 11a in FIG.
, llb are bent at right angles to the connecting portions 26 to the input/output electrode portions to form the terminal plate 21. This terminal 8+, 2
Step 1 is to perform surface plating treatment.

すなわち、この端子板21において、主電極端子22お
よび信号電極端子23のそれぞれに要求される所定の板
厚は、その材料となる金属板体の板厚が主電極端子22
のPJr定の板厚に合致しているので、(8号電極端子
23側シープレス加工を施すのみで得られるようになる
。つまり、このそセぞれ板厚の異なる端子22および2
3は、一枚の金属板体から一体的に形成されるの場合で
も、形状が変形するようなことなく、光分な強度が保た
れるようになる。したがって、受は側端子との接続状態
Z安定して保つことかで゛きる。
That is, in this terminal board 21, the predetermined thickness required for each of the main electrode terminal 22 and the signal electrode terminal 23 is such that the thickness of the metal plate that is the material thereof is the same as that of the main electrode terminal 22.
Since it matches the plate thickness of PJr, it can be obtained by simply applying sea press processing on the No. 8 electrode terminal 23 side.
3, even if it is integrally formed from a single metal plate, the shape will not deform and the light intensity will be maintained. Therefore, the connection state Z of the receiver with the side terminal can be maintained stably.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明(二よれは、それぞれ板厚の異な
る電極端子を一枚の金属板体で一体成形したので、端子
板本体の形状が変化してしまうような不具合が生じるこ
となく、品質および寸法鞘度を同上することかでき、受
は側の端子ン常(二確実に接続するのが可能となる。
As described above, this invention (two folds) is made by integrally molding electrode terminals with different thicknesses from a single metal plate, which eliminates defects such as changes in the shape of the terminal board body and improves quality. The dimensions and sheath degree can be made the same as above, and the receiver can be connected to the terminals on the side securely.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)および(B)はそれぞれ半導体モジュール
を上面および側面から見て示す断面構成図、第2図(A
)および(B)はそれぞれ上記半導体モジュールに使用
される従来の端子板を示す外観図、第3図はこの発明の
一実施例シニ係る半分体モジュール用端子板を説明する
外観図である。 21・・・端子板、22・・・主電極端子、23・・・
信号電極端子、24a、24b・・・端子固定孔、25
a、25b・・・面取り部、26・・・素子接続部分。
Figures 1 (A) and (B) are cross-sectional configuration diagrams showing the semiconductor module viewed from the top and side, respectively, and Figure 2 (A
) and (B) are external views showing conventional terminal boards used in the semiconductor module, respectively, and FIG. 3 is an external view illustrating a terminal board for a half module according to an embodiment of the present invention. 21... Terminal board, 22... Main electrode terminal, 23...
Signal electrode terminal, 24a, 24b...terminal fixing hole, 25
a, 25b... Chamfered portion, 26... Element connection portion.

Claims (1)

【特許請求の範囲】[Claims] それぞれ板厚の異なる少なくとも2つ以上の電極端子を
、一枚の金属板体から一体成形してなる半導体モジュー
ル用端子板。
A terminal board for a semiconductor module, which is formed by integrally molding at least two or more electrode terminals each having a different thickness from a single metal plate.
JP5601983A 1983-03-31 1983-03-31 Terminal plate for semiconductor module Pending JPS59181654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5601983A JPS59181654A (en) 1983-03-31 1983-03-31 Terminal plate for semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5601983A JPS59181654A (en) 1983-03-31 1983-03-31 Terminal plate for semiconductor module

Publications (1)

Publication Number Publication Date
JPS59181654A true JPS59181654A (en) 1984-10-16

Family

ID=13015348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5601983A Pending JPS59181654A (en) 1983-03-31 1983-03-31 Terminal plate for semiconductor module

Country Status (1)

Country Link
JP (1) JPS59181654A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0213745U (en) * 1988-07-08 1990-01-29
DE102011085313B4 (en) * 2010-11-11 2020-12-24 Mitsubishi Electric Corporation Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0213745U (en) * 1988-07-08 1990-01-29
DE102011085313B4 (en) * 2010-11-11 2020-12-24 Mitsubishi Electric Corporation Semiconductor device

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