JPS59180544U - receiving device - Google Patents
receiving deviceInfo
- Publication number
- JPS59180544U JPS59180544U JP7243983U JP7243983U JPS59180544U JP S59180544 U JPS59180544 U JP S59180544U JP 7243983 U JP7243983 U JP 7243983U JP 7243983 U JP7243983 U JP 7243983U JP S59180544 U JPS59180544 U JP S59180544U
- Authority
- JP
- Japan
- Prior art keywords
- band
- receiving device
- sample
- output
- control voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の受信装置の一例を示すブロック図、第2
図は本考案の一実施例における構成を示すブロック図で
ある。
4・・・FMアンテナ、5・・・AMアンテナ、6・・
・FMフロントエンド、7・・・AMフロントエンド、
8・・・FM復調器、9・・・AM検波器、10・・・
低周波段、1゛2・・・シンセサイザ、13・・・設定
器、14・・・切換回路1,15・・・時分割面路、1
6および17・・・サンプルホールド回路、16−、お
よび17−□・・・スイッチ回路、16−2および17
−2・・・コンデンサ。FIG. 1 is a block diagram showing an example of a conventional receiving device, and FIG.
The figure is a block diagram showing the configuration of an embodiment of the present invention. 4...FM antenna, 5...AM antenna, 6...
・FM front end, 7...AM front end,
8...FM demodulator, 9...AM detector, 10...
Low frequency stage, 1゛2... Synthesizer, 13... Setting device, 14... Switching circuit 1, 15... Time division plane path, 1
6 and 17...sample hold circuit, 16-, and 17-□...switch circuit, 16-2 and 17
-2... Capacitor.
Claims (1)
ドに対応して設けられたフロントエンドおよび復調回路
と、各バンドに対応して設けられかつシンセサイザから
時分割で各バンドに対応して出力される制御電圧をそれ
ぞれンサプルホールドし出力を同調側御電圧として対応
するフロントエンドに供給するサンプルホールド回路と
を備えてなることを特徴とする受信装置。In a synthesizer type multi-band receiving device, a front end and a demodulation circuit are provided corresponding to each band, and a control voltage is provided corresponding to each band and is output from the synthesizer in a time-division manner corresponding to each band. and a sample-and-hold circuit that sample-holds each of the signals and supplies the output as a tuning side control voltage to the corresponding front end.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7243983U JPS59180544U (en) | 1983-05-17 | 1983-05-17 | receiving device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7243983U JPS59180544U (en) | 1983-05-17 | 1983-05-17 | receiving device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59180544U true JPS59180544U (en) | 1984-12-03 |
Family
ID=30202578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7243983U Pending JPS59180544U (en) | 1983-05-17 | 1983-05-17 | receiving device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59180544U (en) |
-
1983
- 1983-05-17 JP JP7243983U patent/JPS59180544U/en active Pending
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