JPS59180528U - Clock oscillator - Google Patents

Clock oscillator

Info

Publication number
JPS59180528U
JPS59180528U JP7426683U JP7426683U JPS59180528U JP S59180528 U JPS59180528 U JP S59180528U JP 7426683 U JP7426683 U JP 7426683U JP 7426683 U JP7426683 U JP 7426683U JP S59180528 U JPS59180528 U JP S59180528U
Authority
JP
Japan
Prior art keywords
terminal
clock oscillator
capacitor
resistor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7426683U
Other languages
Japanese (ja)
Inventor
木内　光幸
今橋　久之
中村　「たける」
Original Assignee
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電器産業株式会社 filed Critical 松下電器産業株式会社
Priority to JP7426683U priority Critical patent/JPS59180528U/en
Publication of JPS59180528U publication Critical patent/JPS59180528U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例におけるクロック用発振装置の
電気的回路図、第２図はその発振電圧特性を示す図であ
る。 ２・・・セラミック発振子、３・・・第１の抵抗、４゜
５・・・コンデンサ、６・・・プルアップ抵抗（第２の
抵抗）。FIG. 1 is an electrical circuit diagram of a clock oscillation device according to an embodiment of the present invention, and FIG. 2 is a diagram showing its oscillation voltage characteristics. 2... Ceramic oscillator, 3... First resistor, 4° 5... Capacitor, 6... Pull-up resistor (second resistor).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] インバータの入力端子と接地端子間、出力端子と接地端
子間にそれぞれコンデンサを接続し、前記入・出力端子
間に、第１の抵抗とＬＣ共振回路を接続し、前記出力端
子と電源端子間に第２の抵抗を接続したクロック用発振
装置。A capacitor is connected between the input terminal and the ground terminal of the inverter, and a capacitor is connected between the output terminal and the ground terminal. A first resistor and an LC resonant circuit are connected between the input and output terminals, and a capacitor is connected between the output terminal and the power supply terminal. A clock oscillator connected to a second resistor.
JP7426683U 1983-05-18 1983-05-18 Clock oscillator Pending JPS59180528U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7426683U JPS59180528U (en) 1983-05-18 1983-05-18 Clock oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7426683U JPS59180528U (en) 1983-05-18 1983-05-18 Clock oscillator

Publications (1)

Publication Number Publication Date
JPS59180528U true JPS59180528U (en) 1984-12-03

Family

ID=30204361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7426683U Pending JPS59180528U (en) 1983-05-18 1983-05-18 Clock oscillator

Country Status (1)

Country Link
JP (1) JPS59180528U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5364453A (en) * 1976-11-22 1978-06-08 Nec Corp Complementary insulation gate field effect transistor oscillation circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5364453A (en) * 1976-11-22 1978-06-08 Nec Corp Complementary insulation gate field effect transistor oscillation circuit

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