JPS59179379U - Marker signal processing circuit - Google Patents
Marker signal processing circuitInfo
- Publication number
- JPS59179379U JPS59179379U JP7402783U JP7402783U JPS59179379U JP S59179379 U JPS59179379 U JP S59179379U JP 7402783 U JP7402783 U JP 7402783U JP 7402783 U JP7402783 U JP 7402783U JP S59179379 U JPS59179379 U JP S59179379U
- Authority
- JP
- Japan
- Prior art keywords
- marker signal
- processing circuit
- signal processing
- frequency divider
- constant level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Recording Measured Values (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は測定器と記録計の従来の接続関係を示す図、第
２図は従来のマーカ信号の波形を示す線図、第３図はこ
の考案の構成説明図、第４図はその動作説明図、第５図
はこの考案の実施例を示す電気回路図、第６図はその動
作説明図である。
１１は１７５分周器、１２は演算増幅器、１３は１７２
分周器である。Fig. 1 is a diagram showing the conventional connection relationship between a measuring instrument and a recorder, Fig. 2 is a diagram showing the waveform of a conventional marker signal, Fig. 3 is an explanatory diagram of the configuration of this invention, and Fig. 4 is its operation. FIG. 5 is an electric circuit diagram showing an embodiment of this invention, and FIG. 6 is an explanatory diagram of its operation. 11 is a 175 frequency divider, 12 is an operational amplifier, 13 is a 172
It is a frequency divider.
Claims (1)
を発生する分周器と、該分周器の出力と前記一定レベル
のマーカ信号との重み付は加算を行ない合成マーカ信号
を出力する加算器とを具備したことを特徴とするマーカ
信号処理回路。A frequency divider that generates a signal obtained by dividing a constant level marker signal by a predetermined frequency division ratio, and weighting the output of the frequency divider and the constant level marker signal by performing addition and outputting a composite marker signal. What is claimed is: 1. A marker signal processing circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7402783U JPS59179379U (en) | 1983-05-18 | 1983-05-18 | Marker signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7402783U JPS59179379U (en) | 1983-05-18 | 1983-05-18 | Marker signal processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59179379U true JPS59179379U (en) | 1984-11-30 |
Family
ID=30204132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7402783U Pending JPS59179379U (en) | 1983-05-18 | 1983-05-18 | Marker signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59179379U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS481474U (en) * | 1971-05-24 | 1973-01-10 | ||
| JPS5295273A (en) * | 1976-02-06 | 1977-08-10 | Anritsu Corp | Frequency marker display system |
-
1983
- 1983-05-18 JP JP7402783U patent/JPS59179379U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS481474U (en) * | 1971-05-24 | 1973-01-10 | ||
| JPS5295273A (en) * | 1976-02-06 | 1977-08-10 | Anritsu Corp | Frequency marker display system |
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