JPS59178736A - Bonded unit of semiconductor body and method of bonding same - Google Patents

Bonded unit of semiconductor body and method of bonding same

Info

Publication number
JPS59178736A
JPS59178736A JP4802684A JP4802684A JPS59178736A JP S59178736 A JPS59178736 A JP S59178736A JP 4802684 A JP4802684 A JP 4802684A JP 4802684 A JP4802684 A JP 4802684A JP S59178736 A JPS59178736 A JP S59178736A
Authority
JP
Japan
Prior art keywords
layer
gold
semiconductor body
metal
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4802684A
Other languages
Japanese (ja)
Inventor
ラルフ・バ−トン・デイ−ン
アドリアン・パ−リン・ジヤネセン
ジエニフア−・カレン・スト−ン
ア−サ−・ウオ−カ−
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to JP4802684A priority Critical patent/JPS59178736A/en
Publication of JPS59178736A publication Critical patent/JPS59178736A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は熱伝導性の基板への1′導体本体の接合(ホン
ディング)に関し、特にレーザのピー1−シンクへの取
付におりる応用に関するがこれに限られるものではない
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the bonding of 1' conductor bodies to thermally conductive substrates, and in particular, but not exclusively, applications in the attachment of lasers to P1-sinks. isn't it.

レーザのヒートシンクへの取付に従来使用されてきた方
法は金スズ共融ハンダの成型ペレットを用いるものであ
った。この接合方法にイ」随する問題点の1つは再凝固
したハンダが周囲に隆起した縁部を形成しがちなことで
ある。この縁部ができるのは、接合された成分からハン
ダ内へ金が拡散りるために生じるハンダの成分の変化に
にる融解点の局部的上Hのためと考えられている。この
縁部はレーリ゛が発する光の障害となるほど高くなりう
るので好ましくない。第2の問題点は再凝固したハンダ
には小泡の存在が認められるということにイ」随する。
The method traditionally used to attach lasers to heat sinks has been to use molded pellets of gold-tin eutectic solder. One of the problems with this joining method is that the resolidified solder tends to form raised edges around it. The formation of this edge is believed to be due to a localized increase in the melting point due to changes in the solder composition due to diffusion of gold from the bonded components into the solder. This edge is undesirable because it can be so high that it interferes with the light emitted by the Rayleigh. The second problem is related to the fact that small bubbles are observed in the resolidified solder.

これは含有気体によると思われるが、高電流密度部分に
ある場合にはレーザの寿命をそこなう局部的高温個所ど
なりつる。第3の問題点はタイがハンダに浮くため、特
に上述の縁部が障害となる問題点との関係でレーザのヒ
ートシンクを基準どした正確な最終的高さが制御しにく
いということに匈随づる。
This is thought to be due to the gas content, but if the laser is in a high current density area, it will cause localized high temperature spots that will shorten the life of the laser. A third problem is that the tie floats on the solder, making the exact final height relative to the laser heat sink difficult to control, especially in relation to the edge obstruction problem mentioned above. Zuru.

本発明の目的は特にハンダ成型品を使用しない接合方法
に関する。
The object of the invention particularly relates to a joining method that does not use solder moldings.

本発明によれば、半導体本体の表面は金の層で被覆され
た拡散障壁層により被覆され、基板の表面は金の層によ
り被覆され、上記金の層の一方又は両方は、半導体本体
が耐えうる棉1度を融点とづる金属−全共融物である合
金又は上記金属−全共融物を形成する金属からなり、酸
化Jる月利からなる場合は金の保護被覆により酸化から
護られている厚さ1ミクロン以下の拡散層にJ、り被覆
されており、上記金の層の金内へ層を世過づることなく
完全に拡散し接合領域を覆う連続的に溶融した金属−金
具融層が形成される温度にまで組立体が加熱される間2
つの被覆された表面は当接されてd3す、半導体本体の
表面と熱的電気的に伝導性の基板の表面との間に拡散に
よる金属接合を形成づる方法が提供される。
According to the invention, the surface of the semiconductor body is coated with a diffusion barrier layer coated with a layer of gold, the surface of the substrate is coated with a layer of gold, and one or both of said gold layers are coated with a layer of gold. An alloy with a melting point of 1 degree Celsius is a metal that is a total eutectic, or an alloy that is a metal that forms a total eutectic, and is protected from oxidation by a protective coating of gold if it consists of a metal that forms a total eutectic and is oxidized. A continuous molten metal fitting is coated with a diffusion layer less than 1 micron thick, which completely diffuses into the gold of the gold layer without passing through the layer, covering the bonding area. 2 while the assembly is heated to a temperature at which a melt layer is formed.
The two coated surfaces are brought into abutment d3, providing a method for forming a diffusion metallic bond between the surface of the semiconductor body and the surface of the thermally and electrically conductive substrate.

以下本発明の方法の好ましい例による崖導体し4アヂツ
ブの基板への結合について説明を行なう。
Bonding of the cliff conductor to the substrate according to a preferred embodiment of the method of the present invention will be described below.

GaAeAs又は(Ga In As P)レーザ等の
半導体チップ1は、レーザど電気接続をなし5またレー
)アの熱を放熱し金属被覆を有するタイ\7モンド、シ
リコン又はゲルマニウム等からなる基板2に接合する必
要がある。
A semiconductor chip 1 such as a GaAeAs or (GaInAsP) laser is connected to a substrate 2 made of silicon, germanium, etc., which has an electrical connection to the laser and a metal coating to dissipate the heat of the laser. It is necessary to join.

基板に接合されるシー1アチツプの表面は金の蒸着層3
により被覆されるが、その前に金がレーザ拐に拡散する
のを防ぐようにパラジウム又は白金等の適当な拡散障壁
層4が設(づられる。金層3は、ハング付のために従来
設(〕られでい1このより若干厚く、続く接合過程で金
層が貫通ずることなく拡散しうるよう充分深くなるよう
典型的には約2ミクロンとされいる。
The surface of the sheet 1 chip to be bonded to the substrate is coated with a gold vapor deposited layer 3.
Before this, a suitable diffusion barrier layer 4 such as palladium or platinum is applied to prevent the gold from diffusing into the laser beam. (1) Slightly thicker than this, typically about 2 microns, to be deep enough to allow the gold layer to diffuse through without shearing during the subsequent bonding process.

金層3を覆って1ミクロン以下の厚さのスズの蒸着層5
がある。典型的にはこれは約0.2ミクロンの厚さであ
るがスズは酸化しやづい金属であるためこの層の露出面
は金の保護層6により酸化から護られている。この保護
層は典型的には0.02ミクロンの厚ざである。
A vapor-deposited tin layer 5 having a thickness of 1 micron or less covers the gold layer 3.
There is. Typically this is about 0.2 microns thick, but since tin is a metal that easily oxidizes, the exposed surfaces of this layer are protected from oxidation by a protective layer 6 of gold. This protective layer is typically 0.02 microns thick.

基板2も層3と同様な厚さの金の蒸着層7て覆われてい
るか、これは層5の金層か接合過程で貴通す−ることな
く拡散しうるという同じ機能をはたり必要があるからで
ある。ダイヤモンド等の非金属牲阜板拐わ1には金層7
の接合を改善するため典型的には金属被覆を設【プる必
要がある。このためダイヤモンド基板は接合が改善され
るようチタン層により被覆され(図示せず)、ざらにこ
の層はチタンが金白に相き続き拡散しないよう白金の別
の層(図示せず)で被覆してしよい。明らかにハンダが
使用されていないので基板表面はそれほど平坦でなくて
もよく、その平坦度はダイヤモンドでは杭間により容易
に実現可能である。
The substrate 2 is also covered with a vapor-deposited gold layer 7 of similar thickness to layer 3, which has the same function of being able to diffuse through the gold layer of layer 5 during the bonding process. Because there is. A gold layer 7 is placed on a non-metallic sacrifice board 1 such as diamond.
It is typically necessary to provide a metallization to improve the bond between the two. To this end, the diamond substrate is coated with a layer of titanium (not shown) to improve bonding, and this layer is then coated with another layer of platinum (not shown) to prevent continued diffusion of titanium into the gold and platinum. You can do it. Obviously, since no solder is used, the substrate surface does not have to be very flat, which flatness is more easily achieved with diamond between the studs.

スズは、レーク“か内部拡散効果からの持続的損傷を受
(ブや1くなる400°C程度の湿度より相当に低い2
83℃で金と比較的低い温度のlI(融物を形成覆るか
ら拡散層5の月利として好ましいものの1っである。レ
ーク“チップは基板上適当な位置に誼かれ、例えば約0
.2Nの力を働くニードルチップで適当な位置に軽く係
止される。組立体は典型的には数分以上か(プて約30
0 ’Cまて加熱され、この温度に典型的にはたかだか
30秒賄持され、次いで典型的には5乃至10分間で室
温まで自然冷N1される。この加熱法によりスズ層5は
層3及び7の金の若干と反応して接合領域を覆う連続的
に溶融した共融層を形成する。この溶融層は層3及び7
内へ量適することなく基板2上の障壁層4まて完全に拡
散りる。
Tin suffers from persistent damage from rake or internal diffusion effects (200°C), which is considerably lower than the humidity of about 400°C, where tin suffers from permanent damage from rake or internal diffusion effects.
83° C. is one of the preferred materials for the diffusion layer 5 because it forms a melt at a relatively low temperature with gold at 83°C.
.. It is lightly locked in an appropriate position by a needle tip that applies a force of 2N. Assembly typically takes a few minutes or more (approximately 30
It is heated to 0'C, held at this temperature typically for no more than 30 seconds, and then allowed to naturally cool to room temperature, typically for 5 to 10 minutes. This heating method causes the tin layer 5 to react with some of the gold of layers 3 and 7 to form a continuous molten eutectic layer covering the bonding area. This molten layer consists of layers 3 and 7.
The barrier layer 4 on the substrate 2 is completely diffused without being absorbed.

本方法による作られた接合を幾つかの検査し・たところ
、欠陥の密度が大幅に減少し、接合は高い信頼性を示し
、前記のハンダ成型物法により作られた接合より形状が
正確に制御されることがねがった。また接合の厚Δが薄
く欠陥密度も低いので熱インピーダンスは小さい。
Several tests of joints made by this method showed that the density of defects was significantly reduced, the joints were highly reliable, and the shapes were more accurate than those made by the solder molding method described above. I wanted to be controlled. Furthermore, since the junction thickness Δ is small and the defect density is low, the thermal impedance is small.

拡散層5をレーク“チップの代わりに基板に取り角ける
こと、また薄い拡散層を画素子に取り付けることは容易
である。拡散層が共融物を形成するよう層3及び7から
金を引き81ず必要を減少又はな(づようにスズに若干
の金を混ぜることも容易である。
It is easy to incorporate the diffusion layer 5 into the substrate instead of the rake chip and to attach the thin diffusion layer to the pixel element. It is also easy to mix some gold with tin to reduce or eliminate the need for tin.

拡散層5にスズの代わりに用いられる金属の一例はゲル
マニウムである。ゲルマニウムは金とスズ金J” O1
i物J:り高温の共融物を形成覆るが、その温+ffは
GaAP、AS及び(Ga I n As P) (1
)チップの結合に用いられるのに高ずぎるものではなく
、この共融物の状態図はより単純なものであるから出来
あがった接合の品貿に有利になりつる。
An example of a metal used in the diffusion layer 5 instead of tin is germanium. Germanium is gold and tin gold J”O1
i product J: A high temperature eutectic is formed, but its temperature +ff is GaAP, AS and (Ga I n As P) (1
) is not too expensive to be used in chip bonding, and the simpler phase diagram of this eutectic may favor the trade of the finished bond.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は接合以前のデツプ及び基板組立体の慨I8断面
図、第2図は接合後のIn1様な断面図である。 1・・・半導体デツプ、2・・・基板、3・・・金の層
、4・・・拡散障壁層、5・・・([ム散層、O・・・
保護層、7・・・金の層。 特許出願人 スタンダード テレフォンスアンド ケー
ブルス パブリック 第1頁の続き 0発 明 者 アーサー・ウォーカー イギリス国デボン・トークウニ イ・クラウンヒル・ライズ36番 地
FIG. 1 is a cross-sectional view of the depth and substrate assembly before bonding at I8, and FIG. 2 is a cross-sectional view of In1 after bonding. DESCRIPTION OF SYMBOLS 1... Semiconductor depth, 2... Substrate, 3... Gold layer, 4... Diffusion barrier layer, 5... ([Mum diffusion layer, O...
Protective layer, 7... gold layer. Patent Applicant Standard Telephones and Cables Public Page 1 Continued 0 Inventor Arthur Walker 36 Crownhill Rise, Toukuniy, Devon, United Kingdom

Claims (1)

【特許請求の範囲】 (1)  半導イホ本体の表面は金の層で被覆された拡
散陣V、層により被覆され、基板の表面は金の層により
被覆され、該金の層の一方又は両方は、半導体本体が酎
えうる温度を融点とする金属−金共融物である合金又は
該金属−全共融物を形成でる金属からなり、酸化づる月
利からなる場合は金の保護被覆により酸化から護られて
いる厚さ1ミク目ン以下の拡散層により被覆されており
、該金の層の舎内へ層を白通りることなく完全に拡散し
接合領域を覆うjル続的に溶融した金属−全共融に4が
形成される温度にまで組立体が加熱される間2つの被覆
された表面は当接されており、半導体本体の表面と熱的
電気的に伝導性の基板の表面との間の拡散にJ二り接合
された半導体本体の接合体。 (2)  拡散層はススからなるか又はスズを成分とし
て含むことを特徴とする特許請求の範囲第1項記載の接
合体。 (■ 拡散層はゲルマニウムからなるか又はゲルマニウ
ムを成分として含むことを特徴とする特許請求の範囲第
1項記載の接合体。 (4)  拡散層は元素金属からなることを特徴とする
特許請求の範囲第1j頁、第2項、第3項のいずれか一
項記載の接合体。 (5)半導体本体はレーク゛であることを特徴とする特
許請求の範囲第1項、第2項、第3項、第4項のいずれ
か一項に記載の接合体。 (6)半導体本体(まGaAR−ASからなることを特
徴とする特8′F請求の荀囲第1項、第2項、第3項、
第11Jj’4 、第5珀のいずれか一項に記載の接合
体。 (7)半導体本体は(Gii I n AS P)から
なることを特徴とする特瀘晶求の範囲第1項、第2I貞
。 第3項、第4]負、第5項のいずれか一項に記載の接合
体。 (8)半導体本体の表面は金の層で被覆された拡散障壁
層により被覆され、基板の表面は金の層により被覆され
、頭金の層の一方又は両方は、半導体本体が耐えつる温
度を融点どする金属−全共融物である合金又は該金属−
全共融物を形成りる金属からなり、酸化りる月おlから
なる場合は金の保護被覆により酸化から護られている厚
さ1ミクロン以下の拡WI膚によりm覆されてJ5す、
頭金の層の金内へ層を貫通することなく完全に拡散し桜
台領viを覆う連続的に溶融した金属−金具融層が形成
される温度にまで組立体が加熱される間2つの被覆され
た表面は当接されてJ5す、半導体本体の表面と熱的電
気的に伝導性の基板の表w1との間の拡散ににる金属接
合にJ、り半導体本体を接合り゛る方法。 (9)  拡散層はスズからなるが又はスズを成分とし
て含むことを特徴とする特許請求の範囲第8項記載の接
合方法。 (10)  拡散層はゲルマニウムからなるが又はゲル
マニウムを成分として含むことを特徴とする特rF請求
の範m1第8項記載の接合方法。 (11〉  拡散層は元素金属からなることを特徴とす
る特許請求の範囲第8項、第91頁、第10項のいずれ
か一項記載の接合方法。 (12)  半導体本体はレーザであることを特徴とす
る特r1請求の範囲第8項、第9項、第10項。 第 11項のいずれが一項に記1伐の接合方法。 (13ン  半導体本体はGaAeAsからなることを
特徴とする特許請求の範囲第8項、第91負、第10項
、第11項、第12項のい寸゛れが一項に記載の接合方
法。 (14)  半導体本体は(Gal++ΔSP>がなる
ことを1!1徴どりる特許請求の範囲第83 r(H、
l’、 9 ]L第10項、第11項、第12項のいづ
°れが一項に記載の接合方法。
[Claims] (1) The surface of the semiconductor substrate is covered with a diffusion layer V, which is coated with a layer of gold, and the surface of the substrate is covered with a layer of gold, and one of the gold layers or Both are made of an alloy that is a metal-gold eutectic or a metal that forms a metal-gold eutectic with a melting point at a temperature at which the semiconductor body can melt, and in the case of an oxidized metal, a protective coating of gold. The gold layer is covered with a diffusion layer less than 1 micrometer thick, which is protected from oxidation by the gold layer, and it completely diffuses into the interior of the gold layer without passing through the layer, covering the bonding area continuously. The two coated surfaces are brought into contact while the assembly is heated to a temperature at which a total eutectic 4 is formed, forming a thermally and electrically conductive contact with the surface of the semiconductor body. A junction body of a semiconductor body that is J-junctioned to the surface of a substrate. (2) The joined body according to claim 1, wherein the diffusion layer is made of soot or contains tin as a component. (■ The bonded body according to claim 1, characterized in that the diffusion layer is made of germanium or contains germanium as a component. (4) The joined body according to claim 1, characterized in that the diffusion layer is made of germanium or contains germanium as a component. A bonded body according to any one of claims 2 and 3 on page 1j. (5) Claims 1, 2, and 3, characterized in that the semiconductor body is a rake. (6) The semiconductor body (made of GaAR-AS) of Claim 8'F. Section 3,
The zygote according to any one of No. 11 Jj'4 and No. 5. (7) The semiconductor body is characterized in that it consists of (Gii In ASP). The conjugate according to any one of Items 3, 4) and 5. (8) The surface of the semiconductor body is coated with a diffusion barrier layer coated with a layer of gold, the surface of the substrate is coated with a layer of gold, and one or both of the capillary layers has a melting point that exceeds the temperature that the semiconductor body can withstand. Metals to be mixed - Alloys that are all eutectic or the metals -
If it is made entirely of eutectic-forming metals and consists of oxidized metal, it is covered by an expanded layer of less than 1 micron thick, which is protected from oxidation by a protective coating of gold.
The two coatings are heated while the assembly is heated to a temperature at which a continuous molten metal-metal layer is formed that completely diffuses into the metal of the down payment layer without penetrating the layer and covers the Sakuradai region vi. The surface of the semiconductor body is brought into abutment by a method of bonding the semiconductor body by means of a diffusion metal bond between the surface of the semiconductor body and the surface of the thermally and electrically conductive substrate. (9) The bonding method according to claim 8, wherein the diffusion layer is made of tin or contains tin as a component. (10) The bonding method according to claim m1, wherein the diffusion layer is made of germanium or contains germanium as a component. (11) The bonding method according to claim 8, page 91, or claim 10, wherein the diffusion layer is made of an elemental metal. (12) The semiconductor body is a laser. Items 8, 9, and 10 of the Claims 1. The bonding method according to any one of Item 11. (13) The semiconductor body is made of GaAeAs. Claims 8, 91, negative, 10, 11, and 12 are the bonding method according to claim 1. (14) The semiconductor body has (Gal++ΔSP>) Claim 83 r(H,
l', 9 ]L The joining method according to item 1, each of item 10, item 11, and item 12.
JP4802684A 1984-03-13 1984-03-13 Bonded unit of semiconductor body and method of bonding same Pending JPS59178736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4802684A JPS59178736A (en) 1984-03-13 1984-03-13 Bonded unit of semiconductor body and method of bonding same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4802684A JPS59178736A (en) 1984-03-13 1984-03-13 Bonded unit of semiconductor body and method of bonding same

Publications (1)

Publication Number Publication Date
JPS59178736A true JPS59178736A (en) 1984-10-11

Family

ID=12791792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4802684A Pending JPS59178736A (en) 1984-03-13 1984-03-13 Bonded unit of semiconductor body and method of bonding same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6229147A (en) * 1985-07-30 1987-02-07 Kyocera Corp Electronic parts having conductive layer of gold

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532019A (en) * 1978-08-26 1980-03-06 Fujitsu Ltd Branching filter of light wavelength region variable type

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532019A (en) * 1978-08-26 1980-03-06 Fujitsu Ltd Branching filter of light wavelength region variable type

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6229147A (en) * 1985-07-30 1987-02-07 Kyocera Corp Electronic parts having conductive layer of gold

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