JPS59177777A - Memory pack - Google Patents

Abstract

PURPOSE:To provide versatile property to the titled memory pack without exerting influence upon the high speed processing of the computer side by incorporating an exclusive CPU controlling a semiconductor memory and a power supply backing up the CPU and the semiconductor memory in the memory pack. CONSTITUTION:A file name and a file format supplied from the computer are registered in a file control table FT in a RAM, a file end code FC is detected from the upper address to the lower address, the preceding (end mark +1) address is written in the table FT as a start address, and data are written from the start address. After receiving a data end signal from the computer side, a file end code FC is written in the end of the data and the end address is written in the table FT. At the data writing, the remaining number of data areas stored in a work area WA of the CPU is successively reduced, and when the number becomes zero on the way, a memory overflow comment is sent to the computer side and the current writing is cancelled.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory pack that includes a semiconductor memory and external connection terminals and is detachably attached to a computer.

<Prior Art> Conventionally, memory packs that can easily expand memory according to user needs have been proposed, such as R-product ■ modules or RAM packs.

However, conventional memory packs of this type are simply RA
Since the configuration is such that the M (read/write memory) is simply hacked up using a power supply, the storage contents of the RAM are under the control of the computer's CPU (medium-temperature processing unit). However, for example, when writing data or storing different formats of data, programs, etc., the computer's CPU performs this process, and during this time, the computer's original CPU processing is interrupted. The drawback was that it inevitably hindered high-speed processing.

In addition, the contents of the RAM are stored immediately below the computer's CPU, and for reasons of control, it can only be used in blue computers that have been completely matched in advance. Therefore, for example, the σl J4 can be used by directly connecting to the connector for connecting an audio cassette/external storage device.
It lacked j-ness.

<Fl> The present invention has been made in view of these conventional drawbacks, and aims to provide a memory pack that does not impede high-speed processing on the computer side and is compatible with β/L.

<Example> The present invention will be explained in detail below based on the drawings.

Figure 1 shows the internal circuit of the memory bank according to the present invention (°A
Configuration Diagram FIG. 2 is an internal configuration diagram of the RAM.

In the figure, RAM is a C-MOS type semiconductor memory (read/write memory). Internal 1 of this memory
As shown in Figure 2, for example, assuming that the internal area is from address oooo to address xxxx,
The area where the actual data is stored is set from address 0000 towards higher addresses, and at the end of the manually generated data, a file end code FC is entered to indicate the end of the data. It is now possible to specify the area.

A work area WA is still formed in a predetermined area from address xxxx toward the first address, which is used as temporary storage for the RAM control CPU, which will be described later, and roughly from the work area WA toward the lower addresses. A management table FT for the above-mentioned files is provided in a predetermined area, and the file name, file format, start address, and
The end address is written/placed.

The CPU is a central processing unit for controlling the semiconductor memory IJ RAM, and is connected to the RAM through an address bus AB, a data bus I)B, a chip select signal line C8, and a read/write signal line R/W. has been done.

N and B represent rechargeable batteries, and S and B represent solar cells. These batteries are used as backup for the CPU and RAM, and are connected to the power supply terminal Vcc and the ground terminal GND together with the CP LJ and RAM. The lines are connected in parallel as shown. R is current limited\limiting resistance, D
is a diode for backflow prevention IJ:.

When the power supply circuit constituted by the rechargeable batteries N and B and the solar cells S and H is connected to a computer, power is supplied from the computer side to the CPU and RAM via the power supply terminal VCC, and at the same time, the batteries N and B is charged. Then, when disconnected from the computer, N.

Voltage of B>(S, voltage of B Vs - forward voltage VD of D
) holds true, rechargeable batteries N, B, pcPU,
Supply power to RAM, and conversely VN〈(vs-VD
), the circuit is configured such that the solar cells S and B supply power to the CPU and RAM and simultaneously charge the batteries N and B.

All of the above-mentioned components except for the two terminals are housed in a resin case and formed into a pancage. Further, a data output terminal TD connected only to the CPTJ,
data input terminal RD, control 1-roll terminal CTL],
, 2, the aforementioned power supply terminal Vcc, and the ground terminal GND, a total of six terminals (are planted at predetermined intervals on the outer wall of the data center,
It can be connected to a computer connector.

When such a memory pack is connected to a computer to read and write files, the memory pack's CPU
The control operation is as follows.

First, when storing a file, the file name and file format given by the computer are registered in the RAM file management tape/l/FTK, the file end code FC is detected from the upper address to the lower address, and the file end code FC is detected before it (end mark). The above tape/L with the address of +1) as the first star number 1
'Fill in the FT and enter the data from the first place to the star:
It's getting crowded. When the data end signal is received from the computer side, the file entry code 1' is added to the end of the data.
Write FC and write this end address in Daigle FT. Furthermore, as data is written, the remaining number of data areas stored in the work area WA of the CPU is sequentially reduced, and when it becomes zero midway through, a memory overflow comment is sent to the computer side and the current write is canceled.

Next, when reading the file, enter the file name and file format given by the computer into the file management table FT.
Search further and read from the start address to the end address indicated on the chifur 1. If the file name cannot be found or the file format is different, send a comment to that effect to the computer and stop reading. do.

In this way, the memory pack's CPU can control RAM memory management and access with other devices, and the computer's CPU can control RAM memory management and access with other devices.
There is no need to place a burden on the PU.

FIG. 3 explains the operation when the memory bank of the present invention is connected to a computer to which an external storage device (cassette recorder) can be connected via a connector.

First, the computer CAL is a serial/
It is equipped with a vT10 board and is connected to each terminal of connector CN as shown. Normally, a cassette interface CA is connected to this connector CH to use a cassette recorder as an external storage device, but if the memory pack MP of the present invention is connected to this connector CH, the following will occur. It operates.

Now, when a computer reads a certain file from the outside (memory pack in this case), it first reads the control line CT.
Check the status of L1 to determine whether it can be used or not. and,
When possible, it outputs a signal to the control line CTL2 and waits for the device NO4 to be output from the memory puncture MP.

On the other hand, in the memory puncture MP, power is supplied from the computer, and when it initializes itself, the control) roll line C'FL
1 and outputs a signal to control 1-roll line CI' L
Wait for the signal to be output to 2. When a signal is output to CT L2, it outputs its own device NO1 to data output terminal TD.

When the above operations are completed, the computer CAL determines the currently connected device, executes a control operation suitable for that device, and reads the file data through the data output terminal TD. At this time, the control line CTL1 is used as a data latch signal line, and CTL2 is used as a BUSY signal line ()\endshaft signal transmission).

If you still want to write a file to the memory puncture MpKm, the reading operation is the same as described above until it is determined which device is connected, and then the file is written through the data input terminal RI), and this ψi connection is connected to the control line CT.
L1 is used as a BUSY signal line, and CTL2 is used as a data latch line.

In this way, the memory pack of the present invention can be directly connected to a computer to which the cassette recorder is connected as an external storage device to read and write files.

<Effects> As explained in detail above, the memory pack of the present invention has R
It is equipped with a CPtJ dedicated to AM control, and both are powered up by a built-in power supply, so it does not interfere with the high-speed processing of the connected computer, and it is possible to provide a highly versatile memory pack.

[Brief explanation of the drawing]

Fig. 1 is an internal circuit diagram of the memory puncture according to the present invention, Fig. 2 is an internal diagram of the RAM, and Fig. 31m is a diagram for explaining the operation when the computer and memory back are connected. be. RAM is read/write memory, CPU is central processing unit, N, B are rechargeable batteries, S, B are solar cells, AB is address 7, DB is data north, C8 is chip select signal line, R/ W is read/write signal line

Claims (1)

[Claims] 1. A memory pack that includes a semiconductor memory and an external connection terminal and is detachably attached to a computer, the memory pack comprising a dedicated CPU (Central Processing Unit) for controlling the semiconductor memory, and the CI) A memory pack characterized by having a built-in power supply for backing up TJ and semiconductor memory. 2. When the backup amplifier power source is composed of a rechargeable battery and a solar cell, and one of the batteries contributes as a backup depending on the voltage relationship between the two batteries, and the solar battery contributes as a blow-up. 2. The memory pack according to claim 1, wherein the memory pack is configured so that the rechargeable battery can be recharged using the battery power source at the same time.