JPS58109893U

JPS58109893U - Digital cassette tape memory compatible CMOS memory cassette

Info

Publication number: JPS58109893U
Application number: JP329582U
Authority: JP
Inventors: 内藤　昭; 今村　宗立
Original assignee: 三菱電機株式会社
Priority date: 1982-01-14
Filing date: 1982-01-14
Publication date: 1983-07-26

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のディジタルカセットテープメモリ装置の
外観斜視図、第２図は従来のディジタルカセットテープ
メモリ装置の概略ブロック図、第３図はこの考案のディ
ジタルカセットテープメモリ互換型ＣＭＯＳメモリカセ
ットの一実施例の構成を示す外観斜視図、第４図はこの
考案のディジタルカセットテープメモリ互換型ＣＭＯＳ
メモリカセットの一実施例の構成を示すブロック図であ
る。７・・・・・・ホストシステム、８・・・・・−ＣＭＯ
Ｓメモリカセット、９・・・・・・ケース、１０・・・
・・・インタフェースコントロール部、Ｉ’ｌ・・・・
・・ＣＭＯＳメモリ素子、１２・・・・・・駆動回路、
１３・・・・・・ＣＭＯＳメモリバックアップ用バッチ
１几なお、図中同一符号は同一または相当部分を示す。 −第３図１７′Fig. 1 is an external perspective view of a conventional digital cassette tape memory device, Fig. 2 is a schematic block diagram of a conventional digital cassette tape memory device, and Fig. 3 is an example of a CMOS memory cassette compatible with the digital cassette tape memory of this invention. FIG. 4 is an external perspective view showing the configuration of the embodiment, and is a CMOS compatible with digital cassette tape memory of this invention.
FIG. 2 is a block diagram showing the configuration of an embodiment of a memory cassette. 7...Host system, 8...-CMO
S memory cassette, 9...case, 10...
...Interface control section, I'l...
...CMOS memory element, 12...driver circuit,
13...1 batch for CMOS memory backup Note that the same reference numerals in the drawings indicate the same or corresponding parts. -Figure 3 17'

Claims

[Scope of utility model registration request]

A case that is mechanically compatible with digital cassette tape memory, multiple CMOS memory elements that can be inserted and removed from this case, and a CM that backs up the battery when power is off.
OS memory backup battery and above CMOS
a CMOS memory cassette having a drive circuit for driving a memory element; an interface control unit housed in the case and transmitting and receiving signals between a host system and the CMOS memory power set when the CMOS memory cassette is inserted into the case; A CMOS memory cassette compatible with digital cassette tape memory.