JPS5917769A - Thermal recording system - Google Patents

Abstract

PURPOSE:To prevent the generation of irregularity of recording, by monitoring the decoding of one-line components of encoded recording information, and recording a recording signal of the same line by plural times when the time of this decoding exceeds a prescribed time. CONSTITUTION:Encoded picture information transmitted from the facsimile transmitting side is inputted to a decoding circuit 7 through a buffer 6 and is decoded. The circuit 7 detects a synchronizing code EOL inserted to picture information. The picture signal decoded by the circuit 7 is stored in line memories 8 and 9 alternately through a changeover switch 10. When it is stored in one of memories 8 and 9, the picture signal is outputted from the other to a head control circuit 12 through a changeover switch 11. When an EOL detection signal (b) from the circuit 7 and a recording end signal (d) from the circuit 12 are H-level together, a sequence control circuit 13 generates a switching signal (g) to switches 10 and 11 and generates a pulse l to a motor driving circuit 15. If the signal (b) exceeds a prescribed time counted by a timer 14, a recording signal (e) of the same line is transmitted repeatedly, thus preventing the irregularity of recording.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal recording method used in facsimiles, etc., and in particular, when decoding and recording encoded recording information, pressure is applied to prevent uneven recording density due to the length of decoding time. The purpose is to

In Gl type facsimile receivers, a thermal head is used as a recording means, and recording is performed by applying a recording signal (picture signal) obtained by decoding encoded information from the transmitting side to this head. That's what I do.

However, as is well known, the Gll machine described above performs so-called variable sub-scanning depending on the length of decoding time for one line, so the recording time interval between each line is not constant.

Therefore, even if the current application time and applied voltage per line of the thermal head are the same, the recording density of each line will change. This is because when the recording time interval is short, each heating element of the thermal head is not completely cooled down when recording the next line, but when the time interval is long, each heating element is sufficiently cooled down.

Therefore, the present invention proposes a heat-sensitive recording method that eliminates the above-mentioned drawbacks, and the details thereof will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing the general structure of a general thermal recording apparatus in a simplified manner. In the figure, (1) is a thermal head, and for convenience of explanation, one line is 16
It is made up of dots, with one end connected to a separation diode (four heating elements C commonly connected via a DJ).
Four blocks (B1) to (B
4). (2) is a common terminal driver circuit that selectively drives one of the common terminals (Ml) to (M4) of the head (1) to the power supply (+) by a selection signal to be described later.
VC! Q) Perform K connection operation. (3) is a recording terminal driver circuit, which drives the recording signal terminals (N1 to N1) of the OIJ recording head (1) according to each 4-bit image signal to be described later.
(N4) is grounded. (4) is a recording signal latch circuit that latches each of the above-mentioned 4-bit image signals supplied to the driver circuit (3) K, and each one line of image signal (e) is stored in the shift register (4) in this latch circuit.
5), each 4 bits are converted into parallel and latched. Therefore, in this recording apparatus, the selection signals (fl) to (f
By sequentially applying 4), the recording operation is performed block by block starting from the leftmost block (B1).

Next, FIG. 2 is a block diagram showing a schematic configuration of an image information processing and recording control section embodying the present invention.

In the figure, (6) is a buffer memo that temporarily stores the encoded image information transmitted from the facsimile IJ sending side.
, (7) is a decoding circuit that sequentially decodes the image information transferred from this memory, and this circuit also detects the line synchronization code (F!OL) inserted in the image information. It has become. +81 +91 is a line memory that alternately stores both signals for one line each obtained by decoding in the decoding circuit (7) through the first (77 conversion switch 0rjI); At the same time, the image signal from the other side is successively outputted via the F82 changeover switch (11).(13 sends the read image signal to the shift register (5) in FIG. A selection signal (fl
) to (f4) and a head control circuit that generates a latch pulse (k) to be applied to the latch circuit (4).

In addition, (131 is the decoding circuit (7), the head control circuit (1), the sequence control circuit that controls the first and second changeover switches (1 (1), etc., (131 is a constant clock pulse (h) A timer circuit that sets a predetermined time (described later) by counting (151 is a pulse motor f16 for conveying the recording paper by receiving the pulse (1) from the control circuit +131)
This is a motor drive circuit that moves the motor forward. Here, the sequence control circuit (131) is the K from the decoding circuit (7).
When the OL detection signal (b) and the recording end signal (d) from the head control circuit 0 are both 'H' (high level), the switching signal (ω and motor A pulse (1) is generated to the drive circuit (5). Immediately after the generation of this signal (g), a decoding start signal (a) is given to the decoding circuit (7).

Further, when the recording end signal (d) is 1H', when the decoding start signal (al) or the output (1) of the timer circuit (141) is obtained, the control circuit (131) sends the recording start signal to the head control circuit f12. (C), and this signal (CIK) resets the recording end signal (d,).The decoding start signal (a) is the previous FOL detection signal (b) and the timer. Reset output (1).

One embodiment of the present invention is generally constructed as described above, and its operation will be described below with reference to FIG. 3 showing the timing of each signal of FqiJ.

Now, at time t1 in FIG. 3, the EOI of the line consisting of the decoding circuit (7) is detected, and the EOL from this circuit is detected.
When the detection signal (b) becomes 'H', the recording end signals (d, l) from the sequence control circuit (131 is the head control circuit t+2) are checked.Suppose that at this point the previous recording has finished. Since the recording start signal ([1) is at 'H' as shown in the figure, a switching signal (g) is generated, and this signal (g) switches the first and second changeover switch 10. ) (11) is switched, for example, to a state opposite to that shown. Also, a motor pulse (l) is output almost simultaneously with the switching signal (g), and the recording paper is thereby transported by one line in the sub-scanning direction.Decoding starts immediately after the switching signal (g). The signal (a) is output, and therefore, from this point on, the decoding circuit (7) performs decoding of the encoded information for the next one line at the EOL.
The image signals obtained by decoding are sequentially stored in the line memory (9). At the same time, the decoding start signal (a,)
The timer circuit f1a is reset once, and then this timer circuit (1Φ) counts the clock (h) (not shown in Fig. 6), and its output (1) indicates that the count result becomes a predetermined value. until 'L' (low level)
It becomes. Note that the blank BOL detection signal (1)) is also reset by the decoding start signal (a), so this detection signal becomes as shown in the figure.

On the other hand, since the recording start signal (C) is given to the head control circuit +12 immediately after the RiJ recording/decoding start signal (a), this control circuit receives the image signal of the previous line already stored in the line memory (8). Transfer lock (p) (not shown)
Therefore, the shift register (5) in Fig. 1 is changed by 4 bits.
Store it in and go. Therefore, the image signal is recorded on the recording paper as explained in FIG.

At this time, selection signals (fl) to (f4) from the head control circuit tlZ are sequentially applied to the common terminal driver circuit (2) in FIG. 1. Further, the latch pulse applied to the latch circuit (4) in FIG. 1 is as indicated by k in FIG. 3.

Next, since the decoding that started after the previous time t1 was completed in a relatively short time, the EOL detection signal (b) of the next line is generated from the decoding circuit (7) at the time t2, and at this time, the timer Assume that the output (1) of the circuit (14+) continues to be %L I.Then, at this time, the aforementioned recording operation has already been completed and the recording end signal (d) has returned to %Hp. Similarly to the above, each symbol signal in nIJ) (
a) (C) (1) is generated. Therefore, this time, the decoded image signal for one line passes through the first changeover switch a, which is switched to the state shown in the figure, to the line memory (8).
is stored in At this time, the recording paper is being transferred to the next line position by the motor pulse (1), so the second changeover switch (11) is switched from the line memo (January 9) to the next line position.
The image signal outputted one after another via t? It is recorded in the same manner as the iJ statement. In addition, the selection signal (fl) generated at that time
~(f4), transfer lock (p), latch pulse (k)
is exactly the same as the previous case.

Next, since the decoding that started after time t2 took a long time, the output (1) of timer circuit LJ4J went 'H' at time t3 until the next line's KOL detection signal (1)) was generated. '[Suppose it becomes. Then, at this time as well, the previous recording operation has already been completed and the recording end signal (d) becomes ``H''.
Since the sequence control circuit (131) generates a recording start signal (c) immediately after the time t5 and gives this signal fc to the head control circuit (1), the control circuit 0z The recording operation is started again.At this time, since the BOL detection signal from the decoding circuit (7) is 1L', the sequence control circuit (13)
does not generate switching signal (g) and motor pulse (1).

For this reason, the first and second changeover switches +1fl till
is in the state of eye 11 (the state shown in the figure), and the recording paper is not being transported. Therefore, at this time, line memo January 9)
Both signals will be recorded again at the same position on the recording paper. After the recording operation is completed, when the next line's KOL detection signal (b) (time point 11; s) is generated from the decoding circuit (7), the next line is decoded in the same manner as described above. Now we move on to the recording operation.

Note that the above operation model for recording the same line twice is for the case where the EOL of the next line is detected after the second recording ends (at time t4), but for example, if the EOL of the next line is detected during the second recording operation, If the EOL of the line is detected [3rd]
Refer to time t6 in the figure], there is no problem as long as the decoding speed of the decoding circuit (7) is sufficiently faster than the storage speed of encoded information in the buffer memory (6).

In addition, a timer circuit that determines whether to record once or twice (the set time is selected to be an appropriate length considering the relationship between recording density and coding time for one line, that is, the recording time interval). Furthermore, during the second recording, the voltage applied to the head (1) by the common terminal driver circuit (2) or the energization time may be different from the first time.

Furthermore, so far we have explained that the recording operation by the thermal head is performed sequentially one block at a time, but it is possible to divide the heat generating elements of the head into several groups each consisting of a plurality of blocks.
The present invention can also be applied to a case where a plurality of blocks, one selected from each group, are simultaneously operated and recorded.

As described above, according to the present invention, in a method of decoding encoded recorded information and performing thermal recording, if the decoding time for one line of recorded information exceeds a predetermined time, the decoding is performed. Since the obtained recording signals of the same line are recorded multiple times at the same position, it is possible to reduce the uneven recording density caused by the length of the decoding time of each line, making it suitable for facsimile machines, etc. .

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing a schematic configuration of a thermal recording apparatus, FIG. 2 is a block diagram showing a schematic configuration of an image signal processing/control unit implementing the present invention, and FIG. 3 is a diagram showing the configuration of each part thereof! It is a diagram showing the timing of Tυ production. (6): Buffer memory, (7): Decoding circuit, +81
(91 line memory, (1 depletion: head control circuit, +1
31 Nijikens flr+J control circuit! 141: Timer circuit, (15+: Pulse motor drive circuit. 4 [Fig.

Claims (1)

[Claims] (In the method of decoding recorded information transmitted in 1,1 code and recording it with a thermal head, the decoding time for each line of the recorded information is monitored, and the decoding time is set for a predetermined time. 1. A thermal recording method characterized in that, when the recording signal exceeds 100 kHz, recording signals of the same line obtained by decoding are recorded multiple times in a superimposed manner.