JPS5917276A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5917276A
JPS5917276A JP12724882A JP12724882A JPS5917276A JP S5917276 A JPS5917276 A JP S5917276A JP 12724882 A JP12724882 A JP 12724882A JP 12724882 A JP12724882 A JP 12724882A JP S5917276 A JPS5917276 A JP S5917276A
Authority
JP
Japan
Prior art keywords
noise
voltage
semiconductor device
semiconductor
pellets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12724882A
Other languages
Japanese (ja)
Inventor
Shigeru Kamiya
茂 神谷
Nagao Otake
大竹 永雄
Kenzo Shima
島 健蔵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP12724882A priority Critical patent/JPS5917276A/en
Publication of JPS5917276A publication Critical patent/JPS5917276A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074Stacked arrangements of non-apertured devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To offer the semiconductor device excluded with conduction noise, avalanche noise and moreover, easy to manufacture by a method wherein the device is constructed of semiconductor pellets of the plural sheets having P-N junctions and to perform high-frequency action and laminated between a pair of electrodes arranging the rectifying directions thereof, and a high resistor consisting of a semiconductor interposed between the electrodes adjoining to the cathode side thereof. CONSTITUTION:Depletion layers are formed though a little in P-N junctions of the respective silicon pellets 4a-4n to make junction capacitances to exist, and when a voltage is applied, and junction capacitances are charged to reach conduction, a time constant expressed by the product of junction capacitance and resistance is enlarged because of interposition of the high resistor 6, and forward recovery time is elongated. Accordingly, the current rise rate di/dt at forward recovery time is reduced, a counter electromotive voltage is reduced, and conduction noise is not generated. Moreover, when a reversely directional voltage is applied, the avalanches are generated locally in the silicon pellets 4a-4n on the anode side because of ununiformity of the alloted voltage rate, and even when pulse noise is generated, because the peak value thereof is limited by the high resistor 6, it is not transmitted to a Braun tube as avalanche noise.

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に、pn接合を何する+
1数枚の半導体ベレットをその整流方向を揃えて鑞材で
積層接着し、周囲を絶縁物でモールドした高圧半導体装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular, what is done with a pn junction?
The present invention relates to a high-voltage semiconductor device in which several semiconductor pellets are laminated and bonded together with a solder material with their rectifying directions aligned, and the periphery is molded with an insulating material.

この種高圧半導体装置は、テレビジョン受1象機の水平
偏向回路でフライバックトランスの高圧出力を整流して
ブラウン管に供給する整流器として用いられることが多
い。高周波動作を行なう必要があることから、各半導体
ベレットには金や白金などのライフタイムキラーが添加
され、順回復時間、逆回復時間が、それぞれ、500n
8ec、100ns(イ)以下に短縮されているものも
ある、順回復時間が短縮されているために、順回復時の
電流立上率di/dtと回路の浮遊インダクタンスLに
より、dl  。
This type of high-voltage semiconductor device is often used as a rectifier in the horizontal deflection circuit of a television receiver to rectify the high-voltage output of a flyback transformer and supply it to a cathode ray tube. Since it is necessary to perform high frequency operation, each semiconductor pellet is doped with a lifetime killer such as gold or platinum, and the forward recovery time and reverse recovery time are respectively 500n.
In some cases, the forward recovery time has been shortened to 8ec, 100ns (a) or less, and due to the current rise rate di/dt during forward recovery and the stray inductance L of the circuit, dl.

逆起電圧e(=−LX−a−T)かノイズとして現われ
、チューナー回路に伝播して、ブラウン管画面に悪影・
−を及ぼす(以下、このノイズを導通ノイズと称す)。
The back electromotive force e (=-LX-a-T) appears as noise, propagates to the tuner circuit, and causes bad shadows on the CRT screen.
(hereinafter, this noise will be referred to as conduction noise).

また、逆電圧が面圧半導体装置に印力1された時、浮遊
B−11kにより、各半導体ベレットに均等に電圧が分
担されない。この不均一性を電圧分担率で表せば、アノ
ード側で電圧分担率が高く、カソード側で電圧分担率が
低くなっている。
Further, when a reverse voltage of 1 is applied to the surface pressure semiconductor device, the voltage is not evenly distributed to each semiconductor pellet due to the floating B-11k. If this non-uniformity is expressed in terms of voltage sharing ratio, the voltage sharing ratio is high on the anode side and low on the cathode side.

アノード側の半導体ベレットに、その逆耐圧以上の電圧
が分担されると、その半導体ベレットはア・・ランシエ
領域に達して局部的にアバランシェを生ずる。この時流
れる電流は、浮遊谷駄から、アバランシェを起し7た半
導体ベレットを通ってフライバックトランスの方向へ流
れるものであるが、アバランシェが急速に起こるので、
アバランシェを起していない半導体ベレットの接合容量
を介して、パルスノイズとしてカソード側に伝わり、や
はり、チューナー回路に伝播して、ブラウン管画lll
1に悪影響を及ぼす(以下、このノイズをアバランシェ
ノイズと称す)。
When a voltage higher than the reverse breakdown voltage is applied to the semiconductor pellet on the anode side, the semiconductor pellet reaches the alancier region and locally causes avalanche. The current that flows at this time flows from the floating valley through the avalanche-generated semiconductor pellet to the flyback transformer, but since avalanche occurs rapidly,
It is transmitted as pulse noise to the cathode side through the junction capacitance of the semiconductor bullet that has not caused avalanche, and is also transmitted to the tuner circuit, causing the cathode ray tube picture
1 (hereinafter, this noise will be referred to as avalanche noise).

従来、導通ノイズを低減するために、異なったライフタ
イムキラーが添加された半導体ベレットを組合せて用い
、アバランシェノイズに対しては、半導体ぺ1ノツトの
積層枚数を増加させる試みがあるが、十分とは云えず、
また、工程条件のVA調がとれないことや、製作工程が
煩雑であった。
Conventionally, attempts have been made to use a combination of semiconductor pellets to which different lifetime killers have been added in order to reduce conduction noise, and to increase the number of stacked semiconductor pellets to reduce avalanche noise, but these efforts have not been sufficient. I can't say it,
In addition, VA adjustment of the process conditions could not be achieved and the manufacturing process was complicated.

従って、本発明の目的は、導通ノイズ、アバランシェノ
イズを共に除去でき、かつ、製造の容易な半導体装置を
提供するにある。
Therefore, an object of the present invention is to provide a semiconductor device that can eliminate both conduction noise and avalanche noise and is easy to manufacture.

上記目的を達成する本発明の特徴とするところハ、カソ
ード側に高抵抗体を介装したことにある。
A feature of the present invention that achieves the above object is (3) that a high-resistance element is interposed on the cathode side.

以F1本発明を図面に示す実施例に基づいて説明する。Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

第1図において、1は全体として本発明になる高圧半導
体装置を示しており、2a、2bはタングステンまたは
モリブデンのTJ tffiで、銅を主成分トスるり−
ド3a、31)がパーカッション溶接すれている。電極
2a、2b間にはpn接合を有する複数枚のシリコンベ
レット4a、4b・・・4nがその整流方向を揃えて積
層されている。−例として、[Yf 2 aから電極2
bに向う方向に整流方向が揃えられている。従って、電
極2aはアノード側電極、電極2bはカソード側ri極
でちる。電極2aとンリコンベンッ)4aの間には、p
n接合を■しないシリコンのスペーサ5が、電1it 
2 b トシリコンベレノト4nの間にはpn接合を有
しないシリコンの高抵抗体6が介装さhている。W、極
2aから電極2bまでの各部材間は図示していないアル
ミニウム鑞によシ接着されている。一方の電極2aから
他方のt極2bにかけて、この積層接着体の周囲をガラ
ス7でモールドしている。ガラス7はシリコンペレット
4a、4b・・・4nに対する表面安定化機能を持つも
ので、−例としてZn0 8203 5i(h系ガラス
が用いられる。
In FIG. 1, 1 indicates the high voltage semiconductor device according to the present invention as a whole, and 2a and 2b are TJ tffi made of tungsten or molybdenum, with copper as the main component.
3a, 31) are percussion welded. Between the electrodes 2a and 2b, a plurality of silicon pellets 4a, 4b, . . . , 4n having pn junctions are stacked with their rectifying directions aligned. - As an example, [Yf 2 a to electrode 2
The rectification direction is aligned in the direction toward b. Therefore, the electrode 2a is an anode side electrode, and the electrode 2b is a cathode side RI electrode. There is a p
The silicon spacer 5 that does not form an n-junction is
A silicon high-resistance element 6 having no pn junction is interposed between the silicon bezels 2b and 4n. W, each member from the pole 2a to the electrode 2b is bonded by aluminum solder (not shown). The periphery of this laminated adhesive body is molded with glass 7 from one electrode 2a to the other t-electrode 2b. The glass 7 has a surface stabilizing function for the silicon pellets 4a, 4b, .

各シリコンベンツ)4a、4b・・・4nはpin構造
となっており、白金がライフタイムキラーとして添加さ
れている。シリコンスペーサ5はp型導遊性で、その比
抵抗は0.01Ω−(1)以下のもので、抵抗値はせい
ぜい70mΩ程度であるので、導体とみてさしつかえな
い。高抵抗体6はn型導電性で、その比抵抗は約100
0Ω−(7)である。アルミニウム鑞により、接着時に
表向にp型再成長層が形成されないようにするため、表
面にはn型品濃度層が形成されている。高濃度層にはさ
まれた比抵抗が約1000Ω−(7)の頭載は、約10
にΩの■(抗値を持っている。
Each silicon vent (4a, 4b...4n) has a pin structure, and platinum is added as a lifetime killer. The silicon spacer 5 has p-type conductivity, and has a specific resistance of 0.01 Ω-(1) or less, and a resistance value of about 70 mΩ at most, so it can be regarded as a conductor. The high resistance element 6 has n-type conductivity, and its specific resistance is approximately 100.
0Ω-(7). In order to prevent the formation of a p-type regrowth layer on the surface of the aluminum solder during bonding, an n-type product concentration layer is formed on the surface. The resistivity of the resistivity of about 1000Ω-(7) sandwiched between the high concentration layers is about 10
Ω ■ (has an anti-value.

この高圧半導体装置1は次のようにして製作される。This high voltage semiconductor device 1 is manufactured as follows.

先ス、シリコンペレット4a、4b・・・4nとシリコ
ンスペーサ5、シリコン高抵抗体の積ノー接着体を得る
。この時、その積)@方向で断面を揃え、棒状とする。
First, a bonded body of silicon pellets 4a, 4b, . . . , 4n, silicon spacer 5, and silicon high resistance material is obtained. At this time, the cross sections are aligned in the (product)@ direction to form a rod shape.

一方、電極2a、2bにリード3a。On the other hand, leads 3a are attached to the electrodes 2a and 2b.

3bを溶接したものを用意しておき、電極2a。Prepare a welded electrode 3b and use it as the electrode 2a.

2b間に先に得た棒状の積層接着体を配置して、アルミ
ニウム鑞で、更に一体化する。ZnO−B2O35i0
2系ガラスのスラリーをこの一体化物にまきつけ、加熱
し、モールドガラス7とする。
The rod-shaped laminated adhesive obtained earlier is placed between 2b and further integrated with aluminum solder. ZnO-B2O35i0
A slurry of 2-series glass is spread over this integrated product and heated to form molded glass 7.

シリコンベレット4a、4nとスペーサs、高抵抗体6
は同一材質であるから、シリコンベンッ)4a、4bに
は熱歪が加わらない。また、ガラススラリーを焼結する
時、”RL電極 a 、 2 bとスペーサ5、高抵抗
体6の空間部Aに気泡ができやすいがシリコンベレン)
4a、4nには達せず、従って、シリコンベンッ)4a
、4nの特性は劣化しない。
Silicon pellets 4a, 4n, spacer s, high resistance element 6
Since they are made of the same material, no thermal strain is applied to silicone 4a and 4b. Also, when sintering the glass slurry, bubbles are likely to form in the space A between the RL electrodes a, 2b, the spacer 5, and the high-resistance element 6.
4a, 4n are not reached, so silicon ben) 4a
, 4n characteristics do not deteriorate.

次に、高抵抗体6の機能について説明する。Next, the function of the high resistance body 6 will be explained.

電極2bに対し、電極2aが正醒位となる順方向電圧が
印加された時、各シリコンベレット4a。
When a forward voltage is applied to the electrode 2b so that the electrode 2a is in the positive position, each silicon pellet 4a.

4b・・・4nの順回復時間後に順方向′電流が流れる
After a forward recovery time of 4b...4n, a forward current flows.

電圧が印加されない状態においては、各シリコンベレン
)4a、4b・・・4nのpn接合にはわずかながら空
乏ノーが形成されており、接合容量が存在する。ft圧
が印加され、接合容量が充電されて導通に到るが、その
順回復時間、即ち、充電時間は、接ハ容)栓と抵抗の積
で表わされる時定数で決まる。
In a state where no voltage is applied, a slight depletion node is formed in the pn junction of each silicon belenium 4a, 4b, . . . , 4n, and a junction capacitance exists. ft pressure is applied, the junction capacitance is charged and conduction is reached, but the recovery time, that is, the charging time, is determined by a time constant expressed by the product of the contact capacitance and the resistance.

高抵抗体6が介装されているために、時定数は大きくな
り、順回復時間は長くなる。従って、順回復時の電流立
上率di/dtが小さくなり、逆起電圧Cが小さくなっ
て、導通ノイズが発生しない。
Since the high resistance element 6 is interposed, the time constant becomes large and the normal recovery time becomes long. Therefore, the current rise rate di/dt during forward recovery becomes small, the back electromotive force C becomes small, and conduction noise does not occur.

また、高圧半導体装置1に逆方回ル圧が印カロされた時
、重圧分担率の不均一から、アノード側のシリコンベレ
ットにアバランシェが局部的に発生し、パルスノイズが
発生しても、その波高値が高抵抗体6で制限されるため
、チューナー回路に伝播したとしても、ブラウン管には
アバランシェノイズとして伝わらない。
Furthermore, when reverse circulation pressure is applied to the high-voltage semiconductor device 1, avalanche occurs locally in the silicon pellet on the anode side due to uneven pressure distribution, and even if pulse noise is generated, Since the peak value is limited by the high resistance element 6, even if it propagates to the tuner circuit, it will not be transmitted to the cathode ray tube as avalanche noise.

第2図は、フライバックトランスの出力磁圧波形21と
ブラウン庁の無信号時の映像信号電圧波形220位相関
係を示している。
FIG. 2 shows the phase relationship between the output magnetic pressure waveform 21 of the flyback transformer and the video signal voltage waveform 220 of the Brown Agency when there is no signal.

映像信号磁圧波形22中に点線で示した波形はノイズ波
形であり、23は導通ノイズによるものであす、24 
a−24bはアバランシェノイズによるものである。
The waveform indicated by a dotted line in the video signal magnetic pressure waveform 22 is a noise waveform, and 23 is due to conduction noise, 24
a-24b is due to avalanche noise.

従来の高圧半導体装置を用いた場合では、ノイズ波23
.24a、24bを伴っていたが、本発明による高圧半
導体装置を用いた場合には、ノイズ?7fi23.24
a、24bは見られなかった。
When using a conventional high voltage semiconductor device, noise waves 23
.. 24a and 24b, but when using the high voltage semiconductor device according to the present invention, noise? 7fi23.24
a and 24b were not observed.

ノイズがブラウン管に現われやすい高感度白黒テレビジ
ョン受像機の場合、高抵抗体6の抵抗値としては、8に
Ω以上であれば、ノイズ発生を抑えられることが実験に
上り確認された。
In the case of a high-sensitivity black-and-white television receiver in which noise is likely to appear on a cathode ray tube, it has been experimentally confirmed that noise generation can be suppressed if the resistance value of the high-resistance element 6 is 8Ω or more.

水平偏向回路を流れる平均ビーム電流はわずかであるた
め、高抵抗体6を高圧半導体装置1が内蔵していても、
発生熱損失は無視できる。
Since the average beam current flowing through the horizontal deflection circuit is small, even if the high voltage semiconductor device 1 includes the high resistance element 6,
The heat loss generated is negligible.

約1 、OKΩの抵抗値を持たせるためには、高抵抗体
6は0.25〜0.4Bの長さでよく、高圧半導体装#
1の大きさは高抵抗体6を内蛎していても、従来のもの
とほとんど変らない。近年、高圧半導体装[dをフライ
バックトランス内に組へむことが行なわれているが、本
発明の高圧半導体装置1は使用者のこのような要請にも
十分応じられるものであろう 寸た、従来順方向に電流が流れている時、カソード側高
市1位露出部と接地電位部の間で放電を起し、各シリコ
ンベレット4a、4b・・・4nに多大な電流が流れて
、熱破壊を起すことがあったが、本発明により、げ、高
抵抗体6が電流を制限するため、各7リコンペレツト4
a、4b・・・4nは熱破壊から免れ、長寿命を保つ。
In order to have a resistance value of approximately 1,000Ω, the high resistance element 6 may have a length of 0.25 to 0.4B, and the high voltage semiconductor device #
1 is almost the same size as the conventional one even though it has a high resistance element 6 inside. In recent years, high-voltage semiconductor devices [d] have been assembled into flyback transformers, and the high-voltage semiconductor device 1 of the present invention is designed to meet the needs of users. Conventionally, when a current flows in the forward direction, a discharge occurs between the exposed part of the cathode side and the ground potential part, and a large current flows through each silicon pellet 4a, 4b, . . . 4n, However, according to the present invention, the high resistance element 6 limits the current, so each of the 7 recomp pellets 4
a, 4b, . . . , 4n are spared from thermal damage and maintain a long life.

高抵抗体6を内蔵することで、シリコンベンツ)4a、
4b・・・4nは同一仕様で作られたものを用いること
ができ、また、積層接着するだけで内蔵させることがで
きるので、製造は容易である。
By incorporating a high resistance element 6, silicon Benz) 4a,
4b...4n can be made with the same specifications, and can be built-in simply by laminating and bonding, so manufacturing is easy.

使用昔にしてみれば、高抵抗をわざわざ接続する必要が
ないので、1吏用件も同上している。
In the past, there was no need to go to the trouble of connecting high resistance, so the requirements for the first officer were the same as above.

次に、本発明の実施態様について説明する。Next, embodiments of the present invention will be described.

(【)高抵抗体6にスペーサの機能を兼ねさせるために
は、を極2 bに隣接していることが有効であるが、半
導体ペレットがアバランシェを起さない領域のカソード
側に位置するなら、介装位置は制限されない。
([) In order for the high-resistance element 6 to also function as a spacer, it is effective to have it adjacent to the pole 2b, but if the semiconductor pellet is located on the cathode side in a region where avalanche does not occur, then , the intervening position is not restricted.

(2)高抵抗体6の導電型はp型でもよい。(2) The conductivity type of the high-resistance element 6 may be p-type.

(3)絶縁物7はガラスに限らず、樹脂であってもよい
。樹脂モールドの場合、表面安定化相とモールド利の二
重構造でもよい。
(3) The insulator 7 is not limited to glass, and may be made of resin. In the case of a resin mold, it may have a dual structure of a surface stabilizing phase and a mold layer.

(4)  リード3a、3bがなく、所謂、プラグイン
ノ41J、であってもよい。
(4) It may be a so-called plug-in 41J without the leads 3a and 3b.

(5)高抵抗体6は半導体よりなるものに限らない。(5) The high resistance body 6 is not limited to one made of a semiconductor.

(6)  成べへ2a、2bを省略し、スペーサ5、高
抵抗体6を成極2a、2bとして、それぞれ兼用しても
よい。
(6) The components 2a and 2b may be omitted, and the spacer 5 and the high resistance body 6 may be used as the polarizations 2a and 2b, respectively.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す高圧半導体装tt’t
の断面図、第2図は第1図に示す高圧半導体装14をテ
レビジョン受像機の水平偏向回路に用いた時のフライバ
ックトランスの出力重圧波形とブラウンげにおける無信
号時の映1象信号電圧波形を示す図である。 ■・・・高圧半導体装置、2a、2b・・・電極、3a
FIG. 1 shows a high voltage semiconductor device showing one embodiment of the present invention.
FIG. 2 shows the output heavy pressure waveform of the flyback transformer when the high voltage semiconductor device 14 shown in FIG. FIG. 3 is a diagram showing voltage waveforms. ■...High voltage semiconductor device, 2a, 2b...Electrode, 3a
.

Claims (1)

【特許請求の範囲】[Claims] 1.1対の電極の間にpn接合を有し、高周波動作を行
なう複数枚の半導体ベレットをその整流方向を揃えて積
ノーシ、かつ、そのカソード側に高抵抗体を介装して、
相互間を鑞材で接着し、この積ノー接着体を絶縁物でモ
ールドしていることを特徴とする半導体装置。 2、第1項において、高抵抗体はカソード側電極に隣接
して設けられていることを特徴とする半導体装置。 3、第1項において、高抵抗体は半導体からなることを
特徴とする半導体装置。 4、第1項において、各半導体ベレットと高抵抗体はそ
の積層方向において同一断面を有していることを特徴と
する半導体装置。
1. A plurality of semiconductor pellets having a pn junction between a pair of electrodes and performing high frequency operation are stacked with their rectifying directions aligned, and a high resistance material is interposed on the cathode side,
1. A semiconductor device characterized in that a solder material is used to bond the two together, and the bonded product is molded with an insulating material. 2. The semiconductor device according to item 1, wherein the high resistance element is provided adjacent to the cathode side electrode. 3. The semiconductor device according to item 1, wherein the high resistance body is made of a semiconductor. 4. The semiconductor device according to item 1, wherein each semiconductor pellet and the high-resistance element have the same cross section in the stacking direction.
JP12724882A 1982-07-20 1982-07-20 Semiconductor device Pending JPS5917276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12724882A JPS5917276A (en) 1982-07-20 1982-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12724882A JPS5917276A (en) 1982-07-20 1982-07-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5917276A true JPS5917276A (en) 1984-01-28

Family

ID=14955355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12724882A Pending JPS5917276A (en) 1982-07-20 1982-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5917276A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952974A (en) * 1972-09-22 1974-05-23
JPS4934674B1 (en) * 1969-06-25 1974-09-17
JPS5011388A (en) * 1973-05-30 1975-02-05
JPS5472984A (en) * 1977-11-24 1979-06-11 Hitachi Ltd Semiconductor rectifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934674B1 (en) * 1969-06-25 1974-09-17
JPS4952974A (en) * 1972-09-22 1974-05-23
JPS5011388A (en) * 1973-05-30 1975-02-05
JPS5472984A (en) * 1977-11-24 1979-06-11 Hitachi Ltd Semiconductor rectifier

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