JPS5917244A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5917244A JPS5917244A JP12569282A JP12569282A JPS5917244A JP S5917244 A JPS5917244 A JP S5917244A JP 12569282 A JP12569282 A JP 12569282A JP 12569282 A JP12569282 A JP 12569282A JP S5917244 A JPS5917244 A JP S5917244A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- concentration
- gallium
- silicon substrate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 238000009826 distribution Methods 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052733 gallium Inorganic materials 0.000 abstract description 24
- 238000000137 annealing Methods 0.000 abstract description 11
- 150000002500 ions Chemical class 0.000 abstract description 4
- -1 silicon ions Chemical class 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 102100030704 Interleukin-21 Human genes 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 108010074108 interleukin-21 Proteins 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000000348 solid-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特に、シリコン
基板内に急しゅんな濃度分布を持つｐ”ｐ″″″層甘ｎ
ｐ＋層を形成するのに好適な半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular, a p"p""" layer having a steep concentration distribution in a silicon substrate is manufactured.
The present invention relates to a method of manufacturing a semiconductor device suitable for forming a p+ layer.
従来、不純物濃度が極端に異なシ、かつ濃度分布が急し
ゅんになるような２つの不純物ドーピング層を、結晶軸
を同一面方位にして形成する場合、気相エピタキシャル
成長法により行なっている。Conventionally, when two impurity doped layers with extremely different impurity concentrations and steep concentration distributions are formed with their crystal axes oriented in the same plane, a vapor phase epitaxial growth method is used.
例えば、表面側に低濃度のｐ一層を、基板側に高濃度の
９１層を形成する場合、つまＩ） ｐ−ｐ”層を形成す
る場合、高濃度のｐ３拡ｆ！！１層を有するシリコン基
板表面上に低濃度のｐ−成長層を気相エピタキシャル成
長によシ形成する方法を用いる。For example, when forming a low concentration p layer on the surface side and a high concentration 91 layer on the substrate side, when forming a p-p'' layer, a high concentration p3 expanded f!!1 layer is formed. A method is used in which a low concentration p- growth layer is formed on the surface of a silicon substrate by vapor phase epitaxial growth.
このとき、成長層の形成は、Ｈ１雰囲気中で、成長温度
が１１００〜１２５０ Ｃの条件で行なわれ、反応ガス
として５ｉＣ７，ガス、ｐ型不純物ドーピングガスとし
てＢ２Ｈａガスを供給して行なっておシ、また、成長層
の不純物濃度制御はＢＱＨｅガス流量によｐ制御してい
る。At this time, the growth layer was formed in an H1 atmosphere at a growth temperature of 1100 to 1250 C, and was performed by supplying 5iC7 gas as a reaction gas and B2Ha gas as a p-type impurity doping gas. Moreover, the impurity concentration of the grown layer is controlled by the BQHe gas flow rate.
しかしながら、この方法では、（１）反応温度が高いの
でシリコン基板中のｐ型不純物が成長層に拡散するオー
トドーピングが生じるために比較的薄い成長層を得るこ
とが困難である、（２）結晶軸をそろえるためにはシリ
コン基板表面の清浄度に非常な注意をはらう必要がある
、（３）成長法が複雑かつ高価である、等の問題があっ
た。However, with this method, (1) the high reaction temperature causes autodoping in which p-type impurities in the silicon substrate diffuse into the growth layer, making it difficult to obtain a relatively thin growth layer; (2) it is difficult to obtain a relatively thin growth layer; In order to align the axes, it is necessary to pay great attention to the cleanliness of the silicon substrate surface, and (3) the growth method is complicated and expensive.
本発明の目的は、従来の不純物ａ度が異なシ急しゅんな
濃１に分布を持つ２種類の層を形成する方法の有する上
記問題を解決し、イオン打込みにより生じた非晶質層を
アニールすることにより、単結晶に回復させることによ
シ、容易に、かつ、制仰性良く急しゅんな濃度分布を持
つ２つの層を形成することのできる半導体装置の製造方
法を提供することにある。The purpose of the present invention is to solve the above-mentioned problems of the conventional method of forming two types of layers with different impurity a degrees and sharply distributed concentrations, and to anneal an amorphous layer produced by ion implantation. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can easily form two layers having a sharp concentration distribution with good controllability by recovering a single crystal. .
上記目的を達成するため、本発明は、シリコン基板にガ
リウム等のｎ型不純物を拡散させ高濃度のｐ＋層を形成
したのち、上記ｐ＋層の表面附近にシリコン等のイオン
打込みを行ない非晶質層を形成し、その後、ｎ型不純物
の拡散が殆んど生ずることなにし、上記非晶質層を単結
晶に回復させる程度の流度でアニールを行なうことによ
り、上記非晶質層のｎ型不純物濃度を低トさせｐ一層を
形成し、上記シリコン基板内に不純物ｌ＃度の異なる急
しゅんな濃度分布を持つ２つの層を形成するものである
。In order to achieve the above object, the present invention diffuses n-type impurities such as gallium into a silicon substrate to form a highly concentrated p+ layer, and then implants silicon or other ions near the surface of the p+ layer to form an amorphous layer. The n-type layer of the amorphous layer is formed by forming a layer, and then annealing is performed at such a rate that the amorphous layer is restored to a single crystal without almost any diffusion of n-type impurities. A single p layer is formed by lowering the type impurity concentration, and two layers having steep concentration distributions with different impurity levels are formed in the silicon substrate.
次に、本発明によりｐ一層が形成できる理由を第１図〜
第３図を用いて説明する。Next, the reason why a p-layer can be formed according to the present invention is explained in Figs.
This will be explained using FIG.
第１図に示すように、基板濃度１のシリコン基板にガリ
ウム等のｎ型不純物を拡散し、曲線２のｎ型不純物の分
布を形成したのち、シリコン等のイオン打込みを行なう
と、曲線３の結晶欠陥の分゛布を持つ非晶質層が形成さ
れる。As shown in Figure 1, after diffusing an n-type impurity such as gallium into a silicon substrate with a substrate concentration of 1 to form an n-type impurity distribution of curve 2, when ions of silicon or the like are implanted, the result is a curve 3. An amorphous layer with a distribution of crystal defects is formed.
そこで、この非晶質層をアニールして固相エピタキシャ
ル成長によシ単結晶に回復させる際、第２図に示すよう
に、上記ｎ型不純物は結晶欠陥の影響を受けて非晶質側
に偏析しやすい性質を持つので、非晶質層と単結晶界面
に高濃度層５を形成し、単結晶化された部分には低濃度
層６が形成される。Therefore, when this amorphous layer is annealed and recovered to a single crystal by solid-phase epitaxial growth, the n-type impurity segregates to the amorphous side due to the influence of crystal defects, as shown in Figure 2. Therefore, a high concentration layer 5 is formed at the interface between the amorphous layer and the single crystal, and a low concentration layer 6 is formed at the single crystallized portion.
さらにアニールを続けると、第３図に示すように、非晶
質層内のｎ型不純物の殆んどは、非晶質層の回復と共に
シリコン基板表面側に移動してしまい、また、シリコン
基板表面に達したｎ型不純物は、アニール雰囲気中に散
逸してしまうため、低濃度層７が、打込み直後の非晶質
層と単結晶の界面から、シリコン基板表面寸で形成され
る。If annealing is continued further, as shown in Figure 3, most of the n-type impurities in the amorphous layer will move to the silicon substrate surface side as the amorphous layer recovers, and the silicon substrate Since the n-type impurity that has reached the surface is dissipated into the annealing atmosphere, a low concentration layer 7 is formed from the interface between the amorphous layer and the single crystal immediately after implantation to the size of the silicon substrate surface.
さらにこの時、シリコン基板の濃度１が、上記のように
形成された低＃に層７のＳ度より大きく、かつ、ｎ型不
純物によシ成っている場合、非晶質層が形成された部分
には、ｎ型反転層が形成される。Furthermore, at this time, if the concentration 1 of the silicon substrate is higher than the S degree of the low # layer 7 formed as described above and is composed of n-type impurities, an amorphous layer is formed. An n-type inversion layer is formed in the portion.
Ｉた、打込み直後の非晶質層と単結晶の界面の部分での
濃度分布は非常に急しゅんなものとなる。Furthermore, the concentration distribution at the interface between the amorphous layer and the single crystal immediately after implantation becomes very steep.
その他、打込み時の結晶欠陥が多い程、ｎ型不純物は結
晶欠陥に偏析しやすく、また、非晶質Ｉ響の深さは打込
みエネルギーに依存することから、上記のように形成さ
れる低濃度層の深さや＃度は、イオン打込み条件によ逆
制御できる。In addition, the more crystal defects there are during implantation, the easier it is for n-type impurities to segregate into the crystal defects, and the depth of the amorphous I-sound depends on the implantation energy. The depth and depth of the layer can be controlled by changing the ion implantation conditions.
以下、本発明の実施例を詳細に説明する。Examples of the present invention will be described in detail below.
まず、ｐ−ｐ＋層の形成について、第４図〜第７図を用
いて説明する。First, the formation of the pp+ layer will be explained using FIGS. 4 to 7.
第４図に示すように、抵抗率が１０〜２０Ω−のｎ型シ
リコン基板８に、ｌ１００Ｃでガリウムを３０分間拡散
し、表面濃興が１ｘ１０１９ｃｒｎ−３および接合深さ
が２５μｍの９１層９を形成した。As shown in FIG. 4, gallium is diffused at l100C for 30 minutes into an n-type silicon substrate 8 having a resistivity of 10 to 20 Ω- to form a 91 layer 9 with a surface concentration of 1×1019 crn-3 and a junction depth of 25 μm. Formed.
次に、第５図に示すように、シリコンイオンを２００
ｋｅｙで５ Ｘ １０ ” ６ｉｏｎｓ ／Ｃｒｎ２だ
けイオン打込みし、深さ約０．４μｍの非晶質層ｉｔを
形成した。Next, as shown in FIG.
Ion implantation was performed using a key of 5×10”6ions/Crn2 to form an amorphous layer it with a depth of about 0.4 μm.
その後、第６図に示すように、６００１；、３０分のア
ニールを行ない、非晶質層１１を単結晶に回復させ、か
つ、非晶質層１１の領域のガリウム濃度を低下させ、ｐ
一層１２を形成することによシ、ｐ”ｐ＋層を形成した
。Thereafter, as shown in FIG. 6, annealing is performed for 30 minutes to recover the amorphous layer 11 to a single crystal, lower the gallium concentration in the region of the amorphous layer 11, and reduce the gallium concentration in the region of the amorphous layer 11.
By forming one layer 12, a p''p+ layer was formed.
この際、シリコンイオン打込みにより形成された非晶質
層は、アニールによシ固相エヒリキシャル成長し、非晶
質層中の結晶欠陥が基板中のガリウムを偏析しながら、
表面側に単結晶化している。At this time, the amorphous layer formed by silicon ion implantation undergoes solid phase epitaxy growth by annealing, and crystal defects in the amorphous layer segregate gallium in the substrate.
It is single crystallized on the surface side.
ここで、基枡表面側に達したガリウムは、アニール雰囲
気中に散逸するため、非晶質層中のガリウムの殆んどは
シリコン基板に存在できなくなシ、その結果とし７て、
ガリウムの低濃度層が形成される。Here, since the gallium that has reached the surface of the base cell is dissipated into the annealing atmosphere, most of the gallium in the amorphous layer cannot exist in the silicon substrate, and as a result,
A low concentration layer of gallium is formed.
このようにして得られたガリウムの低ＩＪ１層の濃度は
、最初のガリウム濃度より３桁程度低下してしまうため
、第７図の破線１３で示した濃度を持つｎ型シリコン基
板中のガリウム濃度分布は、第７図の実１腺１４で示さ
れたように、濃度差が３桁程度の急しゅんな分布となる
。The concentration of gallium in the low IJ layer thus obtained is about three orders of magnitude lower than the initial gallium concentration. As shown in fruit 1 gland 14 in FIG. 7, the distribution is steep with a concentration difference of about three orders of magnitude.
次に、ｎｐ＋層を形成した例を説明する。Next, an example in which an np+ layer is formed will be described.
第４図において、ｎ型シリコン基板の抵抗率を０．１Ω
・口程度とすることにより、上記第４図〜第６図で説明
した処理を行ない、第６図のガリウム低濃度層１２の部
分にｎ型反転層を形成し、ｎｐ＋層を形成した。In Figure 4, the resistivity of the n-type silicon substrate is 0.1Ω.
- By making it about the same level as above, the process explained in FIGS. 4 to 6 above was performed, and an n-type inversion layer was formed in the portion of the low concentration gallium layer 12 in FIG. 6, and an np+ layer was formed.
このとき、第７図で示したように、ガリウム低濃度１脅
の濃度が、上記ｎ型シリコン基板のａ度１５より小さく
なるため、シリコン基板の表向部分はｎ型反転する。At this time, as shown in FIG. 7, the concentration of gallium at a low concentration of 1 is lower than the a degree of 15 of the n-type silicon substrate, so that the surface portion of the silicon substrate becomes n-type inverted.
したがって、本発明の方法によりガリウムの低濃度層を
形成し、それを同じ濃度で形成させる場合、シリコン基
板の基板濃度によシ、ｐ−ｐ”層またはｎ ｐ ６層が
形成できる。Therefore, when a low concentration layer of gallium is formed by the method of the present invention and is formed at the same concentration, a p-p'' layer or an n p 6 layer can be formed depending on the substrate concentration of the silicon substrate.
また、イオン打込み条件により、ガリウム低濃度層の濃
度および深さを制御でき、例えば、打込み量を多くする
と非晶質層の結晶欠陥が増え、結晶欠陥の影響を受は非
晶質層側に偏析するガリウムが増加するため、低濃度層
の濃度はさらに低くできる。In addition, the concentration and depth of the low-concentration gallium layer can be controlled by ion implantation conditions. For example, increasing the implantation amount will increase crystal defects in the amorphous layer, and the effect of crystal defects will be on the amorphous layer side. Since more gallium segregates, the concentration of the low concentration layer can be lowered even further.
本発明によれば、比較的低温（〜６００Ｇ）で急しゅん
な濃度分布を持つｐ−ｐ”層やｎｐ＋層を、イオン打込
みを用いることにより、制御性良く、また、非常に浅い
低濃度層やｎ型反転層を形成できるので、これらのｐ−
ｐ＋層やｎ ｐ＋層を形成する際の高精度化、簡素化お
よび低コスト化に非常に効果がある。According to the present invention, by using ion implantation, a p-p'' layer or np+ layer, which has a steep concentration distribution at a relatively low temperature (~600G), can be easily controlled and a very shallow low concentration layer can be formed. These p-
It is very effective in increasing precision, simplifying, and reducing costs when forming a p+ layer or an np+ layer.
例えば、本発明を用いて集積回路を製造する場合、次の
ような効果がある。For example, when manufacturing an integrated circuit using the present invention, the following effects can be obtained.
第８図は、ｐｎｐトランジスタをそれぞれアイソレーシ
ョンして形成した図であり、本発明を用いれば、ｎ型シ
リコン基板８に選択拡散により１１層１６を形成し、そ
の後イオン打込みおよびアニールによ＃）ｐ一層重７を
形成したのち、ｐ−４１７中にｎ型ベース層１８および
ｐ１型エミッタ層１９およびｐ１型コレクタコンタクト
！２０を形成し、ｐ＋層工１をコレクタ領域とすること
により、従来のエピタキシャル成長およびアイソレーシ
ョン拡散の工程を取シ除くことができ、プロセスが非常
に簡単になる。FIG. 8 is a diagram showing pnp transistors formed in isolation, and according to the present invention, 11 layers 16 are formed on an n-type silicon substrate 8 by selective diffusion, and then ion implantation and annealing are performed. After forming the p-layer layer 7, an n-type base layer 18, a p1-type emitter layer 19, and a p1-type collector contact are formed in the p-417! By forming the p+ layer 20 and using the p+ layer 1 as the collector region, the conventional epitaxial growth and isolation diffusion steps can be eliminated, and the process becomes very simple.
第９図は、埋込み抵抗を形成した図であシ、本発明を用
いれば、ｎ型シリコン基板８に選択拡散によ９９１層１
６を形成し、その後イオン打込みおよびアニールにより
ｎ型反転層２１を形成したのち ｐ＋コンタクト層２２
を形成し ｐ ＋層工６を埋込み抵抗領域とすることに
より、従来のエピタキシャル成長工程を取シ除くことが
できる。FIG. 9 is a diagram in which a buried resistor is formed. If the present invention is used, a 991 layer 1 is formed in an n-type silicon substrate 8 by selective diffusion.
After that, an n-type inversion layer 21 is formed by ion implantation and annealing, and then a p+ contact layer 22 is formed.
By forming the p+ layer 6 as a buried resistance region, the conventional epitaxial growth process can be eliminated.
さらに、この埋込み抵抗は、シリコン基板表面からイオ
ン打込み条件によシ任意の深さとすることが可能であシ
、また、埋込み抵抗のシート抵抗は、最初のｐ＋層形成
条件により制御できるため、数Ω／口から数にΩ／口の
値を取ることができ、その他、埋込み抵抗領域上にｎ型
反転層が形成されているため、シリコン基板表面側から
の汚染イオン等の影響を受けることのない高信頼性を有
する抵抗を得ることができる。Furthermore, this buried resistor can be made to any depth from the silicon substrate surface depending on the ion implantation conditions, and the sheet resistance of the buried resistor can be controlled by the initial p+ layer formation conditions, so The value can be calculated from Ω/mm to Ω/mm, and since an n-type inversion layer is formed on the buried resistor region, it is less likely to be affected by contaminant ions from the silicon substrate surface side. It is possible to obtain a resistor with high reliability.
第１図乃至第３図は本発明の原理説明図、第４図乃至第
６図は本発明の一実施例を示す工稈図、第７図は本発明
の効果を示す曲線図、第８図および第９図は本発明の応
用例を示す断面図である。
１．１３．１５・・・ｎ型シリコン基板の濃度、２゜１
４・・・ｐ型不純物濃度分布、３，４・・・非晶質層の
結晶欠陥分布、７・・・低濃度ｐ−１ｍの分布、８・・
・ｎ型シリコン基板、９・・・ガリウム拡散層、１０・
・・シリコンイオン、１１・・・非晶質領域、１２・・
・ガリウム低濃度領域、１６・・・ｐ型不純物高濃度層
、１７・・・ｐ型不純物低濃度層、１８・・・ｎ型ベー
ス層、１９・・・ｐ１型エミンタ層、２０・・・ｐ＋型
コレクタコンタクトＩＬ２１・・・ｎ型反転層、２２・
・・ｐ＋コ第 １ 口
第 ４ 図
１ ↓ １ （＋ φ ↓ ト／θ
χ ６ 目
〉呆さ （Ｐｘ）1 to 3 are diagrams explaining the principle of the present invention, FIGS. 4 to 6 are culm diagrams showing one embodiment of the present invention, FIG. 7 is a curve diagram showing the effects of the present invention, and FIG. 9 and 9 are cross-sectional views showing an application example of the present invention. 1.13.15... Concentration of n-type silicon substrate, 2°1
4... p-type impurity concentration distribution, 3, 4... crystal defect distribution in the amorphous layer, 7... distribution of low concentration p-1m, 8...
・N-type silicon substrate, 9... Gallium diffusion layer, 10.
...Silicon ion, 11...Amorphous region, 12...
・Gallium low concentration region, 16...p type impurity high concentration layer, 17...p type impurity low concentration layer, 18...n type base layer, 19...p1 type emitter layer, 20... p+ type collector contact IL21...n type inversion layer, 22.
...p+ko 1st mouth 4th Fig. 1 ↓ 1 (+ φ ↓ g/θ χ 6th> stupefaction (Px)
Claims (1)
＃度のｐ３型拡散層を形成し、その後イオン打込みによ
シ上記ｐ１型拡散層の表面附近に非晶質層を形成する。 この試料に上記ｐ型不純物の拡散が殆んど生ずることな
しに上記非晶質層を単結晶に回復させるだめのアニール
を施すことにより、上記非晶質層が形成されたｐ“型拡
散層の表面附近に濃度の低いｐ−型層を形成し、シリコ
ン基板内に上記ｐ＋型拡散層と上記ｐ−型層とから成る
急しゅんなａ度分布を持つｐ−ｐ”層を形成することを
特徴とする半導体装置の製造方法。[Claims] 1. A p-type impurity is diffused from the surface of a silicon substrate to form a high-density p3-type diffusion layer, and then ion implantation is performed to form an amorphous layer near the surface of the p1-type diffusion layer. form a layer. This sample is annealed to recover the amorphous layer to a single crystal without causing almost any diffusion of the p-type impurity, resulting in a p"-type diffusion layer in which the amorphous layer is formed. forming a p-type layer with a low concentration near the surface of the silicon substrate, and forming a p-p'' layer with a steep a degree distribution consisting of the p+ type diffusion layer and the p- type layer in the silicon substrate. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12569282A JPS5917244A (en) | 1982-07-21 | 1982-07-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12569282A JPS5917244A (en) | 1982-07-21 | 1982-07-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5917244A true JPS5917244A (en) | 1984-01-28 |
Family
ID=14916330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12569282A Pending JPS5917244A (en) | 1982-07-21 | 1982-07-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5917244A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055588A (en) * | 1988-07-06 | 1991-10-08 | Daicel Chemical Industries Ltd. | Process for preparing N-substituted amino acid esters |
-
1982
- 1982-07-21 JP JP12569282A patent/JPS5917244A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055588A (en) * | 1988-07-06 | 1991-10-08 | Daicel Chemical Industries Ltd. | Process for preparing N-substituted amino acid esters |
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