JPS59171445U - Terminal socket for optical transmission control - Google Patents

Terminal socket for optical transmission control

Info

Publication number
JPS59171445U
JPS59171445U JP1983066368U JP6636883U JPS59171445U JP S59171445 U JPS59171445 U JP S59171445U JP 1983066368 U JP1983066368 U JP 1983066368U JP 6636883 U JP6636883 U JP 6636883U JP S59171445 U JPS59171445 U JP S59171445U
Authority
JP
Japan
Prior art keywords
address
terminal socket
transmission control
section
optical transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983066368U
Other languages
Japanese (ja)
Inventor
榊野 隆弘
Original Assignee
オムロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Priority to JP1983066368U priority Critical patent/JPS59171445U/en
Publication of JPS59171445U publication Critical patent/JPS59171445U/en
Pending legal-status Critical Current

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  • Selective Calling Equipment (AREA)
  • Optical Communication System (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の光伝送制御用ターミナルソケットの全
体の外観図、第2図は光送信回路のブロック回路図、第
3図は主ターミナルソケットの外観斜視図、第4図は主
受信回路部のブロック回路図、第5図は副受信回路部の
ブロック回路図である。 1・・・・・・光伝送制御用ターミナルソケット、2・
・・・・・主ターミナルソケット、3a、  3b、・
・・、  3n・・・・・・副ターミナルソケット、4
・・・・パ・主受信回路部、5・・・・・・光ファイバ
、6・・・・・・光送信回路、11・・・・・・光/電
気変換部、12・・・・・・アドレス判別回路、13・
・・・・・直列/並列変換部、14・・・・・・アドレ
ス制御部、20・・・・・・副受信回路部、23・・・
・・・アドレス制御部、27・・・・・・LEDo−
Fig. 1 is an overall external view of the optical transmission control terminal socket of the present invention, Fig. 2 is a block circuit diagram of the optical transmitting circuit, Fig. 3 is an external perspective view of the main terminal socket, and Fig. 4 is the main receiving circuit. FIG. 5 is a block circuit diagram of the sub-receiving circuit. 1...Terminal socket for optical transmission control, 2.
...Main terminal socket, 3a, 3b,...
..., 3n... Sub-terminal socket, 4
...P-Main receiving circuit section, 5... Optical fiber, 6... Optical transmitting circuit, 11... Optical/electric conversion section, 12...・Address discrimination circuit, 13・
...Serial/parallel conversion section, 14...Address control section, 20...Sub reception circuit section, 23...
...address control unit, 27...LEDo-

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)光送信回路から送り出される光信号を受入れる主
受信回路部を備え、た主ターミナルソケットと、該主タ
ーミナルソケットに連設され、かつ主受信回路部からの
信号を受入れる副受信回路部を備えた複数の副ターミナ
ルソケットとよりなり、主受信回路部は光信号を電気信
号に変換する光/電気変換部と、電気信号からアドレス
を判別し、アドレス信号を出力するアドレス判別回路と
を備え、副受信回路部は主受信回路部から印加されるア
ドレス信号から自己のアドレス信号を検出し作動電流を
出力するアドレス制御部を備えていることを特徴とする
光伝送制御用ターミナルソケット。
(1) A main terminal socket comprising a main receiving circuit section that receives optical signals sent out from the optical transmitting circuit, and a sub-receiving circuit section connected to the main terminal socket and receiving signals from the main receiving circuit section. The main receiving circuit section includes an optical/electrical conversion section that converts an optical signal into an electrical signal, and an address discrimination circuit that discriminates an address from the electrical signal and outputs an address signal. A terminal socket for optical transmission control, characterized in that the sub reception circuit section is equipped with an address control section that detects its own address signal from the address signal applied from the main reception circuit section and outputs an operating current.
(2)前記実用新案登録請求の範囲第1項に記載の光伝
送制御用ターミナルソケットにおいて、前記アドレス判
別回路は印加される電気信号を信号別に区分する直列/
並列変換部と、該並列の信号からアドレスを判別するア
ドレス制御部とよりなる光伝送制御用ターミナルソケッ
ト。
(2) In the optical transmission control terminal socket as set forth in claim 1 of the utility model registration claim, the address discrimination circuit is a serial/
A terminal socket for optical transmission control comprising a parallel conversion section and an address control section that determines an address from the parallel signals.
(3)前記実用新案登録請求の範囲第1項に記載の光伝
送制御用ターミナルソケットにおいて、前記副ターミナ
ルソケットには作動時点灯するモニター用LEDが設け
られている光伝送制御用ターミナルソケット。
(3) The terminal socket for optical transmission control according to claim 1, wherein the sub-terminal socket is provided with a monitoring LED that lights up when activated.
JP1983066368U 1983-05-03 1983-05-03 Terminal socket for optical transmission control Pending JPS59171445U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983066368U JPS59171445U (en) 1983-05-03 1983-05-03 Terminal socket for optical transmission control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983066368U JPS59171445U (en) 1983-05-03 1983-05-03 Terminal socket for optical transmission control

Publications (1)

Publication Number Publication Date
JPS59171445U true JPS59171445U (en) 1984-11-16

Family

ID=30196575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983066368U Pending JPS59171445U (en) 1983-05-03 1983-05-03 Terminal socket for optical transmission control

Country Status (1)

Country Link
JP (1) JPS59171445U (en)

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