JPS59171347U - lead frame - Google Patents
lead frameInfo
- Publication number
- JPS59171347U JPS59171347U JP6483683U JP6483683U JPS59171347U JP S59171347 U JPS59171347 U JP S59171347U JP 6483683 U JP6483683 U JP 6483683U JP 6483683 U JP6483683 U JP 6483683U JP S59171347 U JPS59171347 U JP S59171347U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- center terminal
- island
- lead
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は一個の半導体素子が組み込まれるリードフレー
ムの一例を示す説明図、第2図は第1図に示したリード
フレームに半導体素子を組み込んだ状態を示す説明図、
第3図は2個の半導体素子が組み込まれるときのリード
フレームの説明図、第4図はこの考案の一実施例のリー
ドフレームの要部を示す平面図である。□
10・・・・・・ユニット、12・・・・・・リード端
子、13・・・・・・インナーリード、14.14’、
15A〜15C・・・・・・アイランド。FIG. 1 is an explanatory diagram showing an example of a lead frame in which one semiconductor element is incorporated, FIG. 2 is an explanatory diagram showing a state in which a semiconductor element is incorporated in the lead frame shown in FIG. 1,
FIG. 3 is an explanatory diagram of the lead frame when two semiconductor elements are assembled therein, and FIG. 4 is a plan view showing the main parts of the lead frame of one embodiment of this invention. □ 10...Unit, 12...Lead terminal, 13...Inner lead, 14.14',
15A-15C...Island.
Claims (1)
に隣接した左右の端子にはそれぞれアイランドが備えら
れたことを特徴とするシングルインラインリードフレー
ム。A single in-line lead frame comprising five lead terminals, and a center terminal and left and right terminals adjacent to the center terminal are each provided with an island.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6483683U JPS59171347U (en) | 1983-04-28 | 1983-04-28 | lead frame |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6483683U JPS59171347U (en) | 1983-04-28 | 1983-04-28 | lead frame |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59171347U true JPS59171347U (en) | 1984-11-16 |
Family
ID=30195027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6483683U Pending JPS59171347U (en) | 1983-04-28 | 1983-04-28 | lead frame |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59171347U (en) |
-
1983
- 1983-04-28 JP JP6483683U patent/JPS59171347U/en active Pending
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