JPS59170940A - Read-only fixed memory and multiplying method using this read-only fixed memory - Google Patents

Abstract

PURPOSE:To attain multiplication in a short arithmetic processing time by preparing a ROM specified at the addresses by 8-bit binary data and stored the multiplied value of numbers indicated by high-order 4 bits and low-order 4 bits respectively, and executing multiplication by using said ROM and two registers. CONSTITUTION:A multiplicand P and a multiplier Q which are indicated as 8-bit binary numbers respectively are divided into the parts A, B of the multiplicand P and the parts C, D of the multiplier Q which are indicated as 4-bit data respectively. The multiplied values of all combinations of these 4-bit binary data A, B; C, D are found out. In case of BXD for instance, respective bits of the divided part B consisting of 4- bit binary data are inputted to the address specification input ports AD7-AD4 of the ROM from the upper bit successively and respective bits of the divided part D consisting of 4-bit binary data are inputted to the address specification input ports AD3-AD0 of said ROM from the upper bit successively to obtain the multiplied values from the output ports C7-C0. In the same manner, respective multiplied values of AXD, BXC and AXC are found out. On the basis of BXD, AXD and BXC are shifted by 4 bits respectively. AXC is shifted by 8 bits and these shifted values are added to obtain the multiplied value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a memory value of an address specified by two sets of data input to a J-bit binary board where m-4-n = j? The present invention relates to a read-only fixed storage device output from the output port and a multiplication method using this storage device.

Conventionally, when multiplying binary numbers, as shown in the calculation example below, 1011... Multiplicand (1) XIIOI Multiplicand (2) 1011... (3) 0000・・・・・・-(4) 1011 ・・・・・・(5) 1011 Song...(6) 10001111 ・・・・・・Multiply value (7) Number of digits of multiplicand (1) and multiplier (2) , and each bit of the multiplicand when the corresponding multiplier (2) is ``)''), , :N, and each binary data obtained in this way (3!, (41, (5) and (6) using a two-input adder circuit, [[(: (3! ten (4)) + (51
) By adding sequentially like 10(6)':l,
Multiply value (I'm trying to get power.

However, in such a multiplication method, as the number of digits in the multiplier (2) increases, the number of additions increases accordingly, and t
However, since this addition time is usually relatively long, there is a problem in that the overall calculation time becomes long.

In view of the above-mentioned problems, the present invention has been developed to solve the above-mentioned problem. This was done with the focus on the fact that the time is significantly shorter than the addition time, and the purpose is to enable multiplication in a short calculation processing time. In order to achieve this objective, the present invention provides an addressing input port into which j-bit binary data such as m+n=j is input, and a predetermined output port in the basic read-only fixed storage device. and enter J into the input boat above.
The product value of the tolerances expressed by the predetermined m bits and n bits of the J-bit binary data is stored at the address specified by the bit binary data, and any J-bit binary data is input to the input port. When this happens, output the binary number of the numerical value stored at the above address from the above output port.
As a multiplication method, the binary multiplicand and multiplier are each divided into arbitrary numbers of bits, and each bit of each divided part of the divided multiplicand and multiplier is combined with the address designation board of the above-mentioned read-only fixed storage device. The product value of the divided parts of the multiplicand and the multiplier, which becomes binary data output from the output port by inputting to The product value binary data is shifted by a predetermined bit according to the combination of its divided parts, and each of the shifted product value binary data is added to obtain the product value of the multiplicand and the multiplier.

Embodiments of the present invention will be described below based on the drawings. First, the basic read-only persistent storage, or RO
Let me explain about M. Figure 1 shows 8-bit addressing inputs (ADO, IAD).

AD2. AD3. AD4. A chicken, AD6. A
This is an example of a ROM having 8 bits, and its output port is also 8 bits C61C1lc, , c3. c, , a, ,
a6. c. Then, the address specified by the 8-bit binary data input to the addressing input port is input to the addressing input port AD3.
AD, , , AD, , A'D.

A number represented by 4 bits, and an addressing input port AD7. The product value of AD, , A, AD, and the number represented by 4 bits is stored, and when arbitrary 8-bit binary data is input to the addressing input port, the output port is output as shown in Figure 2. 2 of the product value stored in the address specified by the above 8-bit binary data from 07 to co
It is designed to output decimal numbers. In other words, the 8
Bit binary data is input to address input ports AD3 to AD,
, ,! The product value of each 4-bit binary number divided into :AD, ~AD, is output. For example, address input Kabot Nagi ~
The 8-bit binary data input to ADo is (0011oo
io), the value of the product 3×2 is expressed in binary (00
000110) are output from output ports 07 to Co (addresses 5o and 1fiQ in FIG. 2).

In addition, in this embodiment, ゛γ address square designator capo) A
I), ~8-bit input manually into ADo) The address specified by the binary data corresponds to the number expressed by the 8-bit binary number. For example, if the 8-bit binary code is (00i 10010), the designated address 1/s will be 50.

According to such a read-only IM regularization device OM, for example, the R, OM, and a 4-bit 2-circular number (using two registers each storing the output ports of one register A from the upper The addressing inputs of R and OM shown in Figure 1 are successively connected to the respective output ports of the other register B from the north to the addressing inputs of R and OΔ1. Capo) AI) Each register A is connected to each of 3 to ADo.

A multiplication device for the 4-bit binary number input to B is configured, and the calculation processing time of this multiplication device is approximately the same as that of the ROM.
The readout time is extremely short.

Next, the read-only fixed storage device that has been stagnant until now ↑p
A method of obtaining a multiplied value of a binary number with an even larger number of digits C by using a ROM will be explained.

FIG. 3 is an explanatory diagram showing a method of multiplying an 8-bit binary number by .51-. In this case, Parable 6.2r 1st
It will be used with ROΔ1 shown in FIG.

First, the multiplicand P and the multiplier Q, which are 8-bit binary numbers, are each divided into parts A and B of the multiplicand P and part C2D of the multiplier Q, which are 4-bit binary data.

The divided part A of the multiplicand P that becomes this 4-bit binary data
, B and the divided portion C2] of the multiplier Q, i.e., BXD.

AXD, BXC! , AXC. To find the product value of this divided portion, for example, considering B x D, each bit of divided portion B, which is 4-bit binary data, is input from the upper bit to the addressing address of ROΔ1 shown in FIG. 1 (AD7). ~AJ) 4, and similarly input each bit of the divided portion C, which becomes 4-bit binary data, from the upper bit to the specified input port AD3~ of the ROM.
By inputting A-DoK, its output port Cヮ~
The ratio of 8-bit binary data output from Co is 9:1.
1. Obtain the product value of parts B and C. Similarly, AXD, B
Find the values of XO and AXC.

Here, M function number P, multiplier Q, and division parts A, , B.

The values of 0 and D are respectively p + q + a 1 b,
If c and d, then pXq=(a・2'1-b)-(c-2'-1-d)-
= a*c*2″4-b++ca2’+aedm2’+
It becomes bea. After this step, the 8-bit binary data obtained as described in step 1-BXJ), AXD, BXC
, AXO is 1, f3 are shifted by 4 bits each, and A
xcts bit shift. Then, when added to the product value of each divided portion, which becomes 8-bit binary data shifted in this way, the multiplicand I), ! = The multiplication value by the number of columns Q is obtained.

4-, according to the method described, for example, the multiplicand P=10111
101 (189), multiplier Q211.101100 (23
6) If you are forced to find the multiplier value, the multiplicand P
The divided parts A- and B of are A,=1011, B=1101, and the divided part C2D of multiplier Q is C=1110, D=1100. Figure 1 shows 1 (by OM, BXD,
When calculating AXD, BXC, and AXC, BXD=10011100. AXD=100001
00BXG! =1.0110110, AXC=1
The result is 0011010, which is the product value binary data of the 1111 part? When adding after shifting the specified bits, 10011100...B×]]100
00100...A×1)1011
011.0 --- BXC multiplication value P X Q
'? c 1010111000111100 (446
04).

According to such a multiplication method, the product value of each divided part of the multiplicand and multiplier is determined by the ROM, so the processing time is extremely short, and the multiplier is In the case of 8-bit binary numbers,
Compared to the 8 binary data to be added, in this method, the number of binary numbers to be added is 4, so the addition time is shortened, and the calculation processing time related to multiplication is significantly shortened. be able to.

In addition, as a means for adding the product values of each divided portion, there is an addressing input port into which j-bit binary data is input, as shown in FIG. It has an output port that outputs an n-bit binary number, and the binary input from the n-bit output port when input to the input port at the address specified by the input binary data If the adder ADD is equipped with a plurality of read-only storage ROMs that output the binary value stored at the address specified by the data, the addition time will be equal to the cumulative value of the readout time of each ROM. Therefore, the calculation processing time is further shortened.

Here, the addition device shown in FIG. 4 will be briefly explained. This is an adder that obtains an added value by sequentially adding the same bit μ digits of a 4-bit binary number to the carry digits τ from the lower digits.

In FIG. 4, the read-only fixed storage devices ROMo to ROM constituting the adder ADD have 5-bit input ports ^r A3 + A2 + A4 as shown in FIG.
B2. B, , Bo, and input port A
, 4° A2 , AI , The address specified by the binary data input to Ao is as shown in FIG.
The total number of 11'% in the manual binary data is stored, and the input board input + A, 3 + A2 + AI
When binary data is input to +, the numeric value stored in the address specified by that binary data is output.
2. B, , Bo are output as binary numbers.

In addition, in FIG. 4, each unconnected input port of each ROMo to ROM is set to "0° input."

Here, when performing the following calculation, the operation of the addition device shown in FIG. 4) First, add the above binary number (1) to registers A, B, and C.
, (2) , (When storing 31, ROMo,
ROM, , ROM2゜ROM3 input capo)
A, , , A3.14 is manually input the in-phase bit data of the binary number. Here, ROMQ's addressing input ports 1 and 2 p, , A2 , AI , Ao are (111
00) is input, and as is clear from the table shown in Figure 6,
From the horse, Bl, 13111 (011)
outputs. ROM, addressing input port +
4 r A2 + AI + Enter (01001) in the circle, and similarly its output capo)B2. B,, from BO (
oio) or output. ROM2 address input port input + 4 + A2 + AI + bird (11, 1
B2. B,
, (100) is output from Bo. ROM3 address designation input Mr. Bo 5, A3. A2. A1. (11000) is input to A43, and similarly its output ()B2
．． (010) is output from B,,Bl). ROM
, enters the addressing input port of A3. A2. Ao, A
(00011) is input to Q, and the output cap-)
B2. B, , BO outputs (010). ROM, addressing input gate A4. A3. A2
．． A1. (ooooi) is input to A4, and similarly its output boat horse, B1. (001) is output from BO. As a result, the output port of each ROM and each bit of the output port B1 of the ROM are represented by the sum D5.
．． D4. D3. D2. DI, D, is (0100001)
This matches the calculation result (4) of the above calculation example.

The calculation time of such an adding device is ROMo to OM,
This is only the cumulative value of the readout time, which is extremely short.

When the adder ADD of the adder shown in FIG. 4 is used as the adder S of the product value binary data of each shifted divided portion in the present invention shown in FIG. Number of base numbers, i.e. 4 (BXD, AXI)
, BXC, AXO) and the actual number of bits to be implemented considering the number of shifts of the binary number to be added, that is, 1Xl bits.
The number of ROMs may be determined, and the ROMs may be connected in parallel as shown in FIG. 4.

Now, the read-only fixed storage device shown in Figure 1? X
Although the method of multiplying 8-bit binary numbers using 11.0M has been described, this ROM can also be used to multiply binary numbers of even more bits. For example, in the case of multiplication between 16-bit binary numbers, if &J is divided into 4 pieces with 4 bits each, the result will be as shown in Figure 7, and the shift number of the product value binary data of each divided part is shown in Figure 8. It is as shown. Further, according to the present invention, a more general In bit 2
Multiplication of a base number and an n-bit binary number is also possible.

Further, in the above embodiment, the multiplicand and the multiplier are each divided into 4 bits, but the invention is not limited to this. For example, the 8-bit multiplicand and the multiplier may be divided into 5 bits and 3 bits, respectively. . However, in this case, 7y number of read-only fixed storage devices will be used in correspondence with each number of bits.

As explained above, by providing the read-only fixed storage device 6 according to the present invention, it is possible to achieve the effect that multiplication can be performed in a significantly short calculation processing time.

[Brief explanation of the drawing]

FIG. 1 shows an input/output board in an embodiment of the read-only fixed storage device according to the present invention. The explanatory diagram shown in Fig. 2 is the first
An explanatory diagram showing the storage contents of the read-only fixed storage device and its input/output relationship, FIG. 3 is the read-only fixed storage device shown in FIGS. 1 and 2? An explanatory diagram showing an example of the multiplication method according to the present invention used, FIG. 4 is a block diagram showing an example of an addition device that can be used in the multiplication method according to the present invention, and FIG. An explanatory diagram showing the input/output ports of the read-only fixed storage device, FIG. 6 is a description of the read-only fixed storage device shown in FIG. 5.1. Is there a relationship between the content and the person's output? FIG. 7 is an explanatory diagram showing another example of the multiplication method according to the present invention, and FIG. 8 is an explanatory diagram showing the shift number of the product value binary data of each divided portion in the multiplication method of FIG. 7. It is. Patent applicant: Kokusai System Sangyo Co., Ltd.
Request person Takashi Maruoka Figure 8 勺・Yuki・V catty A crushed 11 pieces

Claims (2)

[Claims] (1) It has an addressing manual port into which j-bit binary data such that m + n = j is input, and a predetermined output port; The product value of the specified m bits and n bits of the J-bit binary data is stored in the address, and when any J-bit binary data is input to the input port, the above output port is stored. A read-only fixed storage device configured to output the 2'a number of product values stored at the above address from . (2) The multiplicand and the multiplier each consisting of a binary number are divided into arbitrary bit positions, and there are two addressing input ports into which one j-bit binary data of the multiplicand is input, and a predetermined output port, and the above-mentioned At the address specified by the J-bit binary data input to the input port, is the product value of the specified m bits and n bits of the J-bit binary data? Addressing input of a read-only fixed storage device such that when arbitrary j-bit binary data is input to the input input port, the output port outputs the stored product value in binary from the output port. By inputting it into the boat, the product value of the divided parts of the multiplicand and multiplier is obtained, which becomes binary data output from the output boat.
The product value binary data of each divided part obtained for all the divided part combinations of the multiplicand and the multiplier is shifted by a predetermined number of digits according to the combination of the divided parts, and each of the shifted product value binary data is Did you add the multiplicand and the multiplier to get the product value? Featured multiplication method.