JPS59169111U - oscillation device - Google Patents

oscillation device

Info

Publication number
JPS59169111U
JPS59169111U JP6401183U JP6401183U JPS59169111U JP S59169111 U JPS59169111 U JP S59169111U JP 6401183 U JP6401183 U JP 6401183U JP 6401183 U JP6401183 U JP 6401183U JP S59169111 U JPS59169111 U JP S59169111U
Authority
JP
Japan
Prior art keywords
amplifier circuit
circuit
oscillation device
amplification gain
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6401183U
Other languages
Japanese (ja)
Inventor
眞 高山
Original Assignee
キヤノン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by キヤノン株式会社 filed Critical キヤノン株式会社
Priority to JP6401183U priority Critical patent/JPS59169111U/en
Publication of JPS59169111U publication Critical patent/JPS59169111U/en
Pending legal-status Critical Current

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は発振装置の従来の構成を示す図、第2因は第1
図会部の波形を示す波形図、第3図は本考案による発振
装置の基本的な原理を示す図、第 4図は本考案の原理
を説明するための図、第5図は本考案の一実施例の回路
構成を示す図、第6図は第5図会部の波形を示す波形図
、第7図は温度依存性抵抗器を具体化した一実施例を示
す図であ   、る。 12は制御信号発生回路、16はオペアンプ、19はF
ETである。
Figure 1 is a diagram showing the conventional configuration of an oscillation device, and the second factor is the first
Figure 3 is a diagram showing the basic principle of the oscillation device according to the present invention, Figure 4 is a diagram for explaining the principle of the present invention, and Figure 5 is a diagram showing the waveform of the present invention. FIG. 6 is a waveform diagram showing the waveform of the section shown in FIG. 5, and FIG. 7 is a diagram showing an embodiment of a temperature-dependent resistor. 12 is a control signal generation circuit, 16 is an operational amplifier, and 19 is F.
It is ET.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 増幅回路と、該増幅回路の出力を移送して正帰還する移
相回路と、ソース−ドレイン抵抗が前記増幅回路の増幅
利得を制御するFETと、該FETの温度特性を補償す
るため前記増幅回路の増幅利得を制御する温度補償回路
とを具える発振装置。
an amplifier circuit; a phase shift circuit for transferring the output of the amplifier circuit for positive feedback; a FET whose source-drain resistance controls the amplification gain of the amplifier circuit; and the amplifier circuit for compensating the temperature characteristics of the FET. and a temperature compensation circuit that controls the amplification gain of the oscillator.
JP6401183U 1983-04-28 1983-04-28 oscillation device Pending JPS59169111U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6401183U JPS59169111U (en) 1983-04-28 1983-04-28 oscillation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6401183U JPS59169111U (en) 1983-04-28 1983-04-28 oscillation device

Publications (1)

Publication Number Publication Date
JPS59169111U true JPS59169111U (en) 1984-11-12

Family

ID=30194194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6401183U Pending JPS59169111U (en) 1983-04-28 1983-04-28 oscillation device

Country Status (1)

Country Link
JP (1) JPS59169111U (en)

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