JPS59168998A - Copying system of stored information - Google Patents

Copying system of stored information

Info

Publication number
JPS59168998A
JPS59168998A JP58044886A JP4488683A JPS59168998A JP S59168998 A JPS59168998 A JP S59168998A JP 58044886 A JP58044886 A JP 58044886A JP 4488683 A JP4488683 A JP 4488683A JP S59168998 A JPS59168998 A JP S59168998A
Authority
JP
Japan
Prior art keywords
information
cpu1
central processing
processing unit
impediment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58044886A
Other languages
Japanese (ja)
Other versions
JPH0236014B2 (en
Inventor
Yoshinobu Torikai
鳥飼 義信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58044886A priority Critical patent/JPS59168998A/en
Publication of JPS59168998A publication Critical patent/JPS59168998A/en
Publication of JPH0236014B2 publication Critical patent/JPH0236014B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation

Abstract

PURPOSE:To quicken dumping process and improve operation efficiency of a central processing unit by adding the second virtual memory area to the central processing unit system and dumping information of real memory area when occurrence of impediment, and operating the system using the second virtual memory area in place of the virtual memory. CONSTITUTION:The second direct access memory DASD5 is added, and when an impediment occurs at point A during operation of the CPU1 and operation of the system becomes impossible, information stored in a main memory MSU2 is shunted to a magnetic tape device MT4 and stored in MT4. This transfer is made immediately without needing time. The CPU1 cuts off DASD3 and combined with the second DASD5, and program restoring IPL is executed and operation of the CPU1 is started. When necessary afterward, data at the time of occurrence of impediment is dumped from DASD3 and MT4.

Description

【発明の詳細な説明】 (a)  発明の技術分封 本発明は実記憶坂とり想記憶域とを砲する中央処理装置
が障害を発生した場合に、障害発生時の両記憶域にある
情報を複写する記憶情報の複写方式の改善に−するもの
でろる。
DETAILED DESCRIPTION OF THE INVENTION (a) Separation of techniques of the invention The present invention provides a system that, when a failure occurs in the central processing unit that stores both the real and virtual storage areas, the information existing in both storage areas at the time of the failure is recovered. This is intended to improve the method of copying stored information to be copied.

(b)従来技術と間塵点 従来中央処理装置が連用中に障害を発生すると実記憚域
吉仮想記偲域とを障害発生時点にて保存し障害対策を行
なうといったことが一般に用いられており、この記憶域
の情報保存のために障害発生時の状態を検案(以後ダン
プと記、す)することが行われている。第1図は従来の
記憶情報の模写方式を説明するための模式図であり、1
は中法処理装置(cpU)、  2は主記憶装置(MS
U)、  3は直接アクセス記憶装置(DASD)、 
 4はi気デーブ装置(MT)、  (以後各々は活弧
内文字を用いる)である。DA 8D 3は領域をペー
ジ単位に分割され情報を格納している。中央処理装置1
が連用を開始するのに先ずDASD3上の初期フログラ
ムをMSA格納する。(以後IPLと記す)格納後CP
旧は運用が行われる。連用中細等かの御由でシステムに
障害がA点にて発生すると障害発生時のMSU 2とD
ASD3との情報(以後データと記す)をMT4にタン
プする。タンプが終了するとシステムは工PLを開始し
0PUIはha用が行われる。しかしながらこの工程中
CPUtはDAE]D3のデータを&収ってデータをt
f11xシ、しかる後にMT4にデータを格納するとい
った手順を必要とし、処理に時間がかかるといった欠点
があった。
(b) Discrepancies between the conventional technology and the conventional technology When a failure occurs in a central processing unit during continuous use, it is generally used to save a real memory area and a virtual memory area at the time of the failure to take measures against the failure. In order to preserve information in this storage area, the state at the time of failure is analyzed (hereinafter referred to as dump). FIG. 1 is a schematic diagram for explaining a conventional method of copying stored information.
is the central processing unit (cpU), and 2 is the main memory (MS).
U), 3 is a direct access storage device (DASD),
4 is an i-device device (MT) (hereinafter, letters in parentheses will be used for each). The area of DA 8D 3 is divided into pages and stores information therein. Central processing unit 1
To start continuous use, first the initial program on DASD 3 is stored in the MSA. (hereinafter referred to as IPL) CP after storage
The old one is still in operation. If a system failure occurs at point A due to continuous use, etc., MSUs 2 and D at the time of failure occur.
Tamp the information with ASD3 (hereinafter referred to as data) into MT4. When the stamp is completed, the system starts the engineering PL and the 0PUI is used for ha. However, during this process, the CPU t collects the data of DAE]D3 and stores the data t.
f11x, and then storing the data in MT4, which has the drawback of taking time to process.

(C)弁明の目的 本発明は上記従来の欠点に鎚み、ダンプ処理が早く行な
え中央処片装置の近用効率が向上する記憶情報の複写方
式を提供することを目的とするものである。
(C) Purpose of Defense The present invention addresses the above-mentioned drawbacks of the prior art, and aims to provide a method for copying stored information that enables quick dump processing and improves the near-use efficiency of the central processing unit.

(cl)  発明の構成 w隼に述べると本発明は、中央処理装置システムに第2
の仮禿記憶域を付設し、障杏発生時に前記失記憶域の情
報を複写するとともに前記仮想記憶に替えて第2の伊想
記情、域を用いてシステムを逆用するようにしたことを
特徴とするものであり。
(cl) Structure of the Invention To describe it to Hayabusa, the present invention has a central processing unit system with a second
A virtual storage area is attached, and when a failure occurs, the information in the lost storage area is copied, and the system is reversely used by using a second memory area in place of the virtual storage. It is characterized by

タンプの処理時間の短縁がi」能となる。The short edge of the processing time of the tamp becomes i'' function.

(e)  欠・、明の実施例 以下木発、明の実施例を図によって詳細に説明する。(e) Missing/Bright Examples Hereinafter, embodiments of the invention will be described in detail with reference to the drawings.

第2図は不発1明による記憶情報の4写方式を示す一実
施例の捗弐図でおり、第1図と同−仇1所は同符号を用
いるとともにその説明もる1賂する。
FIG. 2 is a progress diagram of an embodiment showing a four-copy system for storing information according to the invention, and the same reference numerals as in FIG. 1 are used for the same parts as in FIG.

図において、5は面接アクセス記儂装屓(以後シ、2の
1)ASrlと記す)、6は株S チー−>装置(以後
MTとル1す)をそれぞれ示す12本弁5明が従来例と
気々る部分は第2のDASJ−5を伺股した点であるJ
(’PUIが違用中A点にて障シー゛を弁生じシステム
通用か不可ちト、となるとMSU2に格卸1された情報
けMT4に走避されMT4に格納される。この転送は時
NをνせすIちに行なわれる。C田lばDAbD3をν
)りけなし第2のDAEID5と結合し再IPLが実行
され、 CPU1の】!ヒ用が開始される。後刻必要で
あればDASD3とMT4から一劉・弁生時のデータを
MT6にタンプする。
In the figure, 5 indicates the interview access recording equipment (hereinafter referred to as 2, 1) ASrl), and 6 indicates the stock S Q->device (hereinafter referred to as MT), respectively. An example of this is that the second DASJ-5 was introduced.
(When the PUI is being misused, a fault is generated at point A. If the system is not valid or not, the information transferred to MSU2 is evacuated to MT4 and stored in MT4. This transfer is performed at time N. It is done immediately when ν is set.
) is combined with the second DAE ID5 and re-IPL is executed, and the ]! of CPU1 is executed. The application starts. If needed later, data from DASD3 and MT4 at the time of Ichiryu and Bensei can be tamped into MT6.

(f)  発明の効果 以上、詳細に説、明したように1本づ〔・明の記憶情報
の撥写力式にタンプ処理が早く行なえ中央処坤装置の運
用効率が回−1ニするものとなり中沫処f411装置a
システムを連用する上で第1(虞の多いものとなる。
(f) Effects of the invention As explained and clarified in detail, the tamping process can be performed quickly by using the repellent type of memory information, and the operational efficiency of the central processing device is increased by 1. Next door Nakamori F411 device a
This is the first problem when using the system repeatedly.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の記憶情報の栓型方式を説明するための模
式図、第2図は本発明による記(た情報の作写方式を示
す一実施例の模式図である。 図において、2は注記(萩装置、3と5は面接アクセヌ
記1通装置、4と6は御気テーフ装置をそれぞれ示す。 第1図 第2図
FIG. 1 is a schematic diagram for explaining a conventional plug-type method for storing information, and FIG. 2 is a schematic diagram of an embodiment showing a method for creating recorded information according to the present invention. 1 indicates the notes (Hagi device, 3 and 5 indicate the interview access letter device, and 4 and 6 indicate the Oki Tefu device. Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims] 実記憶製と休息記憶域とからなる中央処理装置システム
における助記両記憶域の情報を複写する方式であって、
該システムに第2の仮想記憶域を付設し、障害発生時に
11」記実記憶域の情報を複写するとともに前記仮想記
憶にもえて前記第2の仮想記憶域を用いてシステムを運
用するようにしたことを特徴とする記憶情報の複写方式
A method for copying information in both auxiliary storage areas in a central processing unit system consisting of a real storage area and a rest storage area, the method comprising:
A second virtual storage area is attached to the system, and when a failure occurs, the information in the 11'' memory storage area is copied, and the system is operated using the second virtual storage area instead of the virtual storage. A method for copying stored information characterized by the following.
JP58044886A 1983-03-16 1983-03-16 Copying system of stored information Granted JPS59168998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58044886A JPS59168998A (en) 1983-03-16 1983-03-16 Copying system of stored information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58044886A JPS59168998A (en) 1983-03-16 1983-03-16 Copying system of stored information

Publications (2)

Publication Number Publication Date
JPS59168998A true JPS59168998A (en) 1984-09-22
JPH0236014B2 JPH0236014B2 (en) 1990-08-15

Family

ID=12703964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58044886A Granted JPS59168998A (en) 1983-03-16 1983-03-16 Copying system of stored information

Country Status (1)

Country Link
JP (1) JPS59168998A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6952793B2 (en) 2000-05-18 2005-10-04 Hitachi, Ltd. Computer system and methods for acquiring dump information and system recovery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5389632A (en) * 1977-01-19 1978-08-07 Hitachi Ltd Backup system of auxiliary memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5389632A (en) * 1977-01-19 1978-08-07 Hitachi Ltd Backup system of auxiliary memory unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6952793B2 (en) 2000-05-18 2005-10-04 Hitachi, Ltd. Computer system and methods for acquiring dump information and system recovery

Also Published As

Publication number Publication date
JPH0236014B2 (en) 1990-08-15

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