JPS59168522A - Gate controller for power converter - Google Patents

Abstract

PURPOSE:To apply automatically a prescribed pattern to a prescribed CTO at a prescribed time point by writing previously a gate pulse pattern to an ROM and applying a timing signal to the ROM. CONSTITUTION:The input and the output of an ROM210 are connected to an address terminal and a data terminal respectively to form a phase data table which the higher harmonic wave is minimized to the current deviation. A pulse generator 220 uses a synchronizing power supply as an input to supply clocks to counters 230 and 240 and at the same time delivers a flag to show the up-count or down-count. These counters 230 and 240 supply the information on the current deviation and the phase signal in addition to the clock counting direction and deliver material signals PL1, PL2, PA1 and PA2 to a constitution unit 250 for production of a gate pulse pattern. Thus the unit 250 produces a gate pulse pattern and delivers it to a distributor 260.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a power conversion device, and particularly to a gate control device for a power conversion device that can provide a high fundamental wave power factor.

[Background of the invention]

FIG. 1 shows a control device which obtains a variable DC voltage from a three-phase AC brazing source and applies it to the armature of a DC motor. 3-phase AC turtle ME, U from.

V, W(7) 3-phase tZ)-i1! Pressure is 6 [lf lister Ul,.

The output voltage Er of the three-phase full-wave thyristor bridge when applied to the AC terminal of the three-phase full-wave thyristor bridge from U2, Vt, V2, Wt, and W2 is the phase that generates the gate pulse of each thyristor. is applied to the armature M of the DC motor.

The phase at which the gate pulse is generated (for the thyristor Ul, this can be expressed as an electrical angle delay from the point when the voltages of the U and W phases switch to positive; hereinafter this will be referred to as the control delay angle) is α. The DC output voltage Ex at a certain time is expressed as V1 EL=□ ・Ell・cO5α ...... River (1) π However, when the control delay angle α is zero, the DC output voltage E
The relationships among the output voltage waveform, U-phase voltage waveform, and U-phase current waveform when L is maximum and when α = 90° and DC output voltage BL is zero are shown in Figures 2 (a) and (b). It becomes like this. Figure 2(a) assumes that the time constant of the armature M of the DC motor is sufficiently longer than the period of the power supply, and that the DC voltage of the load EO
The waveform is Uv assuming that the back electromotive force of the DC motor is slightly lower than the output voltage EL.

V v , Wv is the phase voltage, EL is the output voltage, Ur is U
It is a phase current.

When the output voltage EL is maximum, the center value of the U-phase current UX matches the center value (maximum value) of the Ua voltage Uv, and u
The phase of the fundamental wave component of the sliding electric current Rf, U
Consistent with v, the power factor is the highest for such a control system.

However, as shown in Fig. 2(b), when the output voltage EL is zero, the center of the U-phase current UI is at the zero point of the U-phase voltage Uv ('v'), and the basic point of the U-phase current Ur is It can be said that the wave component is delayed by 90' from the U-phase voltage Uv and has a power factor of zero.

In this way, the method of controlling the output voltage EL by controlling the firing angle of the three-phase full-wave thyristor bridge is as follows:
Especially the output voltage Ei.

It has the disadvantage that the power factor becomes poor in a low range.

In order to solve this power factor problem, a system as shown in FIG. 3 has been proposed in which a GTO (gate turn-off thyristor) is used as a control element for a three-phase bridge. This method does not perform phase control on the GTO, but performs chopping control, so it has the effect of making the fundamental wave power factor 1. However, it has the disadvantage that siggate control is complicated, which is different from the case of a thyristor bridge.

The reason why it is complicated is that the GTO has to be forced to extinguish instead of firing, the order of doing so is complicated, and the firing and extinguishing operations have to be performed at high frequency. According to etc.

Therefore, as shown in the figure, the gate control circuit receives the DC current, current command, and synchronous power supply into the microcontroller μ, calculates the necessary data to generate the necessary firing pulse, and sends the data to the programmable timer modules PTMI to PTM6. A method is adopted in which the GTO is controlled by setting and activating it.

In this case, the microcontroller calculates the current deviation, continuously refers to the firing and extinguishing data stored in the ROM in association with this value, selects it, and performs interpolation processing as necessary. It is determined which firing or extinguishing data is given to which GTO according to the interrupt signal of the corresponding GT.
Processing such as setting data in the connected counter and activating the counter must be performed at a very high speed. Furthermore, the lag in the timing of ignition and extinguishment of the GTO promotes the generation of an abnormal voltage of tl+n in the power supply line, causing damage to the GTO.

Considering these points, it can be said that the gate control circuit of the type in which the microcomputer shown in FIG. 3 is dedicated to gate control has a problem in reliability.

[Purpose of the invention]

The present invention has been made in view of the above, and an object thereof is to provide a gate control device for a power conversion device that can realize a high power factor with a simple circuit configuration.

[Summary of the invention]

A feature of the present invention is that it is equipped with a device for generating a plurality of gate patterns that can change according to commands, and that a table of combinations of gate turns and elements to be applied is written in advance in a ROM. The gate control device has a simple circuit configuration that can automatically apply a predetermined pulse turn to a predetermined GTO at a predetermined time by applying a timing signal obtained from a synchronous power supply to the ROM.

[Embodiments of the invention]

The present invention will be described below using an illustrative embodiment.

FIG. 4 shows a schematic configuration of an embodiment of the present invention.

01 to G6 are gate turn-off thyristors (GTO) D
1 to D6 are reverse voltage blocking diodes, which can be omitted if the GTO itself has sufficient reverse blocking ability. Eσ.

Ev and Ew are the power supply, ts and rs are the line inductance and resistance, RL and L are the load resistance and inductance, l
2 is a comparator that calculates the deviation λ between the current command Ic and the feedback current INF, and 2 is a comparator that calculates the deviation λ between the current command Ic and the feedback current INF.
This is a gate signal generator for providing a predetermined gate signal to the

With this circuit configuration, for example, a GTOO firing pattern as shown in FIG. 5 is generated and a voltage waveform is realized. This diagram shows the chopped voltage (
The case where the number of divisions N=6) is applied to the load is shown. The f+ line portion of the voltage waveform is the DC output voltage, and the black portion of the pattern indicates the conduction period of G and TO. Also, alphabets A, B, C..., X
, Y indicate correspondence with gate Hals patterns, which will be described later. Furthermore, in the figure, λ is a current deviation signal, α is a phase signal, and Tc is a carrier wave period.

For example, the states of ignition and extinction will be explained in terms of time.

During the period 1o-11, 03 and 06 in FIG. 4 are turned on, and the power is not supplied from the power source and the load energy is circulated, which is the circulation mode. From t1 to t2, 03 is turned off, G1 is turned on, and energy is supplied from the power source to the load, which is a conduction mode. From t2 to t3, G1 is turned off and G2 is turned on, and energy is supplied from the power supply through a different route than before. The reason why the output voltage is cut according to the size of αTc when changing the power ring route is unequal pulse control to bring the load current waveform closer to a full sine wave in order to reduce harmonics. be. From t3 to t4, it is in the circulation mode again. By combining the conduction mode and the freewheeling mode in this way, the effective value of the applied voltage is changed isometrically, the phases of the voltage and current match, the power factor is improved, and the load current is made into a sine wave. This also reduces harmonics.

To change the DC output voltage, the value of λTc or λ is changed to change the conduction time. αTc is changed according to a pre-prepared procedure so that harmonics are minimized in accordance with the value of λTc.

Next, what kind of circuit specifically implements pulse generation control will be explained with reference to FIG. 6 and subsequent figures.

FIG. 6 is a diagram showing the configuration of the gate signal generator 2 in detail. 210 inputs the current deviation λ and outputs the phase signal α
The output is a λ−α data table, where λ
α is determined so that the harmonics are minimized. The input/output relationship is a read-only memory in which the input is connected to the address terminal and the output is connected to the data terminal. 220
is a clock and timing generator which inputs the synchronous power supply fB and outputs a clock to the counters 230 and 240 and a flag indicating whether it is an UP count or a DN count. The counters 230 and 240 input information λ and α in addition to the clock and the counting direction, and input the information λ and α, respectively.
A waveform like PLI r PL2+ PAL v Pmu2 shown in the figure is generated. At time point AO, when data corresponding to time is set in 4 counters (2 counters are included in 230 and 240) and started, each counter is set to AI, A4.
, A2, A3, the count ends and the output changes from OH to 1''
, the carrier wave period maintains its value, and the same operation is repeated again at time point A5. That is, FIG. 6 shows the waveform for two periods. PLI created from this λ and α information,
Px, z + PAL, PA2 are gate pulse no.
Aba configurator 2 with a signal that is the material for creating a turn
50 is entered.

250 is PLI r PL2, PAI, PA2
A, B, C, etc. in Fig. 7 using the 4 signals as input.
This is a logic circuit that creates 11 types of gate pulse patterns: ・, X, and Y. If there are these 11 types of gate pulse patterns, it is only necessary to operate the selector so as to give a pattern to the GTO according to a certain rule. An example of how to provide the gate pulse pattern created by this configurator 250 is shown in FIG. Looking at the pattern, GTO2 is GTOI, GT
O3 has a repeated gate pulse pattern delayed by 120 degrees with respect to GTO2, GTO5 has repeated gate pulse patterns with a delay of 120 degrees with respect to G'l'04, and GTO6 has repeated gate pulse patterns with a delay of 120 degrees with respect to GTO5. I understand that. As shown in FIG. 8, this constructor 250 creates a gate pulse pattern by inputting PLI, Psr, PAI, PA2 created by λ and α, so when λ and α change, A, E, C, ..., the X and Y signals also change. Therefore, FIG. 7 shows an example of a gate pulse pattern for certain α and λ. This gate pulse pattern is arranged in the order shown at the bottom of FIG.
It is sufficient if the voltage is applied to G1 to G6. Selection of this gate pulse pattern is performed by selectors 261 to 266 in separator 260 shown in FIG. Selector output is 01
It is connected to the gate of ~G6, and the input is created by the configurator 250 to form Taket-Hals patterns A, B, C...
X and Y are ordered in advance as shown in FIG. 10(a) and input to data input terminals Eo=, Et4 of each selector 261-266. Each selector 261
The purpose of connecting the gate pulse patterns to each of the input terminals 266 to 266 in advance in order is to facilitate the selection of pulse patterns from the select terminals. Select terminal Ao-1s of each selector 261 to 266
The selection data D o = of the indicator 268, which will be described later, is
D7 is connected.

Next, we will show how the selection data D o = D t is created. The selection data is associated with an indicator 268 that creates time elapsed information from a synchronous power supply and which input pulse pattern 'W TO' gate of each selector 261 to 266 is to be applied to the gate at each time point using this time elapsed information as input. It is created by the determiner 267 which is a memory. Indicator 268 for creating time elapsed information from the synchronous power source
Let's explain. The indicator 268 inputs the synchronization power supply fB, divides the 1f @ period of the synchronization source into 12 carrier wave periods, and indicates which of the 12 carrier wave periods the current state is in as Qm~QD. It has the function shown by f.

The output waveforms Qm to QD of this indicator are shown in FIG. 11.

Next, the determiner 267 will be explained. The determiner is 11 (, OMI) of several 10 bytes. That is, as shown in FIG.
Data bus D o = D with 5 g and p1 output
7 are connected to the select terminals Ao-A3 of selectors 261 to 266 (7). Regarding the connection between this time, please refer to the first
The procedure shown in θ diagram (b) may be followed. The reason why the selection information of the selector could be simplified in this way is because of the data input E o -E 1 of the data selectors 261 to 266.
The gate pulse pattern connected to the terminal of 4 is 261
. . . 266, all of them are the same. 7k (, repeating f every 120 degrees: The point is that they are connected in advance.

Now, the order in which gate pulse patterns are selected will be specifically shown using FIG. 5 and FIGS. 1O to 12. In Figure 11, at the moment when the synchronous power supply turns O, fa = Q = QB
=QC=QD=0, so the ROM address inputs in FIG. 12 are all 01. Therefore, the data outputs are all 01 up to Do=Dy. Therefore, as shown in FIG.
266 A o = A s is all 0 human effort, so selector data input E. -E14, the signal Eo becomes the output of the selector. In other words, the selector 261 outputs the pulse pattern F'', and the pulse pattern 262 outputs the pulse pattern 'B''.
263 outputs "Q", 264 outputs 'Y', 265 outputs i'l:"Y", and 266 outputs "X". Next, when the first carrier wave period, which is obtained by dividing the half cycle of the power supply into 6, has elapsed, from FIG. is Do−D3” 1, D4~D?=1, that is, Do=D4=1. DI=D2=Dll=
D5 = Da = D7 = 0, Er of the selector input terminal is selected, and the pulse patterns are Y# for 261, 'C'' for 262, and 26
"R" is output for 3, "A" for 264, 'P' for 265, and 'D' for 266. This matches the pulse pattern table for the second carrier cycle period in FIG. Next, when the second carrier wave cycle period divided into 6 ends, the indicator output is as shown in Figure 11') Qn =
1, QJL = QC = QD = fs "O"),
From Figure 12, Do-D3 is 3, that is, Do "Dt
= 1, D2 = Ds ”O, D4 to D7 are 2, that is, Ds = l, D4 = D6 = D7 = 0, the first
As shown in FIG. 0(b), for the selectors 261 to 263, each input terminal E2 is connected to the selector 264 to 266.
For each input terminal E3 is selected. As shown in the figure (a), the output of the Q selector 261 is 6Y'', 26
2 is ``X'', 263 is ``Y#, 264 bar B'
, 265H"Q", 266 corresponds to "F" and corresponds to the pulse pattern table of the third carrier cycle period in FIG.

As explained above, a logic circuit is provided that generates multiple gate pulse patterns that may be used as pulse signals of the GTO according to the pre-commands λ and Which GTO pattern
Since the information given to the gate circuit is made into a table in the ROM, the circuit configuration can be made simple with only λ and a synchronous power supply, so the gate pulse pattern for 1.7λ is made into a table The ROM capacity and processing time are superior compared to a method in which control is performed while selecting the ROM capacity and processing time.

2. The ROM table for determining the turn is simple because the inputs to the selector for selecting the gate pulse pattern are ordered in advance.

3. It is superior in terms of load factor and reliability compared to a method in which the microcomputer determines the firing order of the GTO and selects the mode pulse every time an interrupt is processed.

The effects of the present invention are significant in these respects.

The above explanation is based on the case of row F, but when it is necessary to perform regeneration, processing to shift the phase by -jC180° may be performed in order to invert the synchronous power supply.

Further, although a control example in which the power supply half cycle is divided into 6 parts has been described here, it is also possible to easily reduce the pulsation rate with respect to the load by dividing the power supply half cycle into 12 parts. Regarding this change, increasing the period of the indicator 268 and determining unit 2
This can be achieved by adding the contents of the 67 ROM, and can be realized without changing the component that creates the gate pulse pattern. Note that the ROM content will be doubled or its absolute amount will be at most 24 bytes, which is no real problem. FIG. 13 shows the experimental results when the number of pulse divisions was increased from 6 to 12.

According to this embodiment, in order to create a gate signal for a controllable switchgear such as a GTO, a configuration device is provided which takes only the current deviation λ as input and generates a predetermined mode pulse. Since the configuration is such that the order in which the GTO is applied to each GTO is stored in advance in the ROM, control of the GTO converter that requires a complicated firing order can be easily achieved by simply providing the current deviation λ and the synchronous power supply fs. There is an effect that can be done.

〔Effect of the invention〕

According to the present invention, the gate control device of the power conversion device can have a simple circuit configuration, and therefore, the sophisticated gate control required for achieving a high power factor can be easily realized. .

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining a conventional power conversion device and its operation, and FIGS. 4 to 13 are diagrams for explaining an embodiment of the present invention, and FIG. A block diagram showing the overall configuration of the device, FIG. 5 is an explanatory diagram of the operation of FIG. 4, FIG. 6 is a configuration diagram of the gate signal generator, FIG. 7 is a signal waveform diagram of FIG. 6, and FIG. 8 is the configuration. FIG. 9 is a circuit diagram of the distributor, and FIGS. 10 to 13 are operation explanatory diagrams. G□~G6...Switching element having an electric element cutoff function, 2
...Gate signal generator, 210...λ-α table, 220...Clock & timing pulse generator, 230...Counter % for λ, 240...Counter for α, 250...Configurator , 260... distributor, 2
61-266...Selector, 267...Determiner, 2
68...\l \〜-, / ″′/D Activation 5I2Il Moge

Claims (1)

[Scope of Claims] A power conversion device comprising a 16 AC power source and a plurality of controlled rectifying elements that convert power between the AC power source and the DC power. a pattern creation device that creates a plurality of gate pulse patterns common to the plurality of control rectifiers that change according to a command; a pattern creation device that inputs a signal synchronized with the AC power source and applies the plurality of gate pulse patterns to the control rectifier; A gate control device for a power conversion device, characterized by comprising a distribution device for distributing power. 2. The pattern creation device generates a plurality of constituent signals for each carrier wave period by inputting the first table for determining the modulation degree according to the command, the command and the modulation degree case.
2. The gate control device for a power conversion device according to claim 1, further comprising: a counter; and a creator that creates a plurality of pulse patterns by inputting a configuration signal that is an output of the counter. 3. The gate for a power conversion device according to claim 1, wherein the first table is written in a read-only memory that uses at least the command as an address input and the optimum modulation degree as a data output. Control device. 4. The distribution device includes a plurality of selectors that receive the plurality of gate pulse patterns as input, and a decision device that determines which gate pulse pattern to select from among the gate pulse patterns input to the selectors. A gate control device for a power conversion device according to claim 1, characterized in that: 5. The determining device has a synchronous power source as an input, an indicator indicating the elapsed time from the start of operation, a signal from this indicator as an address input, and a second lead option in which selection information of the selector is written. 5. A gate control device for a power conversion device according to claim 4, wherein the gate control device is comprised of an IJ-memory. 6. The gate control device for a power conversion device according to claim 1, wherein the controlled rectifying element is a controlled rectifying element having a self-extinguishing function.