JPS59167161A - Trouble position searching system of digital transmission line - Google Patents

Abstract

PURPOSE:To detect a trouble position with one operation by measuring the code error rate of a corresponding repeating section at every repeating point and measuring the code error rate of the whole of a line in a receiving terminal station. CONSTITUTION:A transmitting terminal station 1 converts an original code (a) to a parity code (b). After this parity code is converted to an AMI (alternate mark inversion) code (c), it is transmitted from a transmitter 2 to a transmission line 3. If an error shown by a dotted line in Fig. (d) is generated while the AMI code (c) is transmitted through the transmission line 3, a repeater 4 detects this error and registers it and encoding it again so that the AMI rule is satisfied for the next section, and the code is transmitted. Thus, in the next section, a code error rate of only this section can be detected. Meanwhile, the code error rate of the whole of the line is detected with parity check by returning the code to an original code (f) in a receiving terminal station 5. At each repeating point, the number of code error is transmitted from a trouble signal transmitting circuit 6 when it exceeds a prescribed limit.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a fault location search method for a digital transmission path, and particularly to a search method that can detect the fault location of a repeater in a digital transmission path with a single operation. It is.

[Prior art]

Digital transmission paths include coaxial cables, wireless relays,
Alternatively, millimeter wave waveguides have been used, but recently PCM optical transmission lines using optical fibers are often used. this is,
This method modulates signals with and without optical pulses. First, multiple channels such as telephone signals are input to an encoding circuit via a line multiplexing circuit and converted into a PCM electrical signal. On the other hand, a clock signal is injected into the semiconductor laser by a current to generate an optical pulse. A PCM modulation signal is applied to an optical modulator, and the modulated optical pulse is input to an optical fiber transmission line via an optical coupling circuit (unidirectional waveguide, monitor, etc.). Since the optical pulse at the end of the optical fiber becomes dull,
The equalizer restores the original pulse and extracts it as a received signal. If there is a repeater on the way, the signal passes through an equalizer, becomes an electrical signal, drives the semiconductor laser again, and is sent to the next section of transmission line.

In such an optical transmission line, a photodiode (LD
), it is especially difficult to detect faults in repeaters, and recently there has been a demand for this to be done in-service (during operation).

In conventional digital transmission, in order to search for fault locations in repeaters in-service, the bit error rate at each relay point is measured, the bit error rate for each relay section is calculated from the results, and the error rate is determined in which section. It is necessary to determine whether a serious code error has occurred (Sanno, Hakamada [A method for in-service monitoring of repeater performance in optical transmission systems], 1972)
(Refer to the preliminary presentation number 2234 for the Annual National Conference of the Institute of Electronics and Communication Engineers).

A conventional fault location searching method will be explained with reference to FIG. 1B.

In FIG. 1B, the digital signal sent from the transmitter 2 at the transmitting terminal station 1 is degraded in the middle of the transmission line 3, but this is compensated for and strengthened by the repeater 4, and then sent to the next section. If a failure occurs in this relay function, the transmitting terminal station 11
Alternatively, in the receiving terminal station 5, it is necessary to remotely detect which repeater unit is causing the failure. For this purpose, the transmitted signal is encoded in such a way that errors can be detected, and the detected code errors are transmitted via the fault signal sending circuit 6 and through the intervening cable 7. Transmitting terminal station 1 or receiving terminal station 5
Then, the error rate for each relay section is calculated by totaling the code errors detected at each relay point and calculating the difference between the code error rates detected at adjacent relay points, and then determining in which section the failure occurred. Decide what you are doing. By adding a signal or address having a national frequency to the charge information sent from each relay point, code errors can be totaled at the receiving or transmitting terminal. Because it is necessary to find the difference in bit error rates between adjacent relay points, in order to find out where the largest errors are occurring, it is necessary to measure and calculate the bit error rates of all repeaters, which saves time and This is not a practical method as it is time consuming.

[Purpose of the invention]

The purpose of the present invention is to improve the conventional problems as described above,
At each relay point, the code error rate of the corresponding relay section can be measured, and at the receiving end station, the code error rate of the entire line can be measured, and the fault location can be detected with a single operation, reducing search time and effort. The purpose of this invention is to provide a method for locating faults in digital transmission lines.

[Summary of the invention]

In the digital transmission path fault location search method of the present invention, the transmitting terminal applies two types of error detection encoding to the original signal and transmits it, and each relay point uses one of the 14 error detection codes to detect code errors. After that, only the error detection code mentioned above is re-encoded and sent to the next relay point, and by measuring the detected code error rate, it is transmitted or received that a failure has occurred in the corresponding relay section. The feature is that the terminal station is notified, and the receiving terminal station uses the other error detection code for the received signal to detect the overall code error of the line.

[Embodiments of the invention]

Figures 1A and 1B are a time chart and a diagram of digital transmission code processing showing an embodiment of the present invention.

As shown in FIG. 1B, the four-wheel configuration of the present invention is exactly the same as the conventional system, and a fault signal sending circuit 6 is provided at each relay point, and a fault signal transmission intervening cable 7 is passed to the receiving terminal station. The code error information is sent to the fault signal receiving circuit 10 of. However, as shown in Figure 1A, the processing function of the repeater is
rsion) is different from the conventional method in that it is re-encoded and sent to the next section.

(8,) in FIG. 1A is the original code, and in order to enable error detection in the transmitting terminal station 1, it is parity encoded as shown in (b). As shown by the arrows, one block has a 6-bit structure, and parity pulses are inserted into the shaded areas so that the number of pulses in the block is an odd number (odd parity). In (a), two blocks are shown; in the first block, no parity pulse is inserted because it is a δ pulse, and in the second block, a parity pulse (displayed by diagonal lines) is inserted because it is two pulses. There is.

Next, as shown in (c), after AMI encoding, the signal is transmitted from the beach 2 to the transmission line 3.

In Kasujo's transmission line 3, low-frequency signals are blocked by the transformer and capacitor, so if the code shown in (b) is used as it is, DC fluctuations will occur in the equalized waveform sequence along with fluctuations in the mark rate of the code, making identification difficult. Playback becomes difficult.

Therefore, an AMI code (bipolar code) is used in which the polarity is reversed for each pulse and the spectrum has maximum energy near the pulse repetition frequency.

During transmission on the transmission line 3, if there is no code error, this waveform is transmitted as is, but if an error occurs due to noise on the transmission line 3, for example, as shown by the dotted line in (d),
The repeater detects this error, corrects it, and re-encodes and transmits the next section so as to satisfy the AMI rule. In other words, errors in each section are detected by disturbances in the AMI law, and after registering how many errors exist per second (error rate), one pulse disappears as shown in Figure 1A (d). In this case, as shown in the first A 1ffl (e), the polarity of all the pulses of the subsequent block is inverted, and the entire block is re-encoded so that the polarity is inverted for each pulse.

As a result, in the next section, the code error rate of only that section can be detected.

On the other hand, the code error rate for the entire line can be detected by a parity check at the receiving terminal station 5 by restoring the code to the original code as shown in Figure 1A, so it can be constantly monitored by the receiving circuit 8. .

At each relay point, it is possible to detect code errors in the relay section corresponding to that relay point, so this is registered, and when this exceeds a predetermined limit, a fault signal is sent out from the fault signal sending enclosure 6, which is sent to the intervening cable. 7 through the fault signal receiving circuit 9 or 1
By receiving the signal at 0, it is possible to know in which relay section a failure has occurred. By making the frequency of the fault signal different for each relay section, it is possible to easily identify which relay section the fault signal is in by receiving the fault signal and passing it through a corresponding band-pass filter. It is also possible to add an address to each fault signal.

FIG. 2 and subsequent figures are diagrams showing specific examples of each part of FIG. 1.

FIGS. 2A and 2B are a block diagram of a parity adding circuit and its operation time chart showing an embodiment of the present invention.

The parity addition circuit shown in FIG. 2A allows the first AIffl(
-) is holed into the odd parity code of (b).

The original signal & shown in FIG. 2B (,) is applied from the input terminal 21, phase-adjusted by the delay circuit 22, and then applied to the AND gate 23.

On the other hand, this gate 23 has input terminals 24, !
: Since the clock pulse b shown in FIG. 2B(b) is applied, a waveform C shown in the second BfXJ(Q) appears at the output terminal 25. In addition, in Clock Pal Xb,
The clock is missing only at the end of the block,
A parity pulse will be inserted at this position.

The output waveform 〇 of the gate 23 is directly input to the OR gate 30 and is also applied to the trigger type flip 70 tube 26 .

The trigger type flip-flop 26 is reset each time by the parity clock o (see second BbU(e)) input from the terminal 27. Therefore, the second
Pulse C shown in B IN (0) is a trigger type flip.
Each time it is added to the flop 25, the set/reset is repeated and the signal is reset by the pulse e, so that the code shown in FIG. 2B (d) is obtained.゛The AND of this waveform with the inverted waveform, ie, the parity clock e, is the gate 2
8, the parity pulse f is output terminal 2.
Appears on the 9th.

When the logical sum output pulse C and the parity pulse f are logically summed in the OR gate 30, a pulse train g shown in FIG. 2B (g) appears at the output terminal. Fear,
When jJO is applied to the pulse expansion circuit 31, an NRZ pattern h with parity is obtained at the output terminal 32. The NRZ pattern in FIG. 2B (h) is the first A [ffl (b
), which means that an odd parity code has been created.

FIGS. 3A and 3B are AMIMs showing embodiments of the present invention.
3 is a time chart and a block diagram of a code conversion circuit. FIG.

The NRZ pulse train & with parity obtained by the circuit of FIG. 2A is applied to the input terminal 51 of the AMIM conversion circuit of the third Biffl, and the clock pulse b of FIG. 3A (b) is applied to the terminal 52. As a result, the logical AND of pulse train & and clock pulse b is obtained at gate 53,
A waveform C shown in the third Ald(Q) appears as an output 54. When this waveform C is applied to the trigger type 7 lip/70 tube 55, the output 56 has a waveform d shown in M3AIA(d).
appears. The waveform delayed by the delay circuit 57 is sent to the #1 Ridan gate 59, and the inverted waveform is sent to the AND gate 5.
Add each to 8. Input signals are applied to 58 and 59, respectively. In the AND gate 59, the input signal a and the delayed waveform e are ANDed to obtain the waveform g as an output. Furthermore, in the AND gate 58,
The input signal a and the inverted waveform of the delayed waveform e are ANDed to obtain a waveform f as an output.

By adding these waveforms f and g inverted by the inverter 60 in an adder 61, an AMIM number whose polarity is inverted to positive or negative for each pulse is obtained at the output terminal 62.

In this way, the tAMI code shown in FIG. 1A(c) is created, and this code is sent from the transmitter 2 of the transmitting terminal station l to the transmission line 3.

Next, the operation of the processing circuit in each repeater 4 will be explained.

Figures 4AIJ, 4BIl, and 4C are a time chart and a block diagram of a code error detection circuit and a failure signal transmission circuit, respectively, showing embodiments of the present invention.

As shown by the dotted line in FIG. 4A (&), it is assumed that an AMIM pulse train disappearance error occurs in the middle of the transmission line.

In the code error detection circuit of FIG. 4B, when the AM multiplier signal is applied to the input terminal 71,
are rectified to the positive and negative sides respectively, and each rectified waveform is
a appears at the output cuff 4.75 (Fig. 4A (b) (C
)reference). These waveforms are detected by a rising edge detection circuit 76.
In addition to 77, pulse trains d and e indicating waveform rising are taken out at output cuff 8.79 (see FIG. 4A (d) (θ)). Both pulse trains a and e are added to the AND gate 85 and 86, respectively, and are applied to the input terminals 80 and 81 of the set/reset type 7 lip-flop 62, respectively. The flip-flop δ2 is set every time the pulse shown in FIG. 4A (d) is input, and reset every time the pulse shown in FIG. 4A (e) is input, so that the output 83 has the value shown in FIG.
A waveform f shown in f) is obtained, and an inverted waveform of the waveform is obtained at the output 84. An AND gate 85 takes the AND of the pulse train d and the waveform f, an AND gate 86 takes the AND of the pulse train e and the inverted waveform of the waveform f, and an OR gate 89 takes the OR of both outputs. This gives an error pulse g.

II 4 A When we take the AND of the pulse in Figure (d) and the pulse in Figure (f), we find that pulse d does not match within the positive polarity period of waveform f, so nothing appears on the output 87 and the 1st or 4th A
If we take the AND of the pulse in Figure (8) and the inverted pulse in Figure (f), the second pulse of pulse e is the positive polarity of waveform 7.

Since it matches the seasonal surprise fishing, the output 88 is shown in Figure 4A (
g) appears, which also appears at terminal 90.

This allows error detection.

In the error registration and failure signal sending circuit of FIG. 4C, the error pulse g of FIG. 4A(g) is input to the input terminal 91.
is applied to the counter 9 through the gate 92.
3 to 96 will be automatically registered. That is, terminal 1
After the start signal is input to terminal 02, all flips and 70 blocks 93, 94, 96 are reset, and then when error pulse g is applied to terminal 91, it passes through AND gate 92 and outputs the 1st bit. flip flop 9
Set 3. When the next error pulse g is applied to terminal 91, it resets the 1st bit 7 lip-flop 93 and resets the 2nd bit 7 lip-flop 93.
Set 4. In this way, by increasing the number of flip-70 amplifiers, the number of overflow outputs, that is, the maximum number of error pulses g to be registered, can be arbitrarily set.

When the number of input error pulses g exceeds the set number, the output terminal 97 of the final stage 96 becomes "H" and the terminal 98 becomes "L".
Therefore, the gate 92 is inhibited and error registration is stopped. On the other hand, the AND gate 99 has a Q output 9
7 becomes "H", it opens and allows the signal from the transmitter 99 to pass, and the fault signal is sent from the output terminal 101 to the transmission line. By making the signal frequency of the transmitter 99 different for each repeater, it is possible to determine from which relay point the fault signal is sent.

By applying a start signal to the input terminal 102, all the counters are reset and counting starts.

As described above, the operations of error detection, error registration, and fault signal transmission are automatically performed at each relay point.

Next, the checking operation at the receiving terminal station will be explained.

Figure 5 and Figure 5B are an operation time chart and a block diagram of a code reconversion circuit showing an embodiment of the present invention.

In the receiver 8 of the receiving terminal station 5, the received AMI signal is applied to the hand-over rectifier circuits on the positive side and the negative side, and rectified waveforms a and b are respectively taken out (see Figure ji5A (&) (b)). This is the same operation at each relay point,
FIG. 4A (1)) corresponds to the waveform of (0).

When the rectified waveform outputs a and b in FIGS. 5A (a) and (b) are applied to the input terminals 111 and 112, the OR gate 1
13, the OR output waveform 0 is obtained (Fig. 5A (0
)reference). As a result, N with parity is obtained from the AMI code.
This means that it has been converted into an RZ code. Next, this output waveform C is added to the AND game) 11δ, and the input terminal 1
By adding clock 4 from 14, the sampled waveform .times. is taken out at the gate output (see FIG. 5A (, )). Furthermore, this is connected to the trigger type flip-flop 11.
6, a waveform f shown in FIG. 5A (f) is obtained at the output terminal 117. Next, at the AND gate 119,
The pulse waveform g shown in the fifth person's illustrated biography is obtained by performing the logical product of the inverted waveform of the waveform f and the sample waveform. Furthermore, the AND gate 118 performs an AND operation between the waveform f and the sample waveform .times., thereby obtaining the pulse waveform shown in FIG. 5A (h). Note that since waveform t is slightly delayed by 7 rip and 70 rip f, it matches waveform e just before the waveform falls, and the logical product can be performed, but the sample waveform e that occurs just before the rise does not match. Can not be removes.

The AND output waveforms gr and h are respectively pulse stretcher circuit 1.
23°124, waveform 1. j is terminal 125°1
Obtained on 26th. Here, the pulse stretching circuit 123°12
The time constant of 4 is set to the same time as the period of clock pulse d. When waveform j inverted by inverter 127 and waveform 1 are combined by adder 129, reconverted waveform k is obtained at output terminal 128.

That is, this waveform corresponds to the waveform shown in FIG. 1A (a), and after converting it to the NRZ with parity shown in FIG. 1A (f), by performing a parity check, the first AIiJ It is possible to detect pulse omissions shown by the dotted line in (g).

In the above explanation, an example was given in which an AMI code and a parity code are used together, but if the two types of codes are orthogonal, that is, if the two types of codes are not influenced by each other, then any combination of codes will work. The good news is obvious. For example, a binary AMI code (a code that converts "1" to "11" or "oO〒" and "0" to "oO" or "01") is used on the transmitting side, and this is rolled off on the receiving side. A transmission format that is formed into a duo-binary code by a filter and becomes an AMI code (for example, [0ptiaa! pulse for
mata for fiber optio 61g-
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COM'-24, A4 PP-404-413, 197
If a parity code is used in combination with a parity code (see April 2006), the present invention can be applied to systems such as optical communications that use binary codes on the transmitting side.

Further, although an example has been described in which the fault signal from each relay point is transmitted using the intervening cable 7, it is also possible to multiplex the signal and transmit it.

[Effects of the Invention] As explained above, according to the present invention, two types of error detection codes are used in combination, and one of them is re-encoded at each relay point. In addition to being able to measure the bit error rate of the corresponding section at each point, it is also possible to register the overall bit error rate of the line at the receiving end station, so the location of the fault can be detected in one operation from the bit error rate of each relay point. Therefore, the time and cost for troubleshooting can be significantly reduced.

[Brief explanation of the drawing]

1A and 1B are a time chart and a block diagram of digital transmission code processing showing an embodiment of the present invention, and FIG.
Figure 2B is a block diagram and operation time chart of a parity addition circuit showing an embodiment of the present invention, Figures 3A and 3B are
The figure is a time chart and block diagram of AMI code conversion showing an embodiment of the present invention, and Figures 4A, 4B, and 4c are a code error detection circuit, registration, and failure signal transmission, respectively, showing an embodiment of the present invention. A time chart and a block diagram of the tB circuit, FIGS. 5A and 5B are an operation time chart and a block diagram of a code reconversion circuit showing an embodiment of the present invention. 1: Transmission terminal station, 2: Transmitter, 3: Transmission line, Daytime: Medium equipment, 5: Receiving terminal station, 6: # Harmful signal sending circuit, 7: Intervening cable, 8: Receiver, 9. :to:*Harmful signal receiving circuit. Figure lA Figure'□□ Figure 2A Figure 28 Figure 3A Figure 3B, 58 Figure 4A Figure 9.31J41jO

Claims (1)

[Claims] CL) At the transmitting terminal station of the digital transmission path, the original signal is subjected to two types of error detection encoding and transmitted, and at each relay point, one of the above-mentioned errors of type 2'@1 is detected. After detecting a code error using a detection code, re-encoding is performed only on the error detection code and sending it to the next relay section, and the corresponding relay section is determined by measuring the detected code error rate. notifies the transmitting or receiving end station that a failure has occurred;
A fault position N search method for a digital transmission line, characterized in that a receiving terminal station checks the received signal using the other error detection code to detect code errors in the entire line. e) As the 2m class error detection code 7, a parity code and A M I (AJternILte Mark I
2. A fault location search method for a digital transmission line according to claim 1, characterized in that a digital transmission path fault location search method uses a code (version) code. (3) Parity as the two types of error detection codes. 2. A fault location search method for a digital transmission path according to claim 1, characterized in that a digital transmission line fault location search method uses a binary AMI code and a binary AMI code, and the latter is ternary-formed into an AMI code on the receiving side.