JPS59165960A - Control circuit for switching inductive load - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a control circuit for switching inductive loads, which can be implemented as a monolithically integrated circuit and can be used to drive the electromagnets of the 1j elements in high-speed printing equipment, This invention relates to a control circuit that can be used in a power supply device.

flflJ control circuit for this type of switching &
! A power transistor is included in the final stage to induce power.
It is connected in series with a static load and inserted between two poles of a power supply voltage generator, and is driven alternately from a high voltage/low current state to a low voltage/high current state by a base control signal.

In the first state between the emitter and collector electrodes,
The transistors are virtually open-circuited (turn-off or I-off state) and short-circuited in the second state (conducting or "on" state), thereby each carrying a 64 load. Prevent or allow current to flow through.

The mode of operation of the transistor that closely approximates the operation of an ideal switch is that in the closed state the transistor operates in the saturation region and in the open state it operates in the cut-off region. However, in this case, the final switching frequency of the final stage power transistor is essentially limited by the charge accumulation effect that has already occurred during the conduction phase, K, during the transition from the saturation region to the cut-off region.

As is well known, power transistors have high resistivity and thick collector regions because they are required to withstand high reverse voltages.

A transient phenomenon is observed in this region of the collector; in this first phase, the transistor remains in saturation, and in the "half-saturated" second phase, the collector-emitter voltage begins to rise, but the collector current remains constant. Then, in the last phase, the collector-emitter voltage rises rapidly and the collector current passes through zero.

Especially in the "half-saturated" phase, the transistor dissipates a lot of energy.

Therefore, if the turn-off time can be reduced, it is advantageous both to increase the maximum switching frequency and to improve the efficiency of the control circuit from an energy point of view, thereby improving the operation of the final stage power transistor. Ideal switch operation and reduce time difference.

A known circuit solution to this problem is to provide the base of the final power transistor with low impedance circuit means that rapidly drains the charge carriers stored in the transistor when the transistor is turned off, e.g. , a transistor of suitable dimensions is connected to the base of the final stage transistor, the former functioning in opposite phase to the latter, removing the stored charge and discharging the final stage transistor itself. is obtained by connecting circuit means for accelerating the turn-off of.

This type of circuit solution is e.g.
No. 3-606 and No. 1560854.

However, even though the charge removal transistor is small, it has its own turn-off time, and because this charge removal transistor operates in the opposite phase to the phase of the final stage power transistor, it is necessary to turn off the final stage power transistor again. Involves delays.

And this delay can be ignored when seeking maximum switching speed. On the other hand, when the final stage transistor is already completely turned off, the unnecessary absorption of supply current to keep the charge removal transistor active Even so, it cannot be ignored.

The base control signal is final, by a second transistor coupled to the final stage power transistor.

When transmitted to the power transistor of the stage, the operating speed of the control circuit also depends on the maximum switching speed of this second transistor, which means that the base operates in the saturation region when the transistor we saw earlier is in the conducting state. It depends on the charge stored in this base.

In this case, the speed limitations resulting from the above-mentioned points are considerable, especially when a transistor of the pnp type is provided to drive the power transistor of the last stage (this is related to the integration known to those skilled in the art). In general, npn is used for reasons such as
For control circuits made in monolithic integrated circuits (in the form of 3D), even when the last stage power transistor in the conducting state operates in the active region within the operating range, it is still possible. This is because the turn-off phase of a pnp transistor, which is covered and integrated into an integrated circuit, is longer than that of an npn transistor.

The object of the present invention is to provide a monolithically integrated circuit that has a pnp type transistor for driving the final stage power transistor, has a very high switching speed, and has a very high efficiency. The purpose of this invention is to construct a control circuit for switching an inductive load that suppresses the absorption of unavoidable power supply current.

This object can be achieved with a control circuit for switching inductive loads as defined and characterized in the claims concluding the description here.

The present invention will be described in detail with reference to the drawings by way of examples.
The present invention is not limited to this example.

Corresponding parts are given the same reference numerals throughout each figure.

The switching control circuit shown in FIG. 1 comprises a switching signal source represented by a block labeled SW, which switching signal source SW is connected to control circuit means represented by a block labeled C. ,
Furthermore, this control circuit means C is connected to a pair of bipolar transistors of the pnp type and npn type, denoted T and T2, respectively. The base, emitter and collector of the bipolar transistor are respectively connected to the control circuit means C1.
Positive pole of power supply voltage generator■. 0 and the base of bipolar transistor T2. The collector and emitter of the bipolar transistor T2 are respectively connected to the positive terminal +cc and the negative terminal of the power supply voltage generator via an inductive load represented by a resistor plate and an inductance L connected in series. 0
Connect to.

A diode D is provided in parallel with T and L, and its cathode and anode are connected to the emitter of transistor T2, respectively.
Connect to cc. The base and emitter of transistor T2 are coupled by a resistor P.

Also shown in FIG. 1 is the timed enabling circuit means represented by the block designated TA. This enabling circuit means TA is connected to the control circuit means C by means of a double connection line designated C and a.
is combined with FIG. 1 also includes two pnp type bipolar transistors T and T, and an npn type bipolar transistor T.

The bases of transistors T and T are both control 4 It is connected to the cathode of the circuit means C and the diode D.

The anode of diode D is the positive pole ■. Connect to 0.

The emitters of transistors T8 and T4 are connected to the positive terminal +Vcc. The collector of transistor T3 is transistor T
Connect to the base of the construction. The collector of transistor T4 is connected to the base of transistor T5 and the anode of diode D5.

The emitter of transistor T5 and the diode D50 are connected to the emitter of transistor T2, and the collector of transistor T5 is connected to the base of transistor T2.

FIG. 2 is a circuit diagram of a different embodiment of the invention, which, described in conjunction with FIG. 1, includes two diodes D2 and D7 and pnp bipolar transistors T6 and n
It comprises a pn type bipolar transistor T7.

The base of transistor T6 is connected to the cathode of diode D4 and to the control circuit means.

The emitter and collector of transistor T6 are connected respectively to the positive i+v of the supply voltage and to the anode C- of diode D7. The base of the transistor T7 is also connected to the anode of the diode D7. The cathode of the diode D70 and the emitter of the transistor T7 are the negative terminal of the power supply voltage -■. Connect to C. The collector of transistor T7 is connected to the cathode of diode D20. The anode of diode D2 is connected to the base of transistor T2.

In addition, FIG. 2 also shows specific circuit configurations of blocks C and TA of FIG. 1. The control circuit means, represented by block C in FIG. 1, consists of three npn bipolar transistors T8. T9 and T engineering. Equipped with.

The bases of transistors T8 and T are connected to switching signal source SW and to the anode of diode D9. The cathode of diode D9 is negative electrode -■. Connect to 0.

The emitter of transistor T8 is connected to the negative electrode -VCC,
The collector of the transistor T8 is connected to the base of the transistor T0 and the cathode of the diode D□. The anode of diode D1 is a positive pole ■. .

Connect to. The collector of transistor T9 is transistor T□. It is connected to the base of the diode D, and also connected to the positive electrode +cc through the constant current source A1, and further connected to the anode of the diode D. The emitters of transistors T90 and Tlo and the cathode of diode D100 are connected to the negative electrode -cc. The collector of transistor T0° is connected to transistor T3. T, , is connected to the base of T6 and to the cathode of diode D4.

Timed enabler eclipse, b”, Z
pnp type bipolar transistor T, and T.

Also include an npn type bipolar transistor T□3. The base of transistor T0□ is connected to the cathode of diode D2 and the collector of transistor T8.

The emitter and collector of the transistor are positive terminals, respectively.
■Connected to oo and the base of transistor T□2. Base q of transistor TI2.

Eode D Eng. Connect to the cathode of Diode D
The anode of is a positive pole ■. Connect to 0. The collector of the transformer 2 transistor T1□ is also connected to the negative electrode -CC via the constant current source A0□.

The emitter of the transistor T□2 is the positive pole V. 0, and its collector is connected to the base of transistor T18 and the anode of diode D13. The cathode of the diode D is the negative electrode -V. Connect to 0. transistor engineer,
The emitter and collector of are -■ and transistor T, respectively.
, and the collector of C.

The operation of the circuit shown in FIG. 1 will be explained below.

Diode D4 forms a first current mirror circuit in combination with transistor T8 and transistors T6. In combination with the combination of diode D6 and transistor T5, the second
form a more complex current mirror circuit. Diode D
, and the control circuit means C is the common input terminal of the two current mirror circuits. The connection points between the collector of the transistor T8 and the base of the transistor T□ and the connection point between the collector of the transistor T5 and the base of the transistor T2 are separate output terminals of two current mirror circuits. The input current is mirrored to the output with a constant current transfer factor.

The control circuit means C simultaneously activates the first and second current mirror circuits, and then turns off the transistor T1 and thus turns off the transistor T2 in response to a constant switching signal generated by the switching signal source SW. Control turn-off.

In this way, the charge removal current from the base of transistor T□ is determined, on the one hand the charge absorption current from the collector of transistor T1 in the turn-off phase, and on the other hand the charge removal current from the base of transistor T2. As previously mentioned, these currents are proportional to the currents imposed by the control circuit.

The timed enabling circuit means TA comprises:
A connection line to the control circuit means C detects the turn-off control of the transistors T and T2, and the same control circuit means C activates the two current mirror circuits for a certain period of time.

If a new switching signal arrives from the switching signal source SW during this period, the control circuit means C causes the transistors T and T2 to turn on again, the current mirror circuit to deactivate, and the timed Controls the return of the bling circuit means TA to its initial state.

Otherwise, at the end of said period, the timed enabling circuit means TA instructs the control circuit means C by means of a connection a to turn on the transistors T and T.
The current mirror circuit is inactivated without changing the state of 2.

The operation of the control circuit for switching according to the invention will be better understood by explaining the operation of the circuit shown in FIG. 2 in particular. In contrast to the case of FIG. diode D2, transistor T, diode D, transistor F and 6)
71 and a diode D2 as well as an eighth current mirror circuit formed by the respective connecting lines. The input terminal of this third current mirror circuit is common to the first and second current mirror circuits, and its output terminal is separate from the output terminals of the other two current mirror circuits, but it is also a transistor. It is connected to the base of transistor T2 and allows charge to be more efficiently removed from this transistor T2 during the turn-off phase.

The eighth current mirror circuit is activated simultaneously with the first and second current mirror circuits. Initially, the collector-emitter voltage of transistor T7 is higher than the collector-emitter voltage of transistor T5 (which is equal to the base-emitter voltage of transistor T2 in the conduction state >fFF).

This is because the emitter of the transistor T7 is connected to the negative electrode -CC. The collector current of transistor T7 is therefore greater than the collector current of transistor T5, so adding a third current mirror circuit allows transistor T2 to turn off quickly.

Thus, a cut-off of transistor T2 occurs already when the collector current of transistor T2 has not decreased significantly.

Since the emitter of the final stage transistor T2 is connected to an inductive load, when turn-off occurs, a back electromotive force is induced in the inductive load, reducing the potential of the emitter of the trunk transistor T2 below the reference level of 1 CC. lower to The base potential of transistor T2 also falls, and transistor T7 becomes of reverse polarity and ceases its charge removal activity. - To avoid recirculation of the collector current of transistor T in such a polarity state, a diode D2 is inserted between the collector of transistor T7 and the base of transistor T2.

However, transistor T5 has its emitter connected to the emitter of transistor T2 and is therefore at the same potential as the emitter of transistor T2 in all conditions and is kept in forward conduction, so that in the turn-off phase transistor T0 absorbs the collector current of the transistor T2 and prevents the collector current of the transistor T2 from turning on the transistor T2 again.

When transistor T0 is also cut off, the current mirror circuit is deactivated. This is because the operation of the current mirror circuit is no longer necessary.

The operation of the enabling circuit means in conjunction with the control circuit means will now be described in detail.

? /7 period condition is transistor T1. An image is formed when T2 and TR are in a conductive state.

A switching signal generated by switching signal source SW to control the turn-off of the final stage transistor cuts off transistors T8 and T (simultaneously).

The cutoff of transistor T8 is the cutoff of transistors T and T.
The cut-off of the trunk T is given by the current source A8, and a constant current flows into the base of the transistor, which is completely absorbed by the transistor T when it is conducting. Thus, the transistor T□ was initially in the cutoff state. immediately conducts. Transistor T1o activates the first mentioned @1 and the second current mirror circuit and begins to remove the load from transistors T and T2 with transistors T, T and T7 still in conduction.

Transistor T 2 is driven to switch by transistor T8, similar to transistor T□. The transistor T and the current source A□□1 are such that the current source A gives the transistor T1 a collector current that is smaller than the current imposed by the polarity state of the transistor T□, and the collector current of the transistor T0 is in the grain layer. becomes a value that keeps transistor T2 conductive. In this state, the transistor T is saturated and the transistors T12 and T□8 are cut off.

When transistor T is less than the threshold current that makes transistor T2 conductive, the collector current of transistor T1□ tends to a value less than the current provided by current source A, and transistor T0□ is no longer saturated. At this point, transistors T12 and T18 become conductive and no longer have an active turn-off function, and transistors T1 and T2 become conductive again without delay.

However, if the signal to turn on transistors T2 and T2 again reaches the control circuit means before the activation period thus defined has expired, transistors T8 and T9 immediately become conductive again. As a result, transistor T□□ also becomes conductive, transistors T and T18 are cut off, transistor T again absorbs the entire current supplied from 〇 to the current source, and transistor T□.

turn off.

Thus, at the same time as the final stage transistor is turned on, the charge removal means is deactivated and the timed enabling circuit means is returned to its initial state.

The control circuit according to the invention is particularly suitable for integration in a monolithic semiconductor block using known integration techniques.

Although only one embodiment of the invention has been described above, it is clear that many variations can be envisaged without departing from the scope of the invention.

For example, the current mirror circuit included in FIGS. 1 and 2 may be replaced with a more complex current mirror circuit by appropriate circuit modifications obvious to those skilled in the art; It is possible to have a circuit configuration suitable for creating an insensitive circuit. In addition, suitable resistors are provided in place of diodes D5 and D7 to increment the current gain of transistors T5 and T7 and shorten their turn-off time. And it is possible to compensate for the decrease in accuracy of the value of the collector' peeking current of T7.

In a different embodiment of the invention, the enabling circuit means can be formed by a monostable circuit with a strictly constant enabling time that can be arbitrarily determined.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a switching control circuit according to the present invention (
FIG. 2 is a circuit diagram of another embodiment of the present invention. (Fig. 1) SW...Switching signal source, C...Control circuit means, T□, T8. T, . . . pnp type bipolar transistor, T2. T5...npn type bipolar transistor, 10cc...positive pole of power supply voltage, 'cc...negative pole of power supply voltage (top) and L...inductive load, D,, D41D5...
Diode, ■YoTA...Timed enabling circuit means, a, c...Connection line, (Fig. 2) D~D18...Diode, T1 + T3 + T4 r T6r Tt , r
Tt 2 ''・pnp type bipolar transistor, T2 + T5, T71T81T91'T1.,'
r, B ・” NPN type bipolar transistor, +■oo・2・Positive pole of power supply voltage, 'cc... Negative pole of power supply voltage, A1. A1□... Constant current source.

Claims (1)

[Claims]L Control circuit means (C) which can be monolithically integrated and are connected to a switching signal source (SW) which generates an electrical pulse determined by the signal itself and which has a rising edge and a falling edge; , each of which has a first terminal, a second terminal,
A first transistor (T type) having a control terminal and a second transistor
a transistor (T2), and one of the first and second terminals of the first transistor (T1) is connected to one of the two poles (+■oo. -Voo) of the power supply voltage generator. , the other terminal and the control terminal are respectively connected to the control terminal of the second transistor (T2) and to the control circuit means (C), and the first transistor is rendered conductive by a pulse generated by the circuit means. , the second transistor (T2) connected in series with the inductive load (RL, L) through the first terminal and the second terminal is connected to the two poles (+■CC'' of the power supply voltage generator). a control circuit for switching an inductive load inserted between a first transistor (To), the control circuit comprising charge removal circuit means;
and at least one control terminal of the second transistor (T2) and coupled to control circuit means (C), which control circuit means (C) cause the first transistor (T□) to conduct. a timed enabling circuit means (C), also coupled to the control circuit means (C), a control circuit for controlling the activation thereof in response to the falling edge of the pulse and for further switching the inductive load; TA), the control circuit means (C) being enabled by the enabling circuit means to keep the charge removal circuit means active for a period of time, which period extends from the falling edge of each pulse to the rising edge of the next pulse. 1. A control circuit for switching an inductive load, characterized in that the control circuit is configured to make the switching time equal to the time elapsed. 2. The first transistor (T) and the second transistor (T2) have opposite first and second types of conductivity, respectively, and the first terminal of the first transistor and the second and the first pole (+Voo) of the power supply voltage generator, respectively.
and the control terminal of the second transistor (T2), and connect the first terminal and the second terminal of the second transistor to the second terminal of the power supply voltage generator via inductive loads (RL, L), respectively. 2. A control circuit for switching an inductive load according to claim 1, wherein the control circuit is connected to a first pole (-Voo) and a first pole (10V.0). & an eighth transistor (T8), wherein the charge removal circuit means each have a first terminal, a second terminal and a control terminal;
, a fourth transistor (T, ), and a bamboo transistor (T5), and the third and fourth transistors are connected to the first transistor.
, the fifth transistor is the second conductivity type, and the third transistor (T8) and the fourth transistor (T8) are the conductivity type.
Both control terminals of T, ) are connected to the first diode (D4).
and the anode of the first diode (D4) and the first terminals of the eighth transistor (T8) and the fourth transistor (T,) to the supply voltage generator. The second terminal of the third transistor (T8) is connected to the control terminal of the first transistor (T□), and the fourth transistor (T, ) is connected to the control terminal of the fifth transistor (T5), and the first terminal of this fifth transistor (T5) is connected to the first resistive element (D5).
) and to the first terminal of the second transistor (T2), and connect the second terminal of the fifth transistor (T5) to the second terminal of the second transistor (T2). 3. A control circuit for switching an inductive load according to claim 2, wherein the control circuit is connected to a control terminal. The charge removal circuit means includes a sixth transistor (T6) each having a first conductivity type and a second conductivity type, each having a first terminal, a second terminal, and a control terminal; a seventh transistor (T7), the control terminal of the sixth transistor (T6) being connected to the cathode of the first diode (D,) and to the control circuit means; The first terminal and the second terminal of the power supply voltage generator are connected to the first pole (10) of the power supply voltage generator, respectively, and
A seventh transistor (T7) is connected to the control terminal of C, and the first and second terminals of the seventh transistor (T7) are respectively connected to the second pole (-Voo) of the power supply voltage generator. connected to the second diode (D2),
The control terminal of the seventh transistor (T7) is also connected to the second pole (-Voo) of the power supply voltage generator via the second resistive element (D7), and the control terminal of the seventh transistor (T7) is 9. A control circuit for switching an inductive load according to claim 8, characterized in that the anode is connected to the control terminal of the second transistor (T2). A control circuit for switching an inductive load according to any one of Items 3 and 4 of the scope of the invention, characterized in that the resistive element is a resistor. 1. A control circuit for switching an inductive load according to any one of claims 8 and 4, characterized in that the resistive element is a diode. 7. The control circuit means (C) comprises an eighth transistor (T8) having a second conductivity type and each having a first terminal, a second terminal and a control terminal; Transistor (
) and a tenth transistor (Tlo), an eighth transistor (T8) and a ninth transistor (T
, ) are connected to the control terminals of these eighth and ninth transistors.
A switching signal source for controlling the transistor is connected to the anode of the third diode (D, ), and the cathode of the eighth diode (D9) is connected to the second pole (-Voo) of the power supply voltage generator. and the eighth transistor (T8)
The first and second terminals of the power supply voltage generator are respectively connected to the second pole (-Voo) and both the control terminal of the first transistor (T1) and the cathode of the fourth diode (Dl). , the anode of the fourth diode (D) is connected to the first pole (10V...) of the power supply voltage generator, and the second terminal of the ninth transistor (T,) is connected to the first O control terminal of the transistor (T) and the first constant current source (80)
is connected to the first pole (10V.0) of the power supply voltage generator and the anode of the fifth diode (Dlo) through the ninth
transistor (T, ) and the tenth transistor (T
□. ) and the fifth diode (Dlo)
The cathode of is connected to the second pole (-Voo) of the power supply voltage generator, and the second terminal of the tenth transistor (Tlo) is connected to the eighth transistor (T8) and the fourth transistor (Tlo).
T, ) and a control terminal of a sixth transistor (T6);
and a timed enable song circuit means (TA) connected to the cathode of the first diode (D4), respectively connected to the first terminal, the second terminal and the control terminal. an eleventh transistor (T
,,), the twelfth transistor (T-engineering,), and the eighteenth transistor
a transistor (T), the eleventh transistor and the twelfth transistor have a first conductivity type, the eighteenth transistor has a second conductivity type, and the eleventh transistor (T The control terminal of the 11th transistor (T) is connected to the second terminal of the eighth transistor (T8) and the cathode of the fourth diode (D).
The first terminal and the second terminal of the power supply voltage generator are connected to the first pole (+■co) of the power supply voltage generator, the control terminal of the twelfth transistor (T), and the second constant current source ( The control terminal of the twelfth transistor C (T, 2) is connected to the second pole (-V) of the power supply voltage generator through the sixth diode (D, , ).
The anode of the sixth diode (D□2) is connected to the first pole (+■oo) of the power supply voltage generator, and the The first terminal is connected to the first pole (+■oo) of the power supply voltage generator, and the second terminal is connected to the control terminal of the 18th transistor (T□8). # terminal and the seventh diode (D1
8), and this seventh diode (D
The cathode of □8) and the first terminal of the 18th transistor (T18) are connected to the second pole of the power supply voltage generator, and the second terminal of the 13th transistor (T) is connected to the 9th Control circuit for switching an inductive load according to any one of claims 8.4.5 and 6, characterized in that it is connected to the second terminal of a transistor (T,) of . & Claim 7, characterized in that the physical characteristics and electrical characteristics of the eleventh transistor (T, □) are equal to those of the first transistor (To). Control circuit for switching the described inductive load. 9. A patent claim in which the transistor included in the circuit is an Ibora transistor, and the first terminal, control terminal, and second terminal of the Ibora transistor are an emitter, a pace, and a collector, respectively. A control circuit for switching an inductive load as described in the range before or after each term. 10. A control circuit for switching an inductive load according to any one of the preceding claims, characterized in that the entire circuit is integrated into a monolithic semiconductor block.