JPS59165567A - Adaptive binary coding device - Google Patents

Abstract

PURPOSE:To ensure the binary coding with stable picture quality at both a binary picture region and a halftone picture region by dividing both regions in block units. CONSTITUTION:The analog picture supplied through a terminal 1 is converted into a digital picture signal of 6-bit by an A/D converter 2 and supplied to a feature extracting circuits 3, a binary coding circuit 4 and a dot converting circuit 5 respectively together with the clock supplied from a terminal 9. The circuit 3 divides the digital picture signals for each block by counting the clocks and distinguished whether the input picture signal is equal to a binary picture or a halftone picture. This distinguished picture signal is supplied to a feature quantity deciding circuit 6. The digital picture signal is binary coded by the circuit 4 and then converted into dots by the circuit 5 in the form of a halftone picture for binary coding. A multiplexer 7 selects the binary signals of circuits 4 and 5 for each block on the basis of the result of the circuit 6. These selected signals are delivered through a terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for converting halftone image signals such as binary images and photographs into two
This invention relates to an adaptive binarization device that performs digitization.

Conventionally, there was no adaptive binarization device for binarizing this kind of mixed image, so simple binarization was performed by turning on/off a switch or the like, or halftone dot conversion (dithering) was performed. simple 2
In the case of digitization, halftone image portions are also simply binarized, which has the disadvantage that sufficient image quality cannot be obtained in photographs and the like.

On the other hand, when halftone conversion (dithering) is performed, characters and halftone images are converted into halftone dots. In the case of point photographs, there is a drawback that moiré and the like appear.

An object of the present invention is to improve the above-mentioned drawbacks of the conventional method. The object of the present invention is to provide an adaptive binarization method that provides stable image quality binarization.

According to the present invention, in a binarization device that binarizes an image signal including a binary image and a halftone image, there is provided a means for A/D converting an input image signal to obtain a multi-value digital image signal; means for extracting a characteristic amount of a halftone image using a digital image signal; means for separating the digital image signal into a binary image area and a halftone image area in units of blocks according to the feature amount; Adaptive binarization characterized by comprising a means for simply binarizing the frame area of the binary image, and a means for binarizing the halftone image 1 area by halftone dot conversion. A device is obtained.

Next, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram representing one embodiment of the present invention.

The multiple analog image signals input to the terminal 1 are converted into 6-bit digital image signals by the N0 converter 2, and together with the clock input to the terminal 9, the signals are sent to a feature extraction circuit 3, a binarization circuit 4, and a halftone dot conversion circuit. 5 is input. The feature extraction circuit 3 divides the digital image signal into blocks by counting clocks, extracts features for distinguishing whether the input image signal is a binary image or a halftone image, and performs feature amount determination. Input to circuit 6. The digital image signal is binarized as a normal binary image in the binarization circuit 4, halftone-ized as a halftone image in the halftone conversion circuit 5, and then binarized by the multiplexer 7. is input. In the multiplexer 7, the binary signal from the binarization circuit 4 or the binary signal from the halftone dot formation circuit 5 is selected for each block based on the result of the feature determination circuit 6, and is outputted from the terminal 8 as a binary image signal. Ru.

FIGS. 2(G) and 2(B) are diagrams for explaining the effect when a density difference histogram is used as the feature extraction circuit 3 used in the present invention. When we calculate the density difference histogram of a binary image signal, we find that in the case of a binary image signal, the density difference is large only at the edges, and the density difference is small at the background and the center of the characters, as shown in Figure 2 (3). As shown in the density difference histogram, a two-peaked distribution with peaks at both large and small density differences is obtained. On the other hand, when calculating the density difference histogram of the halftone image signal, the second
As shown in the figure, all concentration differences have a one-peak distribution with an average value.If you calculate the degree difference histogram and determine whether it is a -mountain shape or a two-mountain shape, , it is possible to separate whether the image is a binary image or a halftone image.

FIG. 3 is an example of a feature quantity extraction circuit when the density difference histogram explained in FIG. 2 is used as a feature quantity. In the figure, 0 is first written to the contents of the memory (random access memory) 13 at the beginning tb of the block. Next, the digital image signals input to the A/D converter 2 are delayed by one sample in the register 10, and then input to the adder 12. On the other hand, the digital image signal inverted by the inverter 11 is input to another terminal of the adder 12 and added, thereby determining the density difference with the digital image signal of one pixel before, and giving it as an address in the memory 13. The contents of the given address are read out in the memory 13, 1 is added in the adder 14, and the contents are temporarily stored in the register 15. Then, the density difference histogram is obtained by writing to the same address in the memory 13. The obtained density difference histogram 5-Durham is read out at the end of the block and inputted to the feature quantity determining circuit 6. Here, the feature value determination circuit 6 includes a microprocessor, ROM (read only memory), R
AM (Random Access Memory).

It is a microcomputer configured with an I10 port, etc., and uses the density difference histogram of the feature quantity extraction circuit 5.
It determines whether it is a single peak type or a double peak type, and outputs a selection signal according to the result.

The feature amount extraction circuit described above is just an example, and there is also an equal product that determines whether the image signal is a binary image signal or a halftone image by determining the frequency components included in the image signal. Various methods are possible.

FIG. 4 shows an example of the halftone dotting circuit 5 used in the present invention. The address generator 20 generates an address for generating a halftone dot threshold as shown in FIG. 5 in accordance with a clock added to the digital image signal. R.O.
M21 generates a threshold value for binarizing the current digital image signal according to the address of the address generator 20, and performs binarization by comparing it with the input digital image signal in the comparator 22. A halftone image is obtained. The binarization circuit 4 can be constructed by fixing one input of the comparator 22 in the halftone conversion circuit 5.

Although the present invention has been described above according to embodiments, these are merely illustrative and do not have a restrictive meaning. Although halftone dots are used to express halftone images, it goes without saying that dithering or proprietary methods of outputting as multivalued images may also be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2(3) and (B) are diagrams showing the effect of using a density difference histogram as a feature quantity used in the present invention, and FIG. FIG. 4 is a block diagram showing an example of a feature amount extraction circuit, FIG. 4 is a block diagram showing an example of a halftone dot formation circuit, and FIG. 5 is a diagram showing an example of threshold values for halftone dots. In the figure, reference number 1 is an input terminal, and 2 is an A/D terminal.
Converter, 3 is a feature extraction circuit, 4 is a binarization circuit, 5 is a halftoning circuit, 6 is a feature quantity determination circuit, 7 is a multiplexer, 8
is an output terminal, 10 is a register, 11 is an inverter, 12
is an adder, 13 is a memory, 14 is an adder, 15 is a register, 20 is an address generator, 21 is a ROM (read only memory), and 22 is a comparator. 1'2 Figure JP-A-59-165567 (4)

Claims (1)

[Claims] In a binarization device that binarizes an image signal in which a binary image (character or halftone image) and a halftone image are mixed, means for A/D converting an input image signal and outputting a multivalued digital image signal; , means for extracting a characteristic amount of a halftone image using the digital image signal, means for separating the digital image signal into a binary image region and a multivalued image region in units of blocks according to the feature amount, and the separating method. was done 2
Adaptation 2 characterized in that the value image area portion is comprised of a means for simple binarization, and the halftone image area portion is comprised of a means for binarizing the halftone image area by halftone dotting (or dithering). Value device.