JPH0526389B2 - - Google Patents

Info

Publication number
JPH0526389B2
JPH0526389B2 JP58016415A JP1641583A JPH0526389B2 JP H0526389 B2 JPH0526389 B2 JP H0526389B2 JP 58016415 A JP58016415 A JP 58016415A JP 1641583 A JP1641583 A JP 1641583A JP H0526389 B2 JPH0526389 B2 JP H0526389B2
Authority
JP
Japan
Prior art keywords
pixel
threshold
circuit
value
image signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58016415A
Other languages
Japanese (ja)
Other versions
JPS59141873A (en
Inventor
Hironori Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58016415A priority Critical patent/JPS59141873A/en
Publication of JPS59141873A publication Critical patent/JPS59141873A/en
Publication of JPH0526389B2 publication Critical patent/JPH0526389B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits
    • H04N1/405Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels

Description

【発明の詳細な説明】 この発明は画像信号を適応的に擬似中間調化す
る回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that adaptively converts image signals into pseudo-halftones.

連続階調を凝似的に表現する手段として網点化
処理は広く用いられている。連続階調から成り立
つ普通の写真等においては網点化処理を行うと階
調再現は十分で偽輪郭があらわれることもなく自
然な感じを与える。ところがもともと2値の画像
信号である文字等の線画に対して網点化すると網
点の中央部においては線が太くなり、また周辺部
では線が切れてしまうという様に解像度が低下し
小さな文字ではその判読さえも困難になる。逆に
もともと2値の画像信号である文字等の線画に対
してその輪郭をを保存し解像度よく再現を行うた
めに固定の閾値で2値化を行うと、写真等連続階
調を含む画像信号の部分においては階調が表現さ
れず偽輪郭があらわれるといつた不都合が生じ
る。
Halftone processing is widely used as a means of expressing continuous gradation in a concise manner. For ordinary photographs that consist of continuous gradation, halftone processing provides sufficient gradation reproduction and gives a natural feel without the appearance of false contours. However, when line drawings such as characters, which are originally binary image signals, are converted into halftone dots, the lines become thick in the center of the halftone dots, and the lines are cut off in the periphery, resulting in a decrease in resolution and small characters. Even that makes it difficult to decipher. On the other hand, if line drawings such as characters, which are originally binary image signals, are binarized using a fixed threshold in order to preserve their contours and reproduce them with good resolution, image signals containing continuous gradation, such as photographs, will be processed. In this area, gradations are not expressed and false contours appear.

本発明は上記従来技術では困難であつた解像度
と階調表現能力の両者を共に実現する適応擬似中
間調を行う回路を提供することにある。
An object of the present invention is to provide a circuit that performs adaptive pseudo-halftone that achieves both resolution and gradation expression ability, which have been difficult to achieve with the above-mentioned prior art.

本発明によれば、2値及び連続階調を含む画像
信号を適応的に擬似中間調化する回路であつて、 (a) 入力画像信号の階調連続性の度合を示す、注
目画素の前ラインの画素と注目画素との差分の
絶対値と、注目画素の前画素と注目画素との差
分の絶対値との合計値を計算する計算手段と、 (b) 前記計算手段の計算値を基に、前記計算値が
大きい場合には固定の閾値に近づくように、前
記計算値が小さい場合には所定の順序で配列さ
れた複数個の閾値からなる周期性閾値に近づく
ように前記入力画像信号に対する閾値を画素毎
に出力する閾値決定手段と、 (c) 前記入力画像信号を前記閾値決定手段の出力
により2値化する2値化手段と を備えたことを特徴とする適応凝似中間調化回路
が得られる。
According to the present invention, there is provided a circuit that adaptively converts an image signal including binary and continuous gradations into pseudo-halftones, the circuit comprising: a calculation means for calculating the sum of the absolute value of the difference between the pixel of the line and the pixel of interest and the absolute value of the difference between the pixel preceding the pixel of interest and the pixel of interest; (b) based on the calculated value of the calculation means; The input image signal is adjusted such that when the calculated value is large, the input image signal approaches a fixed threshold, and when the calculated value is small, the input image signal approaches a periodic threshold consisting of a plurality of thresholds arranged in a predetermined order. (c) binarization means to binarize the input image signal using the output of the threshold value determination means. A circuit is obtained.

以下に図面を参照して詳細に説明する。 A detailed description will be given below with reference to the drawings.

第1図は本発明の一実施例示すブロツク図であ
り、連続階調であるかどうかの伴定基準としてコ
ントラストを用いた例である。センサ、アナログ
−デイジタル変換器等を備えた画像入力装置11
から得られるデイジタル化された画像データはコ
ントラスト計算回路12において注目している画
素のコントラストが計算される。そして、閾値決
定回路14は前記コントラスト値をもとにしてあ
らかじめ与えられている網点化閾値を変更し2値
化回路15に出力する。画像入力装置11から得
られる画像信と変更された網点化閾値を2値化回
路15で比較し2値画像信号を出力する。
FIG. 1 is a block diagram showing one embodiment of the present invention, and is an example in which contrast is used as a criterion for determining whether or not continuous gradation is used. Image input device 11 equipped with a sensor, analog-digital converter, etc.
A contrast calculation circuit 12 calculates the contrast of the pixel of interest from the digitized image data obtained from the image data. Then, the threshold determining circuit 14 changes the halftone threshold given in advance based on the contrast value and outputs it to the binarizing circuit 15. A binarization circuit 15 compares the image signal obtained from the image input device 11 with the changed halftone threshold value, and outputs a binary image signal.

第2図にコントラスト計算回路12を示す。端
子21から入力された画像信号はラインメモリ2
2で1ライン分の遅延をうけ減算器23−Aに入
力される。減算器23−Aは現ラインの画素と直
前のラインの画素との差の絶対値を計算する。
FIG. 2 shows the contrast calculation circuit 12. The image signal input from terminal 21 is sent to line memory 2.
2, the signal is delayed by one line and is input to the subtracter 23-A. The subtracter 23-A calculates the absolute value of the difference between the pixels of the current line and the pixels of the immediately previous line.

以上のコントラスト値はライン間におけるコン
トラスト値を計算するものであるが、ラインメモ
リ22のかわりの1画素メモリ24と減算器23
Bを用いてライン内のコントラスト値計算も行
う。加算器25はライン間、ライン内のコントラ
スト値、すなわち、差分値の絶対値の和を端子2
2に出力する。
The above contrast value is used to calculate the contrast value between lines, but the 1-pixel memory 24 instead of the line memory 22 and the subtractor 23 are used to calculate the contrast value between lines.
B is also used to calculate the contrast value within the line. The adder 25 outputs the sum of the contrast values between lines and within the lines, that is, the absolute values of the difference values, to the terminal 2.
Output to 2.

本実施例においては文字等の線画の部分すなわ
ちコントラストの高い所では急峻なエツジが存在
するということを用いてコントラストの高い部分
を判別している。この他にも画像信号の空間周波
数を利用して連続階調であるかどうかを判別する
こともできる。
In this embodiment, high contrast parts are determined based on the fact that steep edges exist in line drawing parts such as characters, that is, parts with high contrast. In addition to this, it is also possible to determine whether the image signal is continuous tone or not using the spatial frequency of the image signal.

第3図に閾値決定回路14のブロツク図を示
す。端子31には図示はしていないクロツク発生
器から画素毎のクロツクが供給され、画素カウン
タ38Aを駆動する。端子32には同様に図示し
ていないクロツク発生器からライン毎のクロツク
が供給されラインカウンタ38Bを駆動する。こ
の2つのカウンタの値をアドレスとして閾値テー
ブルROM(読出し専用メモリ)35は第4図に
一例を示した網点化閾値Tを出力する。但し、こ
こでは閾値TをそのままROM35に書いておく
のではなく、線画の部分を2値化するため固定の
閾値TlをTから差引いた値(T−Tl)を書いてお
く。次に割算器36において端子22から入力さ
れるコントラスト値を正規化した値NでROM3
5の出力T−Tlを割算し(T−Tl)/Nを得る。
但しN≧1としておく。次に加算器37において
Tlを加え端子33に(T−Tl)/N+Tlを出力す
る。これが変更された網点化閾値となる。
FIG. 3 shows a block diagram of the threshold determination circuit 14. A clock for each pixel is supplied to the terminal 31 from a clock generator (not shown) to drive the pixel counter 38A. Similarly, a clock for each line is supplied to the terminal 32 from a clock generator (not shown) to drive a line counter 38B. Using the values of these two counters as addresses, the threshold table ROM (read-only memory) 35 outputs the halftone threshold T, an example of which is shown in FIG. However, here, instead of writing the threshold value T as it is in the ROM 35, in order to binarize the line drawing portion, a value (T- Tl ) obtained by subtracting a fixed threshold value Tl from T is written. Next, in the divider 36, the contrast value inputted from the terminal 22 is normalized, and the value N is used to divide the ROM 3.
Divide the output T- Tl of 5 to obtain (T- Tl )/N.
However, N≧1. Next, in the adder 37
Add T l and output (T-T l )/N+T l to terminal 33. This becomes the changed halftone threshold.

線画のエツジ部分においてNが大きくなると
(T−Tl)/Nの値が小さくなり網点のどの位置
においても閾値はTlに近づいてくるので固定の閾
値で2値化したような画像が得られる。反対に写
真などのようにエツジが少なくなだらかに階調が
変化する画像が入力された時にはNが小さくなり
Tlの影響が小さくなつて閾値はTで決定される。
このTは網点内の位置によつて第4図に示したよ
うに変化するので普通の網点画像が得られること
になる。
As N increases at the edge of the line drawing, the value of (T - T l )/N decreases, and the threshold approaches T l at any position of the halftone dot, resulting in an image that looks like it has been binarized with a fixed threshold. can get. On the other hand, when an image with few edges and gradual gradation changes, such as a photograph, is input, N becomes small.
The influence of T l becomes small and the threshold value is determined by T.
Since this T changes as shown in FIG. 4 depending on the position within the halftone dot, a normal halftone dot image is obtained.

第5図は2値化回路15を示すもので、閾値決
定回路14において決定された閾値が端子43か
ら入力され、端子51に入力される画像入力装置
11からの画像信号と比較器53で比較しその結
果を端子16に出力する。
FIG. 5 shows the binarization circuit 15, in which the threshold determined by the threshold determining circuit 14 is inputted from the terminal 43 and compared with the image signal from the image input device 11 inputted to the terminal 51 by the comparator 53. The result is output to terminal 16.

以上の述べた様に本発明の適応擬似中間調化回
路は、線画等のコントラストの高い部分では固定
に近い閾値で2値化が行なわれるので解像度が保
存される。またなだらかに階調が変化する部分で
は網点用の閾値で2値化されるので階調表現力が
保存される。従つて文字等の部分でもボケがな
く、写真の部分でも偽輪郭のあらわれることのな
い画像が得られるという効果を有する。
As described above, in the adaptive pseudo-halftoning circuit of the present invention, resolution is preserved because binarization is performed using a nearly fixed threshold in high-contrast areas such as line drawings. In addition, since the portion where the gradation changes gradually is binarized using the halftone threshold, the gradation expressiveness is preserved. Therefore, it is possible to obtain an image in which there is no blurring even in parts such as characters, and there is no false contour appearing in parts such as photographs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロツク図、
第2図はコントラスト計算回路のブロツク図、第
3図は閾値決定回路のブロツク図、第4図は網点
化用閾値マトリクスを示す図、第5図は2値化回
路のブロツク図である。 図において、11……画像入力装置、12……
コントラスト計算回路、14……閾値決定回路、
15……2値化回路、22……ラインメモリ、2
3A……減算器、23B……減算器、24……画
素メモリ、25……加算器、35……ROM(読
出し専用メモリ)、36……割算器、37……加
算器、38A……カウンタ、38B……カウン
タ、53……比較器である。
FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram of the contrast calculation circuit, FIG. 3 is a block diagram of the threshold value determination circuit, FIG. 4 is a diagram showing a threshold value matrix for halftone dot formation, and FIG. 5 is a block diagram of the binarization circuit. In the figure, 11... image input device, 12...
Contrast calculation circuit, 14...threshold value determination circuit,
15...Binarization circuit, 22...Line memory, 2
3A...Subtractor, 23B...Subtractor, 24...Pixel memory, 25...Adder, 35...ROM (read-only memory), 36...Divider, 37...Adder, 38A... Counter, 38B... Counter, 53... Comparator.

Claims (1)

【特許請求の範囲】 1 2値及び連続階調を含む画像信号を適応的に
疑似中間調化する回路であつて、 (a) 入力画像信号の階調連続性の度合を示す、注
目画素の前ラインの画素と注目画素との差分の
絶対値と、注目画素の前画素と注目画素との差
分の絶対値との合計値を計算する計算手段と、 (b) 前記計算手段の計算値を基に、前記計算値が
大きい場合には固定の閾値に近づくように、前
記計算値が小さい場合には所定の順序で配列さ
れた複数個の閾値からなる周期性閾値に近づく
ように前記入力画像信号に対する閾値を画素毎
に出力する閾値決定手段と、 (c) 前記入力画像信号を前記閾値決定手段の出力
により2値化する2値化手段と を備えたことを特徴とする適応擬似中間調化回
路。
[Scope of Claims] 1. A circuit that adaptively transforms an image signal including binary and continuous gradations into pseudo-halftones, the circuit comprising: a calculation means for calculating the sum of the absolute value of the difference between the pixel of the previous line and the pixel of interest and the absolute value of the difference between the pixel before the pixel of interest and the pixel of interest; (b) calculating the calculated value of the calculation means; Based on the above, the input image is adjusted such that when the calculated value is large, it approaches a fixed threshold, and when the calculated value is small, it approaches a periodic threshold consisting of a plurality of thresholds arranged in a predetermined order. Adaptive pseudo-halftone characterized by comprising: threshold determining means for outputting a threshold for a signal for each pixel; and (c) binarizing means for binarizing the input image signal using the output of the threshold determining means. circuit.
JP58016415A 1983-02-03 1983-02-03 Converting circuit for adaptive pseudo half tone Granted JPS59141873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58016415A JPS59141873A (en) 1983-02-03 1983-02-03 Converting circuit for adaptive pseudo half tone

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58016415A JPS59141873A (en) 1983-02-03 1983-02-03 Converting circuit for adaptive pseudo half tone

Publications (2)

Publication Number Publication Date
JPS59141873A JPS59141873A (en) 1984-08-14
JPH0526389B2 true JPH0526389B2 (en) 1993-04-15

Family

ID=11915600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58016415A Granted JPS59141873A (en) 1983-02-03 1983-02-03 Converting circuit for adaptive pseudo half tone

Country Status (1)

Country Link
JP (1) JPS59141873A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6191772A (en) * 1984-10-11 1986-05-09 Canon Inc Picture processor
JPH0793681B2 (en) * 1986-03-31 1995-10-09 株式会社東芝 Multi-gradation recording method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396616A (en) * 1977-01-31 1978-08-24 Dacom Inc Facsimile having analog signalltoobinary signal converter
JPS55120025A (en) * 1978-12-26 1980-09-16 Xerox Corp Image processing and device therefor
JPS5666970A (en) * 1979-11-06 1981-06-05 Toshiba Corp Binary device of variable density type picture
JPS587976A (en) * 1981-07-07 1983-01-17 Konishiroku Photo Ind Co Ltd Picture recording method
JPS5810961A (en) * 1981-07-13 1983-01-21 Canon Inc Binary coding method for picture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396616A (en) * 1977-01-31 1978-08-24 Dacom Inc Facsimile having analog signalltoobinary signal converter
JPS55120025A (en) * 1978-12-26 1980-09-16 Xerox Corp Image processing and device therefor
JPS5666970A (en) * 1979-11-06 1981-06-05 Toshiba Corp Binary device of variable density type picture
JPS587976A (en) * 1981-07-07 1983-01-17 Konishiroku Photo Ind Co Ltd Picture recording method
JPS5810961A (en) * 1981-07-13 1983-01-21 Canon Inc Binary coding method for picture

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