JPS5916437A - Address signal transmission system - Google Patents

Abstract

PURPOSE:To reduce the bit rate of data transmission, by providing an addressable function to an unnecessary information bit at a reduced error correcting code to eliminate the need for the bit exclusive for address designation. CONSTITUTION:The unnecessary information bits in reducing an error correcting code, i.e., 103 bits of the unnecessary information bits at the left side in a figure used only in forming a BCH code, not used as the specific information bit and not transmitted, are used for the address designation. Thus, the addressable function is provided without transmitting the bit exclusive for the address designation at all.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address signal transmission system, and particularly to an address signal transmission system suitable for use when transmitting digital audio signals using a CATV (cable television) line.

Background technology and its problems A four-level VSB (residual sideband) digital signal that transmits digital audio signals using a CATV line and can also use parts of television receivers currently in use as its hardware. A transmission method was previously proposed by the present inventors.

1 to 3 show the signal formats used at that time, and FIGS. 4 and 5 show the specific circuit configuration thereof.

First, to explain the signal format, Figure 1A shows, for example, L channel (16 bits), R channel (16 bits),
6 bits), here consisting of 34 bits of service bits (2 bits) used as address signals, Figure 1B is for example channels A, B,
C and D (both 34 pins)), BCH code (16
bit), 1 of the synchronization (5YNC) code (10 bits)
One word consisting of 62 bits.

FIG. 1C shows the signal format of one frame each consisting of 32 words (5184 bits).

and two series of such signal formats (i.e. 4
The transmission capacity (transmission speed) using the value level) is 44. I
Xl03X ((16X2+2) X4+16+10
) X2=14.2884MBPS. This is 3
．． 58MHz (7) Approximately 3d at color subcarrier level
The transmission rate of the filter with attenuation of B is 3.58X1 (r
X2

Furthermore, most of the errors in CATV lines are due to noise and other code amount interference in lieu of television signal interference. Therefore, the data format is configured to make it easy to measure error conditions.

In other words, an error correction code is added to each word, and the error correction code is, for example, a 6-bit error correction code having a 2-bit correction ability.
As shown in the figure, a shortened version of the (255,239) BCH code (152.136) is used, and this code is 136 bits to 1 information bit,
16 bits are check bits.

The signal distribution is as shown in Fig. 2A (for example, among channels A and D that make up the l series, channel A has a digital audio program (stereo) P 1
(16 bits for one channel at 44.1 KHz),
Channel B has a digital audio program (stereo) P2 (44.1KHz, 16 bits for one channel), channel C has announcement information (mono) (22.1KHz, 8 bits) P3 and guide information (mono/ ' ) (22,1KH2B bits)
facsimile P5 is sent to channel D on a time-sharing basis.
and facsimile P6 is inserted. Furthermore, P3 and P4&-!
, when two programs are selected at the same time, one of them is prioritized depending on the importance and urgency of the content. For example, here, P3 is prioritized over P4. To be done ~ to be saved. Also, regarding P5 and P6, one can be given priority over the other.

Also, the transmitting side uses the service bits (SB) of channels C and D.
) to be determined by ~・ru.

When transmitting another four stereo channels in addition to the above-mentioned one series of four stereo channels A to D, they are inserted on the side of FIG. 2B representing the other one series. In addition, if necessary, the sending side
As shown in Figure 5, pseudo data for measurement can be inserted and error status can be checked on the receiving side.

FIG. 3 exemplarily shows the case of obtaining a signal format for transmission at four-value levels. That is, in Figure 3A, 1
The signal configuration from channel A to channel D forming a series (corresponding to Fig. 2 A) is arranged, and the signal configuration from channel E to channel H forming a different l series is arranged in Fig. 3 B:Q (corresponding to Fig. 2 A). (corresponding to Figure 2 B). Then, the binary levels of A and B in FIG. 3 are converted to four-level levels, resulting in channels A and E as shown in FIG. 3C.

Channels B and F, channels C and G, and channels D and H are designed to form a single signal format. Further, in this case, the error correction codes of both series are also configured to have a four-value level.

That is, the BCH1 code in FIG. 3A and the BCH code in FIG. 3B are converted into four-value levels and arranged as shown in FIG. 3C. In this case, the synchronizing signal 5YNC is set to a binary level and not converted to a four-level level for reasons to be described later.

Next, a specific circuit configuration will be explained with reference to FIGS. 4 and 5. FIG. 4 shows the configuration of the transmitting side, and FIG. 5 shows the configuration of the receiving side.

First, to explain FIG. 4, input terminals (1) to (6)
) has the information power of programs P1 to P6 as described above.
Audio analog signals from input terminals (1) to (4) are supplied to Bunalog-digital converters (hereinafter referred to as A/D converters) (7) to (1).
- The analog signal is converted into a digital signal and supplied to the multiplexer (13) via the interface circuit I. On the other hand, input terminals (5) and (6) force and fl
Facsimile, which is a digital signal 1) Signal communication 1
, are supplied to multiplexer 04 via interface circuit I. Further, an address signal from the address switch circuit (12) is supplied to the multiplexer α through the interface circuit aυ. This addressing specifies at least one or more receivers. , these signals are distributed to each corresponding channel as described above, and are outputted with an error correction code, synchronization signal, etc. added thereto.Then, the output signal from the multiplexer (13) is In order to match the frequency characteristics of the entire transmitting/receiving system so as to eliminate interference, a 4-level signal converter circuit (t! , 7.15MBPS X
2 data series is converted into a 4-level baseband signal. Note that when there is only one data series to be transmitted (equivalent to 7.15 MBPS), the other one series may be fixed at the flxl+ or O1' level.

The output signal of the conversion circuit (1!19) is supplied to the AM modulator αt9, which also converts the output signal from the oscillator (I7) to, for example, 38.9M.
The Hz carrier wave is modulated by the output signal of conversion circuit α9. The degree of modulation at this time is, for example, a roll-off rate of 0.2.
In the case of 5, the maximum is 100%.

Therefore, a signal with an intermediate frequency f = 38.9 MHz is obtained on the output side of the modulator (lIlil), and this signal is passed through the vestigial sideband filter (VSBF) (19) to the mixing circuit (
11, where it is mixed with a signal of a local oscillation frequency, for example fl, from a local oscillation circuit and frequency converted.
It is taken out as a signal of frequency fl-fif on the output side. Note that the local oscillation frequency of the oscillation circuit is set to a frequency higher than the transmission frequency of any channel by the f-th frequency. Therefore, it is determined by selecting the local oscillation frequency of the transmission channel.

The output signal from the mixing circuit (11) is taken out to the output terminal 0 through the bandpass filter Qυ, and the signal from this output terminal 0 is supplied to the so-called head end (not shown) of the CATV system. The signal from the end is supplied to the receiving side via a CATV line (not shown).Note that (c) is a pseudo data generation circuit for generating pseudo data for testing.

The signal thus transmitted via the CATV line is supplied to the front end I32 from the receiving side input terminal C31) shown in FIG. converted into a frequency signal. This intermediate frequency signal is supplied to an AM detector, such as a PLL detector, where a four-level baseband signal is demodulated. Although the AM detector used in conventional television systems may be used, it is preferable to use a PLL detector as described above in order to avoid waveform distortion.

The output signal from the PLL detector (to) is sent to the level comparator (2
), where the level is identified where the eye patterns match, the digital data is extracted, and is supplied to the next stage demultiplexer. Here, signal processing such as data rearrangement, error correction, and extraction of a synchronization signal (5YNC) is performed. Then, when the address decoder (to) detects that the address value specified on the sending side matches the setting address value that is individually set in advance on the receiving side (receiver), the demultiplexer (c) The digital signal from the address decoder (to) is passed through the switches (361) to (362) of the switch circuit (t) under the control of the output signal from the address decoder (to) to the D/A converter 0! j
and 00, where the digital signal is converted into an analog signal and then output to output terminals (4 and 03, respectively).

When the switch (361) is on the contact a side, the program is P1, when it is on the contact side, the program is P2, and when the switch (362) is on the contact a side, the program is P1.
3. When it is on the contact side, program P4 is switched and taken out by the output signal from the address decoder (c). On the other hand, the facsimile signal is taken out via the switch circuit C371 to the output terminal Q4 through the facsimile interface circuit (4υ. Also in this case, when the switch of the switch circuit C17) is on the contact a side, the program P5 is taken out, and the program P5 is taken out on the contact side. At some point, program P6 is switched and retrieved. Then, when this receiving side (receiver) is not addressed at the sending side, that is, when the address value of the sending side and the set address value of the receiving side do not match, the address decoder (to) The muting signal causes each switch of the switch circuits 06) and o'i) to switch to the contact C side, and the receiving side is no longer able to receive information from the transmitting side.

In addition, the pit clock during these signal processing is performed with reference only to the period of the synchronization signal in order to reproduce the pit clock without being affected by jitter. That is, the synchronizing signal 5Y is on the output side of the PLL detector (c).
Since the output signal is a binary level signal only during the NC period and a 4-level signal during the rest of the time, the synchronizing signal 5YNC from the demultiplexer (to) and the data from the level comparator (b) are taken out. The bit clock is supplied to the clock regenerator (c), and the data, which is at a binary level only during the period of the synchronizing signal 5YNC, is extracted as a bit clock and supplied to the demultiplexer (to). In other words, by referring to the binary bell signal in the synchronization signal period, a bit clock with less jitter can be reproduced. Also, since the pattern is always constant during this synchronizing signal period, the AGC circuit 6e generates an AGC voltage by referring to the signal voltage during this synchronizing signal period, and supplies this to the front end 0. This ensures that the AG is always stable.
C operation can be obtained.

By the way, in the case of the circuits shown in Figures 4 and 5, it is possible to individually set the receiver to ENABLE (set the image to 5 or output sound) or DISABL through the broadcast radio waves.
In order to provide the so-called address designation (ADDRESSABLE) function, which prevents images from being displayed or makes no sound, the transmitting side must use a bit dedicated to address designation, as described above when the service bit was used as an address signal. Therefore, there is a problem that the number of bits per block increases and the bit rate of data transmission becomes high.

Furthermore, on the receiving side, it is necessary to provide an address decoder for decoding bits dedicated to address designation, which has disadvantages such as a complicated configuration.

SUMMARY OF THE INVENTION In view of these points, the present invention provides an address signal transmission system that can achieve a desired addressing function without transmitting bits dedicated to addressing.

Summary of the Invention In this invention, unnecessary information bits are used when shortening an error correction code, and a receiver to which an address is desired is given zero errors.
．． By giving a predetermined error, for example, an error that exceeds the muting threshold level, to a receiver that does not want to be addressed, the addressing function can be easily implemented without increasing the data transmission bit rate and with a simple configuration. It can be achieved.

EXAMPLE Hereinafter, an example of the present invention will be described in detail based on FIGS. 7 to 9.

7 and 8 show the configuration of this embodiment.
The figure shows the transmitting side, and FIG. 8 shows the receiving side. In each figure, parts corresponding to those in FIGS. 4 and 5 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the present invention, the unnecessary information bits when shortening the error correction code, that is, the left part in FIG. 6, which is used only when creating the BCH code, is not used as the original information bit, and is not transmitted. Use unnecessary information bits for addressing. In addition, unused 10
The reason why the LSB of the 3 bits [00...01] is set to 1 is because if these 103 unused bits are all O, then when all 136 bits of information are 0, the BCH code will also be all O. , since it becomes impossible to distinguish between the state where no information is transmitted or the line itself is broken, it is intentionally set as 1 so that it can be determined.

By the way, 103 bits are unused (00...01)
When the 136-bit information is all "CO" for
The code is [011・1111010110110]. And 0 errors for the receiver you want to address.
, for receivers that do not want to be addressed, for example, with an error exceeding a muting threshold level. For example, in Figure 6, the unused 103
The bits [00...01] are treated as error 0 and are used as the set address value for a receiver that does not specify an address. - 0 out of 103 bits [00...01] that are used forever
If we invert an arbitrary number of bits in the 0 part to 1 so that there is a small error (over the muting threshold level), and set this as the address value for the receiver that we do not want to address, the transmitter side 103 bits unused in
00...01] as the address value, a signal with an error that exceeds the muting threshold level is given to the receiver that does not want to be addressed on the receiving side. The receiver enters the DISABLE state, and on the other hand, the same signal appears to be erroneously O to the receiver that wants to specify the address, so the receiver enters the ENABLE state. Therefore, it is possible to have an addressable function without sending any address-specific bits. That's why.

If the muting threshold level on the receiving side is set to the case where 2-bit or more errors occur many times in succession, the number of addresses that can be specified (the number of 2-bit errors that occur) is 103C2=5253.

Therefore, in FIG. 7, an address switch circuit Q4 is provided for the α-th floor multiplexer, and the address value is set using the above-mentioned 103 unnecessary information bits. This address value can be arbitrarily set using the address switch circuit 04) as an unnecessary information filter.

On the other hand, on the receiving side, the demultiplexer (
In c), if the receiver is the one you want to address, the error is 0. In other words, the same address value as the address value on the transmitting side is set, and if the receiver does not want to be addressed, a predetermined error, for example, an error exceeding the muting threshold level, is set, and an address value different from the address value on the transmitting side is set. Ru.

On the transmitting side, the set address value of each receiver on the receiving side is known in advance, so by setting the address value on the transmitting side arbitrarily, it is possible to freely put any receiver in the ENABIJ state. Or DLSABLE
This gives you the ability to add addresses, such as changing the state.

If the receiving side (receiver) is currently addressed by the transmitting side, each switch of the switch circuit (to) and l37) is set to contact a or b side, the digital output signal from the demultiplexer (c) is connected to the D/A converter 0ω in the case of a digital audio signal.
And after converting to an analog signal with (4[), the output terminal (4
If it is a facsimile signal, it is output to the interface circuit (output terminal 04 through 4υ). In other words, the receiver is in the ENABIJ state.

If the receiving side is not addressed, all switches in the switch circuits (To) and 07) are switched to the contact C side by the control signal (muting signal) from the demultiplexer C149. Cut off the digital output signal from the demultiplexer.

In other words, the receiving side is in the DISABLE state.

For example, in FIG. 9, there is a single transmitter T that can set an address value that corresponds to the address value of the address switch circuit (goods) described above, and a plurality of receivers R that each have a predetermined set address value. If we consider that the set address value of the transmitter T is B'', only the receiver R set to this address value @B'' will be in the ENABLE state, and other than the address value ``B'', the address value ``A'', Receiver R set to "C" is in the DISABLE state. Also transmitter T
If the set address value of is A″, then this address value′″
Only the receiver R set to address value "A" is in the ENABLE state, and the receiver set to address value "B" 2°C is in the ENABLE state.
I 5ABLE state. The same applies to the address value "'C".

Application Example Note that in the above embodiment, an example was explained in which an address signal is added to a digital audio signal and a facsimile signal using a CATV line for multiplex transmission. It is similarly applicable to the case of transmission of other digital signals including.

Effects of the Invention As mentioned above (according to this invention, unnecessary information bits when shortening an error correction code are provided with an address supplement function,
There is no need to provide a bit dedicated to address designation as in the prior art, and the bit rate of data transmission can therefore be lowered. Furthermore, since there is no need to provide an address decoder for decoding bits dedicated to address designation on the receiving side, the configuration becomes simpler.

[Brief explanation of drawings]

1 to 3 are diagrams showing the signal format according to the prior art of the present invention, FIGS. 4 and 5 are block diagrams showing the specific circuit configuration thereof, and FIG. 6 is used to explain the present invention. FIGS. 7 and 8 are block diagrams showing one embodiment of the present invention, and FIG. 9 is a block diagram for explaining the present invention. (7) - α0 is an analog-to-digital converter, aυ is an interface circuit, cz, a4) is an address switch circuit, α9 is a multiplexer, αa is a binary transparsal filter (BTF), (ls is a 4-level level conversion circuit) , αQ is an AM modulator, (I7) is an oscillator, α~ is a vestigial sideband filter (VSBF), a wire is a mixing circuit, a wire is a local oscillation circuit, Qυ is a bandpass filter, (2) is a pseudo data generation circuit, C32 is the front end, (c)
is PLL detector, (goods) is level comparator, (c) is demultiplexer, (to), 07) is switch circuit, (to)
is an address decoder, C3!1゜ is a digital-to-analog converter, (4υ is a facsimile interface circuit, (4 is a clock recovery circuit, and (4e is an AGC circuit).

Claims (1)

[Claims] An address signal transmission method characterized by providing an addressable function to unnecessary information bits during error correction and code shortening.