JPH0531332B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field This invention relates to a digital signal transmission system, particularly
The present invention relates to a digital signal transmission system suitable for use when transmitting digital audio signals using a CATV (cable television) line.

Background technology and its problems A four-level VSB (residual sideband) digital signal that transmits digital audio signals using a CATV line and can also use parts of television receivers currently in use as its hardware. The transmission method was developed by the inventors,
suggested earlier.

FIGS. 1 to 3 show the signal formats used in this case, and FIGS. 4 and 5 show the specific circuit configuration thereof.

First, to explain the signal format, Figure 1A shows, for example, L channel (16 bits), R channel (16 bits), and here 34 service bits (2 bits) used as address signals.
One stereo channel consisting of bits, Figure 1B
For example, channels A, B, C and D (all
One word consists of 162 bits (34 bits), BCH code (16 bits), and synchronization (SYNC) code (10 bits); Figure 1C is 32 words (5184 bits)
The signal format of each frame is shown. The transmission capacity (transmission speed) using two series of such signal formats (ie, four-level levels) is 44.1×10 ³ ×{(16×2+2)×4+16+10}×2=14.2884 MBPS. This is within the permissible range of 3.58 x 10 ⁶ x 2 x 2 = 14.32 MBPS, which is a 4-level transmission rate of a filter with approximately 3 dB attenuation at the 3.58 MHz color subcarrier level, and is within the permissible range of 14.32 MBPS for one channel of television. It can be seen that sufficient transmission is possible with a transmission line having a bandwidth of 6MHz.

Also, most of the errors in CATV lines are due to intersymbol interference. Therefore, an error correction code is added to each word. For example, as shown in Figure 6, the (225, 239) BCH code has a 2-bit correction capability, and the (152, 136) BCH code is shortened. A BCH code is used, in which 136 bits are information bits,
16 bits are check bits.

As for the signal distribution, for example, as shown in Figure 2A, among the channels A to D that make up one series, channel A has digital audio program (stereo) P1 (44.1kHz, 16 bits for one channel), Channel B contains digital audio program (stereo) P2 (44.1kHz, 16 bits for each channel), and channel C contains announcement information (monaural) (22.1kHz 8 bits) P3 and guide information (monaural) (22.1kHz 8 bits) P4. Facsimile P5 and facsimile P6 are inserted into channel D in a time-division manner. Furthermore, when two programs are selected at the same time, P3 and P4 are given priority depending on the importance and urgency of the contents. For example, in this case, P3 is given priority over P4. It is given priority. or,
Regarding P5 and P6, one can be given priority over the other. The transmitting side is also determined by the service bits (SB) of channels C and D.

and the four stereo channels A to D mentioned above.
When transmitting four other stereo channels in addition to the one series, they are inserted on the side B of FIG. 2, which represents the other one series.

FIG. 3 exemplarily shows the case of obtaining a signal format for transmission at four-level levels. In other words, Fig. 3A shows the signal configuration from channel A to channel D forming one series (corresponding to Fig. 2A).
In FIG. 3B, signal configurations from channel E to channel H forming another series (corresponding to FIG. 2B) are arranged. and these third
The binary levels in Figures A and B are converted to a four-level level, and channels A and E, channels B and F, channels C and G, and channels D and H are mixed together as shown in Figure 3C. It is designed to configure two signal formats. Further, in this case, the error correction codes of both series also have a four-value level. In this case, the synchronization signal SYNC is set to a binary level and not converted to a four-level level for reasons to be described later.

Next, a specific circuit configuration will be explained with reference to FIGS. 4 and 5. FIG. 4 shows the configuration of the transmitting side, and FIG. 5 shows the configuration of the receiving side.

First, to explain Fig. 4, input terminals 1 to 1
Information on the programs P1 to P6 as described above is supplied to 6, respectively, and audio analog signals from input terminals 1 to 4 are input to analog-to-digital converters (hereinafter referred to as A/D converters) 7 to 10. The analog signal is converted into a digital signal and supplied to the multiplexer 13 via the interface circuit 11. On the other hand, facsimile signals, which are digital signals, for example, from input terminals 5 and 6 are supplied to a multiplexer 13 via an interface circuit 11. Further, an address signal from the address switch circuit 12 is supplied to the multiplexer 13 via the interface circuit 11. This address signal specifies the address of at least one receiver. Here, these signals are distributed to each corresponding channel as described above, and an error correction code, a synchronization signal, etc. are added and output. The output signal from the multiplexer 13 is sent to a digital-to-analog converter (hereinafter referred to as a D/A converter) through a BTF 14 to match the frequency characteristics of the entire transmitting and receiving system so as to eliminate intersymbol interference.
It is supplied to the value level conversion circuit 15, where
The 7.15MBPS x 2 data series is converted to a four-level baseband signal. In addition, if the data series you are trying to send is only one series (equivalent to 7.15MBPS), set the other one series to "1" or "0".
It should be fixed at the level of The output signal of the conversion circuit 15 is supplied to the AM modulator 16, where the carrier wave of, for example, 38.9 MHz from the oscillator 17 is modulated by the output signal of the conversion circuit 15. A signal with an intermediate frequency f _if =38.9 MHz is therefore obtained at the output of the modulator 16, which is fed through a vestigial sideband filter (VSBF) 18 to a mixing circuit 19.
Here, it is mixed with a signal of a local oscillation frequency, for example, f ₁ from the local oscillation circuit 20, frequency-converted, and outputted as a signal of a frequency f ₁ -f _if . Note that the local oscillation frequency of the oscillation circuit 20 is set to a frequency higher by f _if than the transmission frequency of any channel. Therefore, the transmission channel is determined by selecting the local oscillator frequency.

The output signal from the mixing circuit 19 is taken out to an output terminal 22 through a bandpass filter 21.
The signal from this output terminal 22 is supplied to a so-called head end (not shown) of the CATV system.
And the signal from the head end is
It is supplied to the receiving side via the CATV line. Note that 23 is an input device for other series data CH.E to CH.H.

The signal thus transmitted via the CATV line is supplied to the front end 32 from the receiving side input terminal 31 shown in FIG. 5, where it is amplified and then converted into an intermediate frequency signal such as 58.75 MHz. is converted to This intermediate frequency signal is supplied to an AM detector, for example, a PLL detector 33, where 4
The value level baseband signal is demodulated. still
As the AM detector, one used in a conventional television system may be used, but in order to avoid waveform distortion, it is preferable to use a PLL detector as described above.

The output signal from the PLL detector 33 is supplied to a level comparator 34, which identifies the level at an open eye pattern, extracts digital data, and supplies it to a demultiplexer 35 at the next stage. Then, signal processing such as data rearrangement, error correction, and synchronization signal (SYNC) extraction is performed here. When the address decoder 38 detects that the address value specified on the transmitting side matches the setting address value individually set in advance on the receiving side (receiver), the demultiplexer 3
The digital signal from 5 is sent to address decoder 38
switch circuit 36 under the control of the output signal from
D/A converter 3 via switches 36 ₁ and 36 ₂
9 and 40, where the digital signal is converted into an analog signal and then output to output terminals 42 and 4.
3 are output respectively. When the switch 36 ₁ is on the contact a side, program P1 is used, and when the switch 36 2 is on the contact b side, program P2 is used. When the switch 36 ₂ is on the contact a side, program P3 is used, and when the switch 36 2 is on the contact b side, program P4 is used as the address decoder. It is switched and taken out by the output signal from 38. On the other hand, the facsimile signal is taken out to the output terminal 44 via the switch circuit 37 and the facsimile interface circuit 41. In this case as well, when the switch of the switch circuit 37 is on the contact a side, program P5 is taken out,
When it is on the contact b side, program P6 is switched and taken out. When this receiving side (receiver) is not addressed at the transmitting side, that is, when the address value of the transmitting side and the set address value of the receiving side do not match, a muting signal from the address decoder 38 is used. Each switch of the switch circuits 36 and 37 is switched to the contact c side, and the receiving side cannot receive information from the transmitting side.

Further, the bit clock used in these signal processing is performed by referring only to the period of the synchronizing signal in order to reproduce the bit clock without being affected by jitter. That is, since the output side of the PLL detector 33 receives an output signal which is a binary level signal only during the synchronizing signal SYNC period and a four-level signal at other times, the synchronizing signal SYNC from the demultiplexer 35 and level comparator 34
The data from the bit clock is supplied to the clock regenerator 45, and the data, which is at a binary level only during the period of the synchronization signal SYNC, is extracted as a bit clock and supplied to the demultiplexer 35. In other words, by referring to the binary level signal during the synchronization signal period, a bit clock with less jitter can be reproduced. Also, since the pattern is always constant during this synchronization signal period, the AGC circuit 46 generates an AGC voltage by referring to the signal voltage during this synchronization signal period, and supplies this to the front end 32. This makes it possible to always obtain stable AGC operation.

By the way, in the case of the circuits shown in Figures 4 and 5, the receivers can be individually enabled via broadcast radio waves.
In order to provide the so-called ADDRESSABLE function, which allows the image to be displayed or emitted sound, or DISABLE (disabled from being displayed or emitted sound), a bit dedicated to address specification is required. Therefore, there is a limit to the number of addresses, and there are disadvantages such as not being able to obtain a satisfactory addressable function.

Purpose of the Invention In view of the above, the present invention makes it possible to expand the number of addresses and obtain multifunctional addressable functions by using, for example, unnecessary information bits when shortening an error correction code in addition to bits dedicated to address specification. This provides a digital signal transmission system that can

Summary of the Invention In this invention, by providing an addressable function to unnecessary information bits and bits dedicated to address specification when shortening an error correction code, it is possible to secure the same number of addresses as the product of both, and, for example, to use the former as a lower address. By using the latter as an upper address, it is possible to provide multifunctionality to the addressable function, such as access by group.

Furthermore, to explain specifically, for example, the first
As shown in FIGS. 6 and 9, the transmitter T
In a digital transmission system in which unnecessary information bits are added to the information bits and error correction coding is performed on the information bits, and the information bits and error correction code are transmitted together with address specification bits, the addressing specification bits (for example, 1, Service Bit SB)
and the above-mentioned unnecessary information bits are used as an address value for specifying the receiver R side.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail based on FIGS. 7 to 9.

7 and 8 show the configuration of this embodiment, with FIG. 7 showing the transmitting side and FIG. 8 showing the receiving side, respectively. In addition, in each figure, Figures 4 and 5
Portions corresponding to those in the figures are given the same reference numerals, and detailed explanation thereof will be omitted.

In the present invention, in addition to bits dedicated to addressing,
Unnecessary information bits when shortening the error correction code, that is, the 103 unnecessary bits on the left side in Figure 6 that are used only when creating the BCH code, are not used as original information bits, and are not transmitted. Use information bits for addressing.
In addition, the LSB of unnecessary information bits [00...01]
The reason why is set to 1 is that if all unnecessary information bits are 0, when all 136 bits of information are 0,
The BCH code also becomes all 0, making it impossible to determine that no information is being transmitted or that the line itself is disconnected, so it is intentionally set to 1 so that it can be determined. Incidentally, when all 136 bits of information for unnecessary information bits [00...01] are 0, the BCH code becomes [0111111010110110]. For example, the bits dedicated to address designation are used as upper addresses for accessing regions where receivers are located, and the unnecessary information bits are used as lower addresses for accessing individual receivers (one or several receivers). Of course, the assignment may be reversed. Bits dedicated to address specification may be processed in the same manner as in the prior art, but unnecessary information bits may be processed as follows. That is, the error is set to zero for the receiver to be addressed, and the error is set to exceed, for example, a muting threshold level for the receiver to which it is not desired to be addressed. For example, in Figure 6,
Use the unnecessary information bits [00...01] as the setting address value of the receiver you want to address, and on the other hand, invert any number of bits in the 0 part of the unnecessary information bits [00...01] to 1. , unnecessary information bit [00...
If the setting address value of a receiver that does not want to address is a value that has an error exceeding at least the muting threshold level for [00...01] on the transmitting side, By transmitting the BCH code generated as a value, on the receiving side, a signal with an error that exceeds the muting threshold level is given to a receiver that does not want to be addressed, and the receiver enters the DISABLE state. , on the other hand, since the same signal appears to be 0 errors to the receiver that wants to specify the address, the receiver enters the ENABLE state, so it is possible to provide addressable functionality to the receiver without sending any bits dedicated to address specification. That's why.

Furthermore, if the receiving side's muting threshold level is set to the case where 2-bit or more errors occur many times in a row, the number of addresses that can be specified using unnecessary information bits (the number that causes 2-bit errors) is ₁₀₃ C. ₂ = 5253. The number of addresses possible in this entire transmission system is the product of the number of addresses based on bits dedicated to address designation and the number of addresses based on unnecessary information bits. In other words, the number of addresses will be expanded accordingly.

Therefore, in addition to the address switch circuit 12 for the address designation dedicated bits provided for the interface 11 in FIG. 7, an address switch circuit 24 for unnecessary information bits is provided for the multiplexer 13. The switch circuit 12 sets, for example, an address value for accessing the area where the receiver is located, and the address switch circuit 24 sets an address value for accessing the receiver using, for example, the above-mentioned 103 unnecessary information bits. These address values can be set arbitrarily by the address switch circuits 12 and 24 using bits dedicated to address designation and unnecessary information bits.

On the receiving side, on the other hand, an address decoder 3 decodes bits dedicated to address designation, as in the conventional case, to a demultiplexer 35 of a receiver as shown in FIG.
8 is provided, and in the demultiplexer 35, if the receiver is to be addressed, the error is 0,
In other words, the same address value as the address value set by the address switch circuit 24 on the sending side is set,
If the receiver does not want to be addressed, a predetermined error, for example an error exceeding the muting threshold level, is set, that is, an address value different from the address value set by the address switch circuit 24 on the transmitting side is set.

On the transmitting side, the area of the receiving side and the set address value for each receiver are known in advance. Therefore, by setting the address value of the transmitting side arbitrarily, it is possible to freely send any address in any area. ENABLE the receiver, or
This provides addressable functions such as setting it to DISABLE state.

If the receiving side (receiver) is currently addressed by the transmitting side, each switch in the switch circuits 36 and 37 is activated by the gate output of the control signal from the demultiplexer 35 and the output signal from the address recorder 38. , is connected to the contact a or b side depending on the program information, and outputs the digital output signal from the demultiplexer 35 to the D/A converters 39 and 40 in the case of a digital audio signal.
output terminals 42 and 4 after converting it into an analog signal.
In the case of a facsimile signal, it is outputted to an output terminal 44 through an interface circuit 41. That is, when the address is specified by the address switch circuit 12 and the address is specified by the address switch circuit 24, the receiver is set to the ENABLE state.

Also, this receiving side is an address switch circuit 24.
If the address is not specified by the address switch circuit 12, then by the control signal (muting signal) from the demultiplexer 35, and if the address is not specified by the address switch circuit 12, by the output signal (muting signal) from the address decoder 38. The switches of the switch circuits 36 and 37 are all switched to the contact c side to cut off the digital output signal from the demultiplexer 35.
That is, when the address is no longer specified by at least one of the address switch circuits 12 or 24,
The receiving side is placed in a DISABLE state.

For example, in FIG. 9, there is a single transmitter T capable of setting an upper address and a lower address corresponding to each address value of the address switch circuits 12 and 24 described above, and a plurality of transmitters T each having a predetermined set address value. When considering a receiver R of
Only the receiver R set to is in the ENABLE state, and the address value “A” other than address value “B”,
Receiver R set to "C" is in the DISABLE state. Also, if the set address value obtained by the product of the upper address and lower address of transmitter T is "A",
Only the receiver R set to this address value “A” is in the ENABLE state, and the address values “B” and “C”
The receiver set to is in the DISABLE state. The same applies to address value "C".

Application Example In the above embodiment, an example was explained in which address signals are added to digital audio signals and facsimile signals and multiplexed transmission is performed using a CATV line, but the present invention is not limited to this.
The present invention is similarly applicable to the transmission of other digital signals including at least address signals.

Effects of the Invention As described above, according to the present invention, the unnecessary information bits and the bits dedicated to address specification when shortening the error correction code are given an addressable function, so that both the unnecessary information bits and the bits dedicated to address specification can be You can secure the number of addresses equal to the product of Access is also possible, and the addressable function can be provided with even more diverse functions.

[Brief explanation of the drawing]

1 to 3 are diagrams showing the signal format according to the prior art of the present invention, FIGS. 4 and 5 are block diagrams showing the specific circuit configuration thereof, and FIG. 6 is provided for explanation of the present invention. 7 and 8 are block diagrams showing an embodiment of the present invention,
FIG. 9 is a block diagram for explaining the present invention. 7 to 10 are analog-to-digital converters, 11
is an interface circuit, 12 and 24 are address switch circuits, 13 is a multiplexer, 14 is a binary transversal filter (BTF), 15
is a four-level level conversion circuit, 16 is an AM modulator, 17 is
is an oscillator, 18 is a residual sideband filter (VSBF),
19 is a mixing circuit, 20 is a local oscillation circuit, 21 is a band pass filter, 23 is an input device for other series data, 32 is a front end, 33 is a PLL detector,
34 is a level comparator, 35 is a demultiplexer,
36 and 37 are switch circuits, 38 is an address decoder, 39 and 40 are digital-to-analog converters, 41 is a facsimile interface circuit,
45 is a clock regeneration circuit, and 46 is an AGC circuit.

Claims (1)

[Claims] 1 The transmitter adds unnecessary information bits to the information bits and performs error correction encoding, transmits the information bits and error correction code including the address designation bits, and receives the data specified by the address designation dedicated bits. In a digital signal transmission system in which the transmitted information bits are corrected for errors using data with the same pattern as the unnecessary information bits and the transmitted error correction code, the unnecessary information bits are corrected in advance for each receiver. A digital signal transmission method characterized by setting different patterns.