JPS5916341A - Manufacture of substrate for integrated circuit - Google Patents
Manufacture of substrate for integrated circuitInfo
- Publication number
- JPS5916341A JPS5916341A JP12554282A JP12554282A JPS5916341A JP S5916341 A JPS5916341 A JP S5916341A JP 12554282 A JP12554282 A JP 12554282A JP 12554282 A JP12554282 A JP 12554282A JP S5916341 A JPS5916341 A JP S5916341A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- silicon
- substrate
- oxide film
- crystal silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Abstract
Description
【発明の詳細な説明】
本発明は、誘電体絶縁分離による集積回路用基板の製造
方法に係るもので、特に、シリコン酸化物によって絶縁
分離領域が形成される集積回路用基板の製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an integrated circuit substrate using dielectric isolation, and more particularly to a method for manufacturing an integrated circuit substrate in which an isolation region is formed using silicon oxide. It is.
半導体集積回路における素子の分離の方法には種々ある
が、最も一般的に用いられているものはｐｎ接合分離で
ある。しかし、近時、誘電体絶縁分離が、耐圧、容量、
スピード、リークなどの特性の面においてＰ）Ｊ接合よ
りも優れているので、その利用が考えられている。しか
し、この誘電体絶縁分離においては、工数が多くなるこ
と、歩留が低下すること、などが実用化の上で大きな問
題となっている。Although there are various methods for isolating elements in semiconductor integrated circuits, the most commonly used method is pn junction isolation. However, in recent years, dielectric isolation has improved
Since it is superior to the P)J junction in terms of characteristics such as speed and leakage, its use is being considered. However, in this dielectric insulation separation, there are major problems in practical use, such as an increase in the number of man-hours and a decrease in yield.
最も多く利用されている誘電体絶縁分離の方法は、単結
晶シリコン基板にｅを形成し、その上に酸化膜を形成し
た後に多結晶シリコンを１２００℃近い温度で約４００
μｍ堆積させるものである。The most commonly used dielectric isolation method is to form a dielectric layer on a single-crystal silicon substrate, form an oxide film on it, and then heat polycrystalline silicon to about 400℃ at a temperature close to 1200℃.
It is used to deposit micrometers.
このときの熱によってウェハが反ったり、損傷したシす
る問題があり、まだそのために、シリコン基板全研磨し
たときに単結晶シリコンの島が設計通りにできず、削り
過ぎと外ったり、完全に分離されなかったりしてしまう
ことが多い。There is a problem that the wafer may warp or be damaged due to the heat generated at this time, and as a result, when the silicon substrate is completely polished, islands of single crystal silicon cannot be formed as designed, and may come off due to excessive polishing, or may not be completely removed. Often they are not separated.
上記のような誘屯体絶縁分離技術における問題を解決す
る方法についても種々前えら１ｔでいる。There are various methods to solve the problems in the dielectric isolation technology as described above.
その一つに、溝を形成せずに、単結晶シリコンを部分的
に絶縁物に変換して絶縁分離領域を形成する方法がある
。One method is to partially convert single crystal silicon into an insulator to form an isolation region without forming a trench.
上記の絶縁分離領域の形成方法の改良てついて、本発明
者はすでに行頭１１ｉ’３５７−６７４７４において陽
極化成を利用して単結晶シリコンの島の側面を囲む誘１
１体絶縁分離領域を形成し、底面の絶縁層と接続するこ
とによって単結晶シリコンの島を分離する方法を提業し
ている。Regarding the improvement of the above-mentioned method of forming an insulating isolation region, the present inventor has already proposed a method for forming an insulating layer surrounding the side surface of a monocrystalline silicon island by using anodization at the beginning of the article 11i'357-67474.
The company proposes a method for isolating single-crystal silicon islands by forming monolithic isolation regions and connecting them to the bottom insulating layer.
本発明は、この単結晶シリコン全７ｉｊＬ分的に酸化す
ることによって絶縁分離領域を形成する集積回路用基板
の製造方法の改良に係るもので、浮遊容量の小さな集積
回路用基板を得ることを目的とする。The present invention relates to an improvement in a method for manufacturing an integrated circuit substrate in which an insulating isolation region is formed by oxidizing the entire 7ijL of single crystal silicon, and its purpose is to obtain an integrated circuit substrate with small stray capacitance. shall be.
本発明忙よる集積回路用基板の製造方法は、単結晶シリ
コンを部分的に酸化するとともだ酸化膜による絶縁層の
一部を溶かして空洞を形成することによって、上記の目
的を達成するものである。The method of manufacturing an integrated circuit substrate according to the present invention achieves the above object by partially oxidizing single crystal silicon and melting a portion of the insulating layer formed by the oxide film to form a cavity. be.
以下、図面に従って、本発明の実施例につき説明する。Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明の実施例を示す正面断面図である。Ｎ
型の導電性を有する単結晶シリコン基板１００表面を研
磨して平坦とする（ａ）、単結晶シリコン基板１０はＮ
型に限られず、Ｐ型であってもはｙ同様な工程を経て集
積回路用基板が得られる。FIG. 1 is a front sectional view showing an embodiment of the present invention. N
The surface of a single crystal silicon substrate 100 having type conductivity is polished to make it flat (a), the single crystal silicon substrate 10 is made of N
It is not limited to the type, but even if it is P type, an integrated circuit substrate can be obtained through the same process.
単結晶シリコン基板１００表面に５ｉＯｚから成るシリ
コン酸化膜１１を形成する（ｂ）。このシリコン酸化膜
は、単結晶シリコン基板１ｏと後に形成される多結晶シ
リコンとを絶縁し分離する層となる。A silicon oxide film 11 of 5 iOz is formed on the surface of the single crystal silicon substrate 100 (b). This silicon oxide film becomes a layer that insulates and separates the single crystal silicon substrate 1o from the polycrystalline silicon that will be formed later.
シリコン酸化膜１１の上にＩｌ］１ｓＮ４のシリコン窒
化膜１２を形成しておく（ｃ）。とのシリコン窒化膜は
シリコン酸化膜１１とともに絶縁層となるだけでなく、
後の工程において多結晶シリコンがフッ化水素に侵され
るのを防止する役割を果たす。但゛シ、このシリコン窒
化膜は必ずも形成する必要はない。A silicon nitride film 12 of Il]1sN4 is formed on the silicon oxide film 11 (c). The silicon nitride film not only serves as an insulating layer together with the silicon oxide film 11, but also
It plays a role in preventing polycrystalline silicon from being attacked by hydrogen fluoride in later steps. However, it is not always necessary to form this silicon nitride film.
シリコン窒化膜１２０表面にシリコンを気相成長させて
、多結晶シリコン１３ｆ１：形成する。多結晶シリコン
１３はシリコンウェハを支持するのに十分な厚み、例え
ば３インチウェハの場合には約４００μｍとなるように
形成される（ａ０単結晶シリコン基板１０を裏面から研
磨して県債回路素子を形成するのに適した厚みとする。Silicon is vapor-phase grown on the surface of the silicon nitride film 120 to form polycrystalline silicon 13f1. The polycrystalline silicon 13 is formed to have a thickness sufficient to support a silicon wafer, for example, approximately 400 μm in the case of a 3-inch wafer (the a0 single crystal silicon substrate 10 is polished from the back side to form a circuit element). The thickness is suitable for forming.
この単結晶シリコンは通常５〜５ｏμｍの厚みとされる
（ｅ）。This single crystal silicon usually has a thickness of 5 to 5 μm (e).
単結晶シリコン１ｏの表面を５ｉＢＮ４のシリコン窒化
膜１４で覆い、分離領域となる部分のみをエツチングし
て除去する（ト）。この場合、窒化シリコン膜１４の窓
は、分離領域の面積よりも小さくしておく。The surface of the single crystal silicon 1o is covered with a silicon nitride film 14 of 5iBN4, and only the portion that will become the isolation region is removed by etching (T). In this case, the window of the silicon nitride film 14 is made smaller than the area of the isolation region.
Ｎｍ基板を用いた場合には、陽極化成を容易にするだめ
に、窒化シリコン膜１４をマスクとしてＰ型の不純物を
単結晶シリコン１ｏに拡散または注入して、表面からシ
リコン酸化膜１１に達するＰ型領域１５を形成しておく
（ω。基板がＰ型である場合には、との工程は省略する
ととができる。When a Nm substrate is used, in order to facilitate anodization, P-type impurities are diffused or implanted into the single crystal silicon 1o using the silicon nitride film 14 as a mask, and P-type impurities reach the silicon oxide film 11 from the surface. A mold region 15 is formed (ω). If the substrate is of P type, steps of and can be omitted.
単結晶シリコン１０が部分的にＰ型に変換され、それ以
外の部分がシリコン窒化膜１４で覆われた状態で、単結
晶シリコン１Ｏｔ−フッ化水素（Ｈ７）中で陽極化成す
る（→。この陽極化酸洗よって、Ｐ型の単結晶シリコン
領域１５は多孔質シリコンとなる。Ｐ型の領域を陽極化
成するのに十分な時間以上に陽極化成を続けると、フッ
化水素は底面の酸化シリコン膜１１を溶かすようになる
。そしてフッ化水素の浸透した部分の酸化シリコン模１
１には空洞が形成されることに２よる。With the single crystal silicon 10 partially converted to P type and the other parts covered with the silicon nitride film 14, the single crystal silicon 10 is anodized in 1Ot-hydrogen fluoride (H7) (→. This By anodizing and pickling, the P-type single-crystal silicon region 15 becomes porous silicon.If anodization is continued for a period longer than sufficient to anodize the P-type region, the hydrogen fluoride will dissolve into the silicon oxide on the bottom surface. It begins to dissolve the film 11.Then, the silicon oxide model 1 in the area where hydrogen fluoride has penetrated
It is based on 2 that a cavity is formed in 1.
次に多孔質化した単結晶シリコン１５を酸化してシリコ
ン酸化物゛１６とする（５．）。このシリコン酸化物１
６が単ザ１吉晶シリコンの島を囲む絶縁分離領域となる
。Next, the porous single crystal silicon 15 is oxidized to form silicon oxide 16 (5.). This silicon oxide 1
6 is an insulating isolation region surrounding the island of single crystal silicon.
上記のようにして、単結晶シリコンの島が、側面はシリ
コン酸化物により、底面は空洞を有するシリコン酸化膜
によＬ・、囲まれて形成され誘電体によって絶縁され、
分離された、イも積回路用基板が得られる。As described above, an island of single crystal silicon is formed surrounded by silicon oxide on the side surfaces and a silicon oxide film having a cavity on the bottom surface, and is insulated by a dielectric material,
A separated integrated circuit board is obtained.
本発明による集積回路用基板の製造方法（ｄ前記の例に
限られず、種々の実施例が考えられる。以下、それらの
うちの主要なものについてＲ１？１明しておく。The method for manufacturing an integrated circuit board according to the present invention (d) is not limited to the above-mentioned example, and various embodiments can be considered.The main ones among them will be explained below.
第２図は、本発明の他の実施例の正面断面図であるが、
これはシリコン酸化膜の両側にシリコン窒化膜を形成す
る場合を示しだものである。すなわち、単結晶シリコン
基板２０を予めシリコン窒化膜２２で覆い、絶縁領域の
形成パターンに従って窓を形成して分く（８）。次にシ
リコン酸化ｊ漠２１を形成しく１〕）、その上をシリコ
ン窒化膜２２′で覆う。この後のプロセスは第１図の場
合と同じである。このようにして得られる＃４．積回路
用基板では、シリコン酸化ｊ漠２１が二つのシリコン窒
化膜によって挾まれ、しかも、空洞が形成される構造と
なる（１）。これによって、底面の絶縁層が多層となる
とともに、多孔質シリコンの酸化の際に単結晶シリコン
の底面が酸化されることを防止できる。FIG. 2 is a front sectional view of another embodiment of the present invention,
This shows the case where silicon nitride films are formed on both sides of a silicon oxide film. That is, the single-crystal silicon substrate 20 is covered in advance with a silicon nitride film 22, and windows are formed and separated according to the formation pattern of the insulating regions (8). Next, a silicon oxide layer 21 is formed (1), and the silicon nitride layer 22' is covered thereon. The subsequent process is the same as in FIG. #4 obtained in this way. The integrated circuit board has a structure in which a silicon oxide film 21 is sandwiched between two silicon nitride films, and a cavity is formed (1). As a result, the insulating layer on the bottom surface becomes multilayered, and the bottom surface of the single crystal silicon can be prevented from being oxidized during oxidation of the porous silicon.
本発明によれば、底面の分離領域が８１０２ではなく、
空洞をもったシリコン酸化膜によって形成されるので、
浮遊容量を大ｊ１１１＋；に低下さぜることができる。According to the present invention, the separation area on the bottom surface is not 8102,
It is formed from a silicon oxide film with cavities, so
The stray capacitance can be reduced to a large value j111+;.
すかわち、容量ＣはＣ−λ−で表わされる（εけ誘α率
、８は面積、ｄは距１’！ｉＡ ）が、シリコンの誘眠
率１２．５ｉ０２の誘電率３．８に対して空気の誘電率
は１であるので、空洞を形成することによって容量Ｏを
大１清に低減することができる。空洞を理想的に形成す
れば、ＰＨ接合分離の！シ）倉の１／１２、従来の誘ｊ
（１体分離の１／３．ｓとすることができる。In other words, the capacitance C is expressed as C-λ- (ε and α constant, 8 is the area, and d is the distance 1'!iA), whereas the dielectric constant of silicon is 12.5i02 and the dielectric constant is 3.8. Since the dielectric constant of air is 1, the capacitance O can be reduced by a factor of 1 by forming a cavity. If the cavity is formed ideally, PH junction separation can be achieved! C) 1/12 of the warehouse, conventional kidnapping
(It can be 1/3.s of one body separation.
また、シリコン酸１ヒ膜をシリコン窒化膜で挾まれ、か
つ空洞どなるようにｔＪｔば、絶縁層（誘醍体層）が多
層となって容１：１１をより小さくする効果もあり、ま
た、酸化の際に空洞が５１ｏ２が成長して埋められるこ
とを防止できる利点もめる。In addition, if the silicon oxide film is sandwiched between silicon nitride films and the cavity is tJt, the insulating layer (dielectric layer) becomes multilayered, which has the effect of making the capacitance 1:11 smaller. It also has the advantage of preventing cavities from being filled by 51o2 growth during oxidation.
更に、本発明においてＶよ、空洞を形成するための工程
を特別に付加する必要もなく、陽極化成の工程において
同時にできるので、特別の装置Ｒ，を必要としない。Furthermore, in the present invention, there is no need to add a special process for forming cavities, and since the process can be performed simultaneously with the anodization process, no special equipment R is required.
第１図、第２図は本発明の実施例を示す正ｆｆｉ？断面
凹である。
ｉｎ、２０・・・・・・ｇｌ、 Ｈ１晶シリコン。
１１．２１・・・・・・シリコン酸化膜。
１２．１４．２２・・・・・・シリコン窒化膜。
１５・・・・・・多孔質シリコン。
１６・・・・・・シリコン酸化物
特：Ｆｌ’出願人 自動耐測技術研究組合代哩人 弁
理士 大 １） 優
第 １ 図FIGS. 1 and 2 show an embodiment of the present invention. It has a concave cross section. in, 20...gl, H1 crystal silicon. 11.21...Silicon oxide film. 12.14.22...Silicon nitride film. 15...Porous silicon. 16...Silicon oxide special: Fl' Applicant, Representative of Automatic Testing Technology Research Association, Patent Attorney, University 1) Yu No. 1
Claims (1)
〜、該シリコン酸化膜上に多結晶シリコン層を形成し、
該単結晶シリコン基板ｔ−裏面から研磨して所定のｊ厚
さとし、該研磨された単結晶シリコン基板の表面の一部
をシリコン窒化膜でヤ荒い、該シリコン窒化膜をマスク
としてフッ化水素中で該単結晶シリコンを陽極化成して
、該シリコン窒化膜に覆われない部分とその下の領域を
多孔質化するとともに該シリコン酸化膜の一部をフッ化
水素で溶かして単結晶シリコン基板と多結晶シリコン層
の間に空洞を形成し、蚊多孔質化された単結晶シリコン
を酸化してシリコン酸化物を形成することによって、該
シリコン酸化物と少なくとも一部が空洞とΔつだシリコ
ン酸化膜によって分離された単結晶シリコンの島を形成
することを特徴とする集積回路用基板の一製造方法。Forming a silicon oxide film on one surface of a single crystal silicon substrate 1
~, forming a polycrystalline silicon layer on the silicon oxide film,
The single-crystal silicon substrate is polished from the back side to a predetermined thickness, a part of the surface of the polished single-crystal silicon substrate is roughened with a silicon nitride film, and the silicon nitride film is used as a mask in hydrogen fluoride. Then, the single crystal silicon is anodized to make the portion not covered with the silicon nitride film and the area below it porous, and a part of the silicon oxide film is dissolved with hydrogen fluoride to form a single crystal silicon substrate. By forming a cavity between the polycrystalline silicon layers and oxidizing the porous single crystal silicon to form silicon oxide, the silicon oxide is formed such that at least a portion of the silicon oxide has a Δ-contact with the cavity. A method of manufacturing a substrate for an integrated circuit, characterized by forming islands of single crystal silicon separated by a membrane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12554282A JPS5916341A (en) | 1982-07-19 | 1982-07-19 | Manufacture of substrate for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12554282A JPS5916341A (en) | 1982-07-19 | 1982-07-19 | Manufacture of substrate for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5916341A true JPS5916341A (en) | 1984-01-27 |
| JPS6244412B2 JPS6244412B2 (en) | 1987-09-21 |
Family
ID=14912768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12554282A Granted JPS5916341A (en) | 1982-07-19 | 1982-07-19 | Manufacture of substrate for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5916341A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7829971B2 (en) | 2007-12-14 | 2010-11-09 | Denso Corporation | Semiconductor apparatus |
| US8148809B2 (en) | 2009-01-15 | 2012-04-03 | Denso Corporation | Semiconductor device, method for manufacturing the same, and multilayer substrate having the same |
-
1982
- 1982-07-19 JP JP12554282A patent/JPS5916341A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7829971B2 (en) | 2007-12-14 | 2010-11-09 | Denso Corporation | Semiconductor apparatus |
| US8148809B2 (en) | 2009-01-15 | 2012-04-03 | Denso Corporation | Semiconductor device, method for manufacturing the same, and multilayer substrate having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6244412B2 (en) | 1987-09-21 |
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