JPS59162668U - Negative phase detection circuit for power conversion equipment - Google Patents
Negative phase detection circuit for power conversion equipmentInfo
- Publication number
- JPS59162668U JPS59162668U JP5667983U JP5667983U JPS59162668U JP S59162668 U JPS59162668 U JP S59162668U JP 5667983 U JP5667983 U JP 5667983U JP 5667983 U JP5667983 U JP 5667983U JP S59162668 U JPS59162668 U JP S59162668U
- Authority
- JP
- Japan
- Prior art keywords
- power
- detection circuit
- phase detection
- negative phase
- power conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図および第2図は純ブリツジ接続例の電力変換装置
の要部構成図およびそのサイリスタの制御信号波形図、
第3図は本考案の一実施例の要部構成を示す系統図、第
4図、第5図および第6図は第3図の説明のため示した
波形図である。
1・・・・・・三相交流電源、2・・・・・・電力変換
器、3・・・・・・停電検出器、4・・・・・・遅延器
、5・・・・・・Dフリップフロップ、6・・・・・・
論理和ゲート。FIGS. 1 and 2 are main part configuration diagrams of a power conversion device with a pure bridge connection example, and control signal waveform diagrams of its thyristors,
FIG. 3 is a system diagram showing the main structure of an embodiment of the present invention, and FIGS. 4, 5, and 6 are waveform diagrams shown for explaining FIG. 3. 1... Three-phase AC power supply, 2... Power converter, 3... Power failure detector, 4... Delay device, 5...・D flip-flop, 6...
Disjunction gate.
Claims (1)
該交流電源の電力変換を行うものにおいて、前記交流電
源の停電検出を行う停電検出器の出力信号をセット端子
に入力し、かつ該交流電源の所定の二相に同期したパル
ス入力信号の一方をクロック入力端子に他方をD入力端
子に得るDフリップフロップと、前記停電検出器の出力
信号を得る遅延器の出力と前記Dフリップフロップの出
力を入力する論理和ゲートとを設けて成ることを特徴と
する電力変換装置の逆相検出回路。In a device that obtains AC power through a switching element connected in a bridge and converts the power of the AC power source, an output signal of a power failure detector that detects a power failure of the AC power source is inputted to a set terminal, and a predetermined value of the AC power source is a D flip-flop that receives one of the pulse input signals synchronized with the two phases of the clock input terminal and the other one to the D input terminal; the output of the delay device that obtains the output signal of the power failure detector; and the output of the D flip-flop that receives the output signal of the power outage detector. What is claimed is: 1. A negative phase detection circuit for a power conversion device, comprising: an OR gate;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5667983U JPS59162668U (en) | 1983-04-18 | 1983-04-18 | Negative phase detection circuit for power conversion equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5667983U JPS59162668U (en) | 1983-04-18 | 1983-04-18 | Negative phase detection circuit for power conversion equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59162668U true JPS59162668U (en) | 1984-10-31 |
Family
ID=30187000
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5667983U Pending JPS59162668U (en) | 1983-04-18 | 1983-04-18 | Negative phase detection circuit for power conversion equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59162668U (en) |
-
1983
- 1983-04-18 JP JP5667983U patent/JPS59162668U/en active Pending
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