JPS59161845A - Containing package for semiconductor device - Google Patents

Containing package for semiconductor device

Info

Publication number
JPS59161845A
JPS59161845A JP3627883A JP3627883A JPS59161845A JP S59161845 A JPS59161845 A JP S59161845A JP 3627883 A JP3627883 A JP 3627883A JP 3627883 A JP3627883 A JP 3627883A JP S59161845 A JPS59161845 A JP S59161845A
Authority
JP
Japan
Prior art keywords
package
input
interposed
isolation
output terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3627883A
Other languages
Japanese (ja)
Inventor
Shintaro Takase
信太郎 高瀬
Hidenori Takahashi
英徳 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3627883A priority Critical patent/JPS59161845A/en
Publication of JPS59161845A publication Critical patent/JPS59161845A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736Metallic materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To improve the high frequency isolation between the input and output by a method wherein a buffer material which absorbs the stress caused by the difference of coefficients of thermal expansion is split in the direction of the extension of input-output terminals, and then an isolation member electrically connected to a package substrate is inserted to the split end surfaces, when said buffer material is interposed between the package substrate made of a metal and a ceramic package mounted thereon. CONSTITUTION:A semiconductor element mounting base 4 is provided on the package substrate 1 made of a metal, and the ceramic package 3 having an aperture corresponding to the mounting base 4, the input terminal 5 and the output terminal 6 projecting out from the aperture is provided, thus being decided as the titled package. In this constitution, the buffer member 12 made of an Mo plate, etc. is provided under the mounting base 4 as an underlay. At this time, this member 12 is split, and the isolation member 13 put in electric contact with the substrate 1 is interposed between the produced split end surfaces. Thus, a package of good isolation between input-output terminals even in a high frequency band is obtained.

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明は半導体装置の収容容器の改良に関する。[Detailed description of the invention] (al Technical field of invention The present invention relates to improvements in housing containers for semiconductor devices.

(bl  従来技術と問題点 半導体装置、特に高周波高出力半導体装置用の収容容器
は、要請される高周波特性を満足させ且つ素子内部で発
生する熱を速やかに外部に放出し得るよう良好な放熱特
性を具備せしめるため、第1図(a) 、 Tblに示
すような構造のものが多く用いられる。なお第1図(a
lは従来の半導体装置の収容容器(以下単にパッケージ
と記す)の平面図、(blはその断面図である。
(bl) Prior Art and Problems Containers for semiconductor devices, especially high-frequency, high-power semiconductor devices, have good heat dissipation properties so as to satisfy the required high-frequency characteristics and to quickly release the heat generated inside the device to the outside. In order to provide the
1 is a plan view of a conventional housing container for a semiconductor device (hereinafter simply referred to as a package), and bl is a cross-sectional view thereof.

同図において、1は無酸素銅(Cu)よりなるパッケー
ジ基体、2はモリブデン(Mo)板、3はセラミックよ
りなる外囲器、4はパッケージ基体1を突起させて形成
した半導体素子の載置台、5及び6は入力及び出力の端
子である。これを実際に使用する際には、半導体素子(
例えばGaAs−FET、図示せず)を載置台4上に接
着し、金属細線をボンディングして上記入力端子5及び
出力端子6を半導体素子の対応する電極バンド(前記G
aAs−FETにあってはゲート電極及びドレイン電極
)とを電気的に接続する。しがる後上記セラミ7り外囲
器3の上面に金属板等からなる蓋(図示せず)を接着し
て、半導体素子を気密封止する。
In the figure, 1 is a package base made of oxygen-free copper (Cu), 2 is a molybdenum (Mo) plate, 3 is an envelope made of ceramic, and 4 is a mounting table for a semiconductor element formed by protruding the package base 1. , 5 and 6 are input and output terminals. When actually using this, the semiconductor element (
For example, a GaAs-FET (not shown) is glued on the mounting table 4, and thin metal wires are bonded to connect the input terminal 5 and output terminal 6 to the corresponding electrode band (the G
In the aAs-FET, the gate electrode and the drain electrode are electrically connected. After that, a lid (not shown) made of a metal plate or the like is adhered to the upper surface of the ceramic envelope 3 to hermetically seal the semiconductor element.

上記構造において、モリブデン板2は、そりプデンがセ
ラミックに近い熱膨張係数を有することから、上記クラ
ンクの発生を防止するためにパッケージ基体1とセラミ
ック外囲器3との間に介装された緩衝材である。
In the above structure, the molybdenum plate 2 is a buffer interposed between the package base 1 and the ceramic envelope 3 in order to prevent the occurrence of the above-mentioned crank, since sled molybdenum has a coefficient of thermal expansion close to that of ceramic. It is a material.

ところモリブデン板2の表面は接着材である銀源との濡
れ性が悪いため、パッケージ基体1とモリブデン板2点
の接着は必ずしも良好とは言い難い。そのためモリブデ
ン板2は高周波的にはアース(接地)が取れておらず、
2つの端子リー15゜6とモリブデン板2との間の浮遊
容量を介して入力端子5と出力端子6間に帰還を生じ、
従って入出力端子間のアイソレーションが低下するとい
う難点があった。第2図はパッケージの入出力端子間の
等価回路図であって、c、、C2は入力及び出力端子5
,6とモリブデン板2間の浮遊容量、L、、L2はモリ
ブデン板2自身のインダクタンスを示す。
However, since the surface of the molybdenum plate 2 has poor wettability with the silver source, which is an adhesive, the adhesion between the package substrate 1 and the two molybdenum plates is not necessarily good. Therefore, the molybdenum plate 2 is not grounded in terms of high frequencies,
Feedback occurs between the input terminal 5 and the output terminal 6 via the stray capacitance between the two terminal leads 15°6 and the molybdenum plate 2,
Therefore, there was a problem that the isolation between the input and output terminals deteriorated. Figure 2 is an equivalent circuit diagram between the input and output terminals of the package, where c, , C2 are the input and output terminals 5
, 6 and the stray capacitance L, , L2 between the molybdenum plate 2 represents the inductance of the molybdenum plate 2 itself.

tc+  発明の目的 本発明の目的は上記問題点を解消して、パッケージの入
出力間における高周波のアイソレーションの良好な半導
体装置の収容容器を提供することにある。
tc+ OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and provide a container for housing semiconductor devices with good high-frequency isolation between the input and output of the package.

(d)  発明の構成 本発明の特徴は、金属よりなるパッケージ基体と該パッ
ケージ基体上面に取りつけられたセラミックよりなる外
囲器との間に、前記パッケージ基体とセラミックよりな
る外囲器との熱膨張係数の差に起因するストレスの緩衝
材が介装されてなる構造において、前記緩衝材が入出力
端子の延在する方向に少なくとも2個に分割され、且つ
該緩衝材の対向する分割端面間に前記パッケージ基体に
電気的に接続された分離部材が介装されてなることにあ
る。
(d) Structure of the Invention A feature of the present invention is that heat generated between the package base and the ceramic envelope is disposed between the package base made of metal and the ceramic envelope attached to the upper surface of the package base. In a structure in which a buffer material for stress caused by a difference in expansion coefficients is interposed, the buffer material is divided into at least two parts in the direction in which the input/output terminal extends, and the buffer material is divided into at least two pieces, and there is a gap between opposing divided end faces of the buffer material. A separation member electrically connected to the package base is interposed therein.

(al  発明の実施例 以下本発明の一実施例を図面を参照しながら説明する。(al Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

第3図(a)、 (blは本実施例の平面図及び断面図
、第4図は上記一実施例の入出力端子間の等価回路図、
第5図(a)〜(C1は第3図に示す本実施例の分解斜
視図である。
FIG. 3(a), (bl is a plan view and a sectional view of this embodiment, FIG. 4 is an equivalent circuit diagram between input and output terminals of the above embodiment,
5(a) to (C1) are exploded perspective views of the present embodiment shown in FIG. 3. FIG.

第5図に示すように本実施例では、従来のパッケージで
は緩衝部材のモリブデン板2が環状の一体物であったの
を、第5図(b)に示す如く2個に分割して “U”の
字状のモリブデン板12となし、この2個のモリブデン
板I2を、第5図fc)に見られるように載置台4のパ
ッケージ基体1の入出力端子の配列方向端面に、新たに
パッケージ基体1を突起させて形成した分離部材13を
挟んで対向させ、該分離部材13及びパンケージ基体1
とに銀源を用いて接着する。ここでモリブデン板12と
分離部材13の上面は略同一平面を形成するよう、2個
のモリブデン板12及び分離部材13の厚さを選択する
As shown in FIG. 5, in this embodiment, the molybdenum plate 2 of the buffer member is an annular integral piece in the conventional package, but it is divided into two pieces as shown in FIG. 5(b). These two molybdenum plates I2 are placed on the end face of the package base 1 of the mounting table 4 in the direction in which the input/output terminals are arranged, as shown in FIG. The separation member 13 and the pancage base 1 are opposed to each other with a separation member 13 formed by protruding the base 1 interposed therebetween.
Glue using a silver source. Here, the thicknesses of the two molybdenum plates 12 and the separation member 13 are selected so that the upper surfaces of the molybdenum plates 12 and the separation member 13 form substantially the same plane.

そしてその上に第5図fa)に示すセラミック外囲器3
を接着する。
Then, on top of that, a ceramic envelope 3 shown in Fig. 5fa) is placed.
Glue.

このように構成された本実施例のパッケージ(第3図(
al及び(bl参照)は、緩衝材であるモリブデン板が
2分割され、更に両者の対向する端面間に分離部材13
が介装されたことにより、上記2個のモリブデン板12
の対向する端面間の電気力線は切断される。従って本実
施例においては、第2図に示した等価回路のモリブデン
板2自身のインダクタンスL1及びL2が分割されしか
もその間が開放状態となる。第4図に上記本実施例のパ
ッケージの等価回路を示す。同図においてL 、/ 、
  L 2/は2個のモリブデン板12自身のインダク
タンスである。このように本実施例では入出力端子間が
高周波的に遮断されるので、入出力間の帰還が防止され
、アイソレーションが改善される。
The package of this embodiment configured in this way (Fig. 3 (
In al and (see bl), a molybdenum plate serving as a buffer material is divided into two parts, and a separation member 13 is placed between the opposing end surfaces of the two parts.
is interposed, the two molybdenum plates 12
The lines of electric force between the opposing end faces of are cut. Therefore, in this embodiment, the inductances L1 and L2 of the molybdenum plate 2 itself in the equivalent circuit shown in FIG. 2 are divided, and the space between them is in an open state. FIG. 4 shows an equivalent circuit of the package of this embodiment. In the same figure, L, /,
L 2/ is the inductance of the two molybdenum plates 12 themselves. As described above, in this embodiment, since the input and output terminals are cut off at high frequency, feedback between the input and output terminals is prevented, and isolation is improved.

なお上述の如く2分割されたモリブデン板12の端面間
には分離部材13が介装され且つ接着されているので、
形状的には従来のパッケージと全く同一となるので、封
止後においては従来のパッケージと同様に十分な気密性
を得ることが出来、何ら問題はない。
Furthermore, since the separation member 13 is interposed and bonded between the end faces of the molybdenum plate 12 divided into two parts as described above,
Since the shape is exactly the same as the conventional package, after sealing, sufficient airtightness can be obtained like the conventional package, and there is no problem.

なお上記一実施例においては、緩衝材を2f[lilに
分割した例を掲げて説明したが、分割数は2個に限定さ
れるものではなく、3個以上であっても良い。
Although the above embodiment has been described with reference to an example in which the cushioning material is divided into 2f[lil], the number of divisions is not limited to two, and may be three or more.

また緩衝材はパッケージ基体1とセラミック筒外囲器3
との熱膨張係数の差に起因するストレスを吸収し得るも
のであれば良く、従ってこれはモリブデン板に限定され
る必要はない。
In addition, the cushioning materials are the package base 1 and the ceramic cylinder envelope 3.
Any material may be used as long as it can absorb the stress caused by the difference in coefficient of thermal expansion between the material and the material, so it is not necessary to be limited to molybdenum plates.

(fl  発明の詳細 な説明した如く本発明により、高周波帯においても入出
力端子間のアイソレーションが良好な半導体装置の収容
容器が提供される。
(fl) As described in detail, the present invention provides a housing container for semiconductor devices with good isolation between input and output terminals even in a high frequency band.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の収容容器の要部を示す平面
図及び断面図、第2図は上記従来の収容容器の入出力端
子間の等価回路図、第3図は本発明の一実施例の要部を
示す平面図及び断面図、第4図は上記一実施例の入出力
端子間の等価回路図、第5図は上記一実施例の分解斜視
図である。 図において、1はパッケージ基体、2及び12は緩衝材
、3はセラミック外囲器、4は半導体素子の載置台、5
及び6は入力及び出力端子、13は分離部材を示す。 第1図 第2図 第 3 図 第4図 第 5 図
FIG. 1 is a plan view and a sectional view showing the main parts of a conventional storage container for a semiconductor device, FIG. 2 is an equivalent circuit diagram between input and output terminals of the conventional storage container, and FIG. 3 is an embodiment of the present invention. FIG. 4 is an equivalent circuit diagram between the input and output terminals of the embodiment, and FIG. 5 is an exploded perspective view of the embodiment. In the figure, 1 is a package base, 2 and 12 are cushioning materials, 3 is a ceramic envelope, 4 is a mounting table for semiconductor elements, and 5
and 6 indicate input and output terminals, and 13 indicates a separation member. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 金属よりなるパッケージ基体と該パッケージ基体上面に
取りつけられたセラミックよりなる外囲器との間に、前
記パンケージ基体とセラミックよ・りなる外囲器との熱
膨張係数の差に起因するストレスの緩衝材が介装されて
なる構造において、前記緩衝材が入出力端子の延在する
方向に少なくとも2個に分割され、且つ該緩衝材の対向
する分割端面間に前記パンケージ基体に電気的に接続さ
れた分離部材が介装されてなることを特徴とする半導体
装置の収容容器。
Between the package base made of metal and the envelope made of ceramic attached to the upper surface of the package base, there is a buffer for stress caused by the difference in coefficient of thermal expansion between the package base and the envelope made of ceramic. In the structure in which a material is interposed, the buffer material is divided into at least two parts in the direction in which the input/output terminal extends, and the opposing divided end faces of the buffer material are electrically connected to the pan cage base. 1. A storage container for a semiconductor device, characterized in that a separating member is interposed therein.
JP3627883A 1983-03-04 1983-03-04 Containing package for semiconductor device Pending JPS59161845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3627883A JPS59161845A (en) 1983-03-04 1983-03-04 Containing package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3627883A JPS59161845A (en) 1983-03-04 1983-03-04 Containing package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS59161845A true JPS59161845A (en) 1984-09-12

Family

ID=12465308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3627883A Pending JPS59161845A (en) 1983-03-04 1983-03-04 Containing package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS59161845A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020009953A (en) * 2018-07-10 2020-01-16 住友電工デバイス・イノベーション株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020009953A (en) * 2018-07-10 2020-01-16 住友電工デバイス・イノベーション株式会社 Semiconductor device
US10903171B2 (en) 2018-07-10 2021-01-26 Sumitomo Electric Device Innovations, Inc. Semiconductor device
US11508672B2 (en) 2018-07-10 2022-11-22 Sumitomo Electric Device Innovations, Inc. Semiconductor device

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