JPS59156008A - Signal input blocking circuit - Google Patents
Signal input blocking circuitInfo
- Publication number
- JPS59156008A JPS59156008A JP58029280A JP2928083A JPS59156008A JP S59156008 A JPS59156008 A JP S59156008A JP 58029280 A JP58029280 A JP 58029280A JP 2928083 A JP2928083 A JP 2928083A JP S59156008 A JPS59156008 A JP S59156008A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input
- operational amplifier
- signal input
- impressed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000903 blocking effect Effects 0.000 title claims description 8
- 230000003321 amplification Effects 0.000 claims description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 235000009508 confectionery Nutrition 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】 技術分野 本発明はアンプ等に施す信号入力阻止回路に関する。[Detailed description of the invention] Technical field The present invention relates to a signal input blocking circuit applied to an amplifier or the like.
従来技術
電子回路網を構成するに当っては、あるアンプ回路の信
号入力を一時的に阻止する如く構成する要求が良くある
。好適なる一例を示せば。BACKGROUND OF THE INVENTION When configuring an electronic circuit network, there is often a need to configure it in such a way that signal input to a certain amplifier circuit is temporarily blocked. Let me give you a suitable example.
カセット装置のり−ド/ライト共用ヘッドに接続された
場合のリードアンプ自身である。該ヘッドに書込直流を
流すときにはり−ドアンフの入力にも過大信号が加わる
。よってリードアンプ自身の保獲からもまた書込中に疑
似リードテータ信号が出力されるという不都合を無くす
る意味からもリードアンプ回路への信号入力阻止を施す
必要がある。This is the read amplifier itself when connected to the read/write head of the cassette device. When a write direct current is applied to the head, an excessive signal is also added to the input of the amplifier. Therefore, it is necessary to prevent signal input to the read amplifier circuit, both from the read amplifier's own retention and from the standpoint of eliminating the inconvenience of outputting a pseudo read data signal during writing.
従来は、アンプ回路の入力に直列して大きく逆バイアス
のかけられたダイオードの回路を接続し。Conventionally, a highly reverse-biased diode circuit was connected in series with the input of the amplifier circuit.
かつバイアスを制御することによって書込時にはライト
信号がリードアンプ側に入力されないように遮断するも
のがある。しかしこの方法を実施するには、余分な素子
や回路網を附加する必要が、あり、廉価なる装置を構成
するにはコスト増の要因ともなっていた。There is also a device that blocks the write signal from being input to the read amplifier side during writing by controlling the bias. However, in order to implement this method, it is necessary to add extra elements and circuit networks, which also causes an increase in costs in order to construct an inexpensive device.
目的
本発明はかかる従来技術の不利益に鑑み為されたもので
らってその目的とする所似、簡単な構成でアンプ回路の
信号入力を阻止できる信号入力阻止回路を提供すること
にある。SUMMARY OF THE INVENTION The present invention has been devised in view of the disadvantages of the prior art, and it is therefore an object of the present invention to provide a signal input blocking circuit capable of blocking signal input to an amplifier circuit with a simple configuration.
実施例
以下1図面を参照して本発明の一実施例を詳細に説明す
る。第1図は一実施例の信号入力阻止回路を示す回路図
である。図において、lは後接するアンプ回路2への信
号の入力端子、 DI 、D2扛過大入力をクランプす
るための保護ダイオード。EXAMPLE An example of the present invention will be described in detail below with reference to one drawing. FIG. 1 is a circuit diagram showing a signal input blocking circuit according to one embodiment. In the figure, l is a signal input terminal to the subsequent amplifier circuit 2, and DI and D2 are protection diodes for clamping excessive input.
Cはカンプリングコンデンサである。アンプ回路2はオ
ペアンプ素子3を要素とし、増巾度を決定する抵抗R1
,R2と、アンプ出力の上Φ下限値をクランプするツェ
ナダイオードZ1.Z2と。C is a compling capacitor. The amplifier circuit 2 includes an operational amplifier element 3, and a resistor R1 that determines the degree of amplification.
, R2, and a Zener diode Z1. which clamps the upper and lower limits of the amplifier output. With Z2.
オペアンプ素子3の出力回路を保護する抵抗R3とから
成る。該アンプ回路2はトランジスタ等を組合せた適音
のアンプ回路でも良い。また、前記オペアンプ素子3の
正の電源端子7には+Vccが印′加され、また負の電
源−子8は保護ダイオード。and a resistor R3 that protects the output circuit of the operational amplifier element 3. The amplifier circuit 2 may be an amplifier circuit with suitable sound, which is a combination of transistors and the like. Further, +Vcc is applied to the positive power supply terminal 7 of the operational amplifier element 3, and the negative power supply terminal 8 is a protection diode.
DI 、D2との結合点9に接続されている。5はスイ
ッチ手段たるトランジスタでそのコレクタを結合点9に
接続し、エミッタを接地している。実施例では接地回路
が信号の共通路である。さらにベースはプルアップ抵抗
R4によって+Vcc に接続され、制御端子6に印
加される信号がHIでるるときはトランジスタ5を導通
させて前記結合点9にGND@供給し、またLOである
ときはGNDを遮断する。このようなトランジスタ5の
機能は、他にFET素子、C−MOSアナログスイッチ
素子、リレーの接点等で置き換えられる。It is connected to the connection point 9 with DI and D2. Reference numeral 5 denotes a transistor serving as a switching means, the collector of which is connected to the node 9, and the emitter of which is grounded. In the embodiment, the ground circuit is the common path for the signals. Further, the base is connected to +Vcc by a pull-up resistor R4, and when the signal applied to the control terminal 6 is HI, the transistor 5 is made conductive to supply GND to the connection point 9, and when it is LO, it is connected to GND. cut off. The function of the transistor 5 may be replaced by an FET element, a C-MOS analog switch element, a relay contact, or the like.
腹
4はアンプ回路2の出力を4kmする復調器で6.bか
かる構成においてその作用を以下に説明する。6. Anode 4 is a demodulator that outputs the output of amplifier circuit 2 by 4 km. b The operation of this configuration will be explained below.
図において9通常は制御端子6にHIレベルが印加され
ている。よってトランジスタ5は深く導通して結合点9
にtXは接地レベルを与える。この状態でオペアンプ3
は入力信号を増巾する動作領域にある。また入力の保護
ダイオード”Dl、D2も入力信号をクランプする目的
を十分に果たす。もし入力端子lに負の過大信号が印加
されるならトランジスタ5は逆I(イアスされる。この
ような場合はトランジスタ51C−MOSのア九ログス
イッチ素子で置き換えても良い。次にアンプ回路2の入
力信号を阻止したい場合は、制御端子6にLOレベルを
印加してトランジスタ5をカットオフし。In the figure, a HI level is normally applied to the control terminal 6 (9). Therefore, transistor 5 becomes deeply conductive and connects to node 9.
tX gives the ground level. In this state, operational amplifier 3
is in the operating region that amplifies the input signal. The input protection diodes Dl and D2 also serve the purpose of clamping the input signal. If a negative excessive signal is applied to the input terminal l, the transistor 5 is reversed I (earthed). In such a case, Transistor 51C-MOS may be replaced with an a9log switch element.Next, if it is desired to block the input signal to amplifier circuit 2, LO level is applied to control terminal 6 to cut off transistor 5.
オペアンプ素子3への信号の共通路tl−逅断遮断。Common path tl of the signal to the operational amplifier element 3 - cutoff.
以後、オペアンプ素子3の負の電源端子8の電位はほぼ
信号路の電位に追従するから、アンプ回路2の出力への
信号出力が阻止される。同時に、保護ダイオードD1.
−02はカップリングコンデンサCの充it−制限して
オペアンプ素子3の入力回路を保護する役目も果たす。Thereafter, since the potential of the negative power supply terminal 8 of the operational amplifier element 3 approximately follows the potential of the signal path, the signal output to the output of the amplifier circuit 2 is blocked. At the same time, protection diode D1.
-02 also serves to protect the input circuit of the operational amplifier element 3 by limiting the charging of the coupling capacitor C.
実施例において、トランジスタ5のエミッタが負の電源
に接続されたとしても同等の作用効果が得られることは
明白でおる。また本発明に係る信号入力阻止回路は実施
例にある如きアンプ回路2ヘの供給電源の極性に制限さ
れるものでもない。In the embodiment, it is clear that the same effect can be obtained even if the emitter of transistor 5 is connected to a negative power supply. Further, the signal input blocking circuit according to the present invention is not limited to the polarity of the power supplied to the amplifier circuit 2 as in the embodiment.
効果
以上述べた如く本発明によれば、簡単な構成で信号増巾
手段への信号入力を阻止するととができる。従来は、信
号路に直列に挿入したスイッチ手段によって信号入力を
阻止するから、異種の信号路が存在すれは信号路の数だ
けスイッチ手段を必要とする。しかるに本発明によれば
、信号の共通路を遮断するものであるから、単一スイッ
チ手段によって異種の信号を同時に阻止できるという効
果がるる。カセット装置やコンピュータ磁気テープ装び
等、多チャンネルの信号を扱う装置においては装置コス
トの低減にも大きな効果を発揮する。Effects As described above, according to the present invention, it is possible to block signal input to the signal amplification means with a simple configuration. Conventionally, signal input is blocked by switch means inserted in series in the signal path, so if different types of signal paths exist, the number of switch means equal to the number of signal paths is required. However, according to the present invention, since the common path of signals is blocked, different types of signals can be blocked simultaneously by a single switch means. In devices that handle multi-channel signals, such as cassette devices and computer magnetic tape devices, it is also highly effective in reducing device costs.
第1図はアンプの入力信号を阻止する−(?すを示す一
実施例の回路図である。
ここで。
l・・・信号の入力端子、2・・・アンプ回路、3・・
・オペアンプ菓子、4・・・復調器、5・・トランジス
タ。
6・・・制御端子、7・・・正の給電端子、8・・負の
給電端子、9・・・結合点でおる。
員願 Δ キャノン株式会社FIG. 1 is a circuit diagram of an embodiment showing a path for blocking an input signal to an amplifier. Here, l...signal input terminal, 2... amplifier circuit, 3...
- Op-amp candy, 4... demodulator, 5... transistor. 6...Control terminal, 7...Positive power supply terminal, 8...Negative power supply terminal, 9...Connection point. Membership Application Δ Canon Co., Ltd.
Claims (1)
を増巾するための増巾手段と、前記共通路と前記増巾手
段との間に直列接続され両者の間を開放、閉成に制御す
るスイッチ手段とから成り。 該スイッチ手段を開放に制御することにより前記増巾手
段の信号入力を阻止することを特徴とする信号入力阻止
回路。[Claims] 1. Amplifying means for amplifying a signal inputted via a signal path and a common path for the signals, and an amplifying means connected in series between the common path and the amplifying means; and switch means for controlling the opening and closing of the space. A signal input blocking circuit characterized in that signal input to the amplification means is blocked by controlling the switch means to open.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58029280A JPS59156008A (en) | 1983-02-25 | 1983-02-25 | Signal input blocking circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58029280A JPS59156008A (en) | 1983-02-25 | 1983-02-25 | Signal input blocking circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59156008A true JPS59156008A (en) | 1984-09-05 |
Family
ID=12271851
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58029280A Pending JPS59156008A (en) | 1983-02-25 | 1983-02-25 | Signal input blocking circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59156008A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002236429A (en) * | 2001-02-08 | 2002-08-23 | Matsushita Electric Ind Co Ltd | Fixing device |
-
1983
- 1983-02-25 JP JP58029280A patent/JPS59156008A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002236429A (en) * | 2001-02-08 | 2002-08-23 | Matsushita Electric Ind Co Ltd | Fixing device |
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