JPS59155701A - Method and device for thickness measurement of specimen - Google Patents
Method and device for thickness measurement of specimenInfo
- Publication number
- JPS59155701A JPS59155701A JP3046083A JP3046083A JPS59155701A JP S59155701 A JPS59155701 A JP S59155701A JP 3046083 A JP3046083 A JP 3046083A JP 3046083 A JP3046083 A JP 3046083A JP S59155701 A JPS59155701 A JP S59155701A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- sample
- thickness
- oscillation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
本発明は薄い試料の厚みを測定する方法と装置とに係る
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for measuring the thickness of thin samples.
非常に薄い試料の厚みを精度よく測定することは多くの
技術分野において要請されていることでおるが、これま
ではこの要請に十分に応じることはできなかった。例え
ば肉厚700々いし70μの圧電性フィルムの厚みを精
確に測定することはできなかった。このためその厚み変
化分を測定して圧電性フィルムの特性を決定することは
でき力かった。Accurately measuring the thickness of very thin samples is required in many technical fields, but until now it has not been possible to fully meet this demand. For example, it has not been possible to accurately measure the thickness of a piezoelectric film with a wall thickness of 700 μm to 70 μm. Therefore, it has been difficult to determine the properties of piezoelectric films by measuring changes in thickness.
本発明の目的は非常に薄い試料の厚さを精度よく測定す
る方法と装置とを提供することである。An object of the present invention is to provide a method and apparatus for accurately measuring the thickness of very thin samples.
この目的は本発明に従って一枚の平行板の中心に試料を
配置し、平行板の中心に対称な位置にそれぞれ対向して
配置した2組の電極の静電容量の逆数の和として試料の
厚みを測定することにより達成される。The purpose of this is to arrange the sample at the center of a parallel plate according to the present invention, and calculate the thickness of the sample as the sum of the reciprocals of the capacitance of two sets of electrodes placed symmetrically to the center of the parallel plate and facing each other. This is achieved by measuring the
添付図面を参照して本発明の詳細な説明する第7図を参
照する。両端に同じ面積の電極1.2.8.4を設けた
2枚の平行板5.6の中心に試料7を挾み、電極を対向
させて平行板5.6を上下に配置する。電極1.2の間
隔をdl、電極8.4の間隔をd2 そ1−て試料7
の厚みをdとすると、により与えられ、電極8.4の静
電容量C2は同求められる。Reference is made to FIG. 7, which provides a detailed description of the invention with reference to the accompanying drawings. The sample 7 is sandwiched between two parallel plates 5.6 having electrodes 1.2.8.4 of the same area on both ends, and the parallel plates 5.6 are arranged one above the other with the electrodes facing each other. The distance between electrodes 1.2 is dl, and the distance between electrodes 8.4 is d2.
Letting the thickness of the electrode 8.4 be d, the capacitance C2 of the electrode 8.4 can be calculated as follows.
第2図を参照する。電極1,2の静電容ic。See Figure 2. Electrostatic capacitance ic of electrodes 1 and 2.
を帰還素子に含む第1の演算回路9と電極8.4の静電
容量C2を帰還素子に含む第一の演算回路10とが発振
回路8に接続されている。第1と第一の演算回路9、l
Oの出力に加算回路11を接続し、第1と第一の演算回
路の出力電圧の和を演算する。この加算回路】1の出力
に位相検波回路12を接続し、発振回路8の発振信号と
qO度位相をずらした参照信号を移相回路21を介して
位相検波回路12に加え、それにより、発振信号と90
度位相をずらした点で第1と第一の演算回路の出力電圧
の和を位相検波する。これは各演算回路の帰還素子がコ
ンデンサであることを考慮して発振信号の測定位相と整
合した位相で検出するためである。A first arithmetic circuit 9 whose feedback element includes the capacitance C2 of the electrode 8.4 and a first arithmetic circuit 10 whose feedback element includes the capacitance C2 of the electrode 8.4 are connected to the oscillation circuit 8. First and first arithmetic circuits 9, l
An adder circuit 11 is connected to the output of O, and the sum of the output voltages of the first and first arithmetic circuits is calculated. A phase detection circuit 12 is connected to the output of the adder circuit 1, and a reference signal whose phase is shifted by q0 degrees from the oscillation signal of the oscillation circuit 8 is applied to the phase detection circuit 12 via the phase shift circuit 21, thereby detecting the oscillation. signal and 90
The sum of the output voltages of the first and first arithmetic circuits is phase-detected at a point where the phase is shifted by a degree. This is because the feedback element of each arithmetic circuit is a capacitor, and detection is performed with a phase that matches the measurement phase of the oscillation signal.
このように回路を構成することによって第1の/
演算回路9の出力電圧V、は、v、=vo−ユπ1ずR
,C。By configuring the circuit in this way, the output voltage V of the first arithmetic circuit 9 is: v,=vo-yuπ1zuR
,C.
(こ\で、■o は発振回路8の出力電圧、fは周波
数、R4は入力抵抗)となり、第一の演算回路10の出
力電圧■2 も、同様に
に比例しており、従って試料の厚みdを表わす信号が出
力端子1Bに得られる。(Here, ■o is the output voltage of the oscillation circuit 8, f is the frequency, and R4 is the input resistance.) The output voltage ■2 of the first arithmetic circuit 10 is also proportional to A signal representing the thickness d is obtained at the output terminal 1B.
第3図を参照する。第2図の回路と同じ構成要素には同
じ参照数字を付してあり、それらの要素から成る部分は
第2図の回路と同じ動作をするのでその説明は省略する
。第Ω図の回路が試料の厚みを測定するためのものであ
るのに対し、第3図の回路は試料の厚み変化分と試料の
厚みとを測定するものである。図に示すように、位相検
波回路12の出力に積分回路14、サンプル・ホールド
回路15を接続する。発振回路8と加算回路11との間
に第7又は第一演算回路と同様の構成の第3演算回路1
8を反転型乗算回路19と\もに接続し、前記のサンプ
ル・ホールド回路15の出力を反転回路19に接続して
反転型乗算回路19の利得を調整する。See Figure 3. Components that are the same as those in the circuit of FIG. 2 are designated by the same reference numerals, and since the portions consisting of these components operate in the same manner as the circuit of FIG. 2, their explanation will be omitted. While the circuit shown in Figure Ω is for measuring the thickness of the sample, the circuit shown in Figure 3 is for measuring the change in thickness of the sample and the thickness of the sample. As shown in the figure, an integrating circuit 14 and a sample/hold circuit 15 are connected to the output of the phase detection circuit 12. A third arithmetic circuit 1 having the same configuration as the seventh or first arithmetic circuit is provided between the oscillation circuit 8 and the addition circuit 11.
8 is also connected to the inverting multiplier circuit 19, and the output of the sample-and-hold circuit 15 is connected to the inverting circuit 19 to adjust the gain of the inverting multiplier circuit 19.
このように構成して、試料に例えば正弦的応力を加えて
その厚み変化を測定するには、その応力変化の周期でサ
ンプル・ホールド回路15により積分回路14に位相検
波回路12の出力を積分させる。との積分値を表わす信
号を反転型乗算回路19に加え、その反転出力を第7と
第一の演算回路の出力と\もに加算回路11に加える。With this configuration, in order to apply, for example, a sinusoidal stress to the sample and measure its thickness change, the sample/hold circuit 15 causes the integration circuit 14 to integrate the output of the phase detection circuit 12 at the period of the stress change. . A signal representing the integral value of .
これにより試料の厚みの瞬時値に相当する第1と第一の
演算回路の出力信号から試料の厚み(厚みの平均値)に
相当する信号を差引いた値、すなわち試料の厚み変化分
を表わす信号が第1の出力端子20に得られる。又、第
aの出力端子16には試料の厚みに相当する信号が得ら
れる。This results in a value obtained by subtracting a signal corresponding to the sample thickness (average thickness) from the output signals of the first and first arithmetic circuits corresponding to the instantaneous value of the sample thickness, that is, a signal representing the change in the sample thickness. is obtained at the first output terminal 20. Further, a signal corresponding to the thickness of the sample is obtained at the a-th output terminal 16.
すなわち、積分回路14、サンプル・ホールド回路15
、第3の演算回路18及び反転型乗算回路19は負帰還
系を構成しており、その負帰還作用により定常状態では
サンプル・ホールド回路ハ試料厚みに相当する信号を反
転型乗算回路19に継続的に加え、その結果位相検波回
路12の出力は試料の厚み変化分のみとなる。That is, the integrating circuit 14 and the sample/hold circuit 15
, the third arithmetic circuit 18 and the inverting multiplier circuit 19 constitute a negative feedback system, and due to the negative feedback effect, in a steady state, the sample/hold circuit continues to send a signal corresponding to the sample thickness to the inverting multiplier circuit 19. In addition, as a result, the output of the phase detection circuit 12 only corresponds to the change in the thickness of the sample.
圧電素子を試料としてその特性を測定するには二枚の平
行板5.6の中央に試料電極(図示せず)を設けて圧電
素子を挾み、これに正弦波電圧を印加することにより厚
み方向に正弦的に変化する応力を加えるようにすればよ
い。To measure the characteristics of a piezoelectric element as a sample, a sample electrode (not shown) is provided at the center of two parallel plates 5 and 6, the piezoelectric element is sandwiched between the two, and a sinusoidal voltage is applied to this to measure the thickness. What is necessary is to apply a stress that changes sinusoidally in the direction.
Claims (1)
に対称な位置にそれぞれ対向して配置した2組の電極の
静電容量の逆数の和として前記の試料の厚みを測定する
ことを%徴とする試料の厚み測定方法。 (21コ枚の平行板の中心に対称左位置に配置した2組
の電極の各々を帰還素子に含み、発振回路に接続された
第7と第一の演算回路;第1と第2の演算回路の出力に
接続され、これらの演算回路の出力電圧の和を演算する
加算回路;この加算回路の出力に接続され、加算回路の
出力信号を前記の発振回路からの発振信号と9θ度位相
の異なる参照信号で位相検波する回路を備え位相検波回
路の出力に前記の平行板の中心の試料の厚みに比例する
信号を発生することを特徴とする試料の厚み測定装置。 (3)2枚の平行板の中心に対称な位置に配置した2組
の電極の各々を帰還素子に含み、発振回路に接続された
第1と第一の演算回路;第1と第一の演算回路の出力に
接続され、これらの演算回路の出力電圧の和を演算する
加算回路;この加算回路の出力に接続され、加算回路の
出力信号を前記の発振回路からの発振信号と9θ度位相
の異なる参照信号で位相検波する回路;及びこの位相検
波回路出力と前記の加算回路の入力との間に接続されて
いる負帰還回路を含み、この負帰還回路は前記の位相検
波回路に接続された積分回路、この積分回路に接続され
たサンプル・ホールド回路、コンデンサを帰還素子に含
み前記の発振回路に接続された第3の演算回路及び、こ
の第3の演算回路と前記の加算回路の入力とに接続され
た反転型乗算回路を含み、この反転型乗算回路は前記の
サンプル・ホールド回路に接続されており、前記の位相
検波回路の出力に前記の平行板の中心の試料の厚み変化
に比例する信号を発生することを%徴とする試料の厚み
測定装置。[Claims] ■ A sample is placed at the center of two parallel plates, and the above value is calculated as the sum of the reciprocals of the capacitances of two sets of electrodes placed opposite each other at symmetrical positions about the center of the parallel plates. A method for measuring the thickness of a sample that uses the measurement of the thickness of the sample as a percentage. (Seventh and first arithmetic circuits each including two sets of electrodes placed symmetrically to the left of the center of 21 parallel plates in the feedback element and connected to the oscillation circuit; first and second arithmetic circuits) An adder circuit connected to the output of the circuit and calculates the sum of the output voltages of these arithmetic circuits; connected to the output of this adder circuit, the output signal of the adder circuit is connected to the oscillation signal from the oscillation circuit and has a phase difference of 9θ degrees. A sample thickness measuring device comprising a circuit for phase detection using different reference signals and generating a signal proportional to the thickness of the sample at the center of the parallel plates at the output of the phase detection circuit. First and first arithmetic circuits each including two sets of electrodes arranged symmetrically around the center of the parallel plate in the feedback element and connected to the oscillation circuit; connected to the outputs of the first and first arithmetic circuits; An adder circuit that calculates the sum of the output voltages of these arithmetic circuits; connected to the output of this adder circuit, the output signal of the adder circuit is phased with a reference signal that has a phase difference of 9θ degrees from the oscillation signal from the oscillation circuit. a detection circuit; and a negative feedback circuit connected between the output of this phase detection circuit and the input of the addition circuit, and this negative feedback circuit includes an integration circuit connected to the phase detection circuit; A sample and hold circuit connected to the circuit, a third arithmetic circuit including a capacitor as a feedback element and connected to the oscillation circuit, and an inverting circuit connected to the third arithmetic circuit and the input of the adder circuit. a type multiplier circuit, the inverting type multiplier circuit being connected to the sample and hold circuit, and generating a signal proportional to the thickness change of the sample at the center of the parallel plate at the output of the phase detection circuit. A sample thickness measuring device that uses this as a percentage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3046083A JPH0233081B2 (en) | 1983-02-25 | 1983-02-25 | SHIRYONOATSUMISOKUTEIHOHOTOSONOSOCHI |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3046083A JPH0233081B2 (en) | 1983-02-25 | 1983-02-25 | SHIRYONOATSUMISOKUTEIHOHOTOSONOSOCHI |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59155701A true JPS59155701A (en) | 1984-09-04 |
JPH0233081B2 JPH0233081B2 (en) | 1990-07-25 |
Family
ID=12304500
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3046083A Expired - Lifetime JPH0233081B2 (en) | 1983-02-25 | 1983-02-25 | SHIRYONOATSUMISOKUTEIHOHOTOSONOSOCHI |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0233081B2 (en) |
-
1983
- 1983-02-25 JP JP3046083A patent/JPH0233081B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0233081B2 (en) | 1990-07-25 |
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