JPS59152620A - Surface treatment of compound semiconductor - Google Patents
Surface treatment of compound semiconductorInfo
- Publication number
- JPS59152620A JPS59152620A JP2717683A JP2717683A JPS59152620A JP S59152620 A JPS59152620 A JP S59152620A JP 2717683 A JP2717683 A JP 2717683A JP 2717683 A JP2717683 A JP 2717683A JP S59152620 A JPS59152620 A JP S59152620A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- sputtering
- ion
- inp
- semiconductor crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02543—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は化合物半導体結晶の表面処理方法に関する。[Detailed description of the invention] The present invention relates to a method for surface treatment of compound semiconductor crystals.
方法として、当該半導体を高温に加熱する方法が従来一
般に用いられている。しかしこの方法は、表面に吸着し
てｉる炭化水素、酸素、水蒸気等の不純物を完全に除去
するには不十分でちることが、第１図（ａｔに示したオ
ージェ電子分光分析の結果より明らかである。この°よ
うな残留不純物のある化の不適により、オーミック性不
良、１瀧特性の劣化等の不都合を引き起こす。A commonly used method is to heat the semiconductor to a high temperature. However, the results of Auger electron spectroscopy shown in Figure 1 (at) show that this method is insufficient to completely remove impurities such as hydrocarbons, oxygen, and water vapor adsorbed on the surface. It is obvious that the presence of such residual impurities causes inconveniences such as poor ohmic properties and deterioration of 100% characteristics.
本発明の目的は、以上のような従来法の欠点を面の吸着
不純物を十分除去する方法を提供するこ本発明によれば
、薄膜ｌ槓に先んじて化合物半導体結晶表面を低速イオ
ンによシスバッタすること釦より化合物半導体結晶表面
上の吸着不純物を除去することが可能である。An object of the present invention is to provide a method for sufficiently removing adsorbed impurities on a surface to overcome the drawbacks of the conventional method. It is possible to remove adsorbed impurities on the surface of the compound semiconductor crystal using the button.
以下本発明について、ＩｎＰ単結晶ウェーハ表面を例に
と９図を参照しながら詳細に説゛明する。第２図は本発
明における一実施例を示す図である〇真空容器１中にお
かれたＩｎＰ単結晶ウェーハ２に対向して、イオンガン
３、およびオージェ電子分光分析のための電子銃４、分
析部であるＣＭＡ５が設置されている。ＩｎＰ単結晶ウ
ェーハ２線ホルダー６を通してアースされている。真空
容器１はイオンポンプ７如よル高真空に排気可能でδり
、Ａｒガスが適量導入できるような導入口８が付属して
いる。薄膜形成の為の付属装置および真空ゲージは特に
図示していない。ＩｎＰ単結晶ウェーハ２は真空容器ｌ
へ投入される直前に１化学エツチング等で表面処理を施
されておシ、結晶表面には空気中からの汚染物質である
炭化水素、酸素、水蒸純度のＡｒガスを１・〜５ｘＩＯ
−５Ｔｏｒｒ 導入して圧力を保つ。次にイオンガンを
加速電圧Ｉ ＫＶ、イオン電流１０ｍＡで約１０秒開動
作きせる。仁の過程で表面ニ吸着している成分はＡｒイ
オンのスパッタ作用り目はとんどの場合蒸発飛散し、清
浄なＩｎＰ表面が得られる。連れは５イオンガンの動作
と並行して動作させたオージェ分析のデータより明らか
であシ、第１図（ｂ）に示したようにＩｎＰ単結単結晶
ウェー面表面上いてＣおよび０が検出されなくなる。ス
パッタ時間は、吸着量に応じて最大１分間程度までは許
容され、これ以上になるとｌｎＰ単結晶ウェーハ表面に
損傷を、与えかねないので結晶性保存の観点よシ好まし
くない。スパッタ終了後は、再び真空容器１を１０−８
〜１０−ｇＴｏｒｒに排気した後、講
薄膜層積の過程に移ればよい。上記の条件はＩｎＰ単結
晶ウェーハの代わり忙Ｉ” １− Ｘ Ｇ” ｘＰ ｚ
−ｙＡｓ ｙ （０≦ｘ＜１．０＜ｙ＜１ ） で
あっても同様に使える。The present invention will be described in detail below with reference to FIG. 9, taking the surface of an InP single crystal wafer as an example. FIG. 2 is a diagram showing an embodiment of the present invention. An ion gun 3, an electron gun 4 for Auger electron spectroscopy, and an analysis CMA5, which is a department, is installed. It is grounded through the InP single crystal wafer two-wire holder 6. The vacuum container 1 can be evacuated to a high vacuum using an ion pump 7, and is provided with an inlet 8 through which an appropriate amount of Ar gas can be introduced. Accessories for thin film formation and vacuum gauges are not particularly shown. InP single crystal wafer 2 is placed in a vacuum container l
Immediately before being introduced into the crystal, the crystal surface is subjected to a surface treatment such as chemical etching, and the surface of the crystal is exposed to 1.~5xIO of Ar gas with a purity of hydrocarbons, oxygen, and water vapor, which are contaminants from the air.
-5 Torr is introduced and the pressure is maintained. Next, the ion gun was opened for about 10 seconds at an accelerating voltage of I KV and an ion current of 10 mA. In most cases, the components adsorbed on the surface during the cracking process evaporate and scatter due to the sputtering action of Ar ions, resulting in a clean InP surface. This is clear from the data of Auger analysis performed in parallel with the operation of the 5-ion gun, and as shown in Figure 1(b), C and 0 were detected on the surface of the InP single crystal wafer. It disappears. The sputtering time is permissible up to about 1 minute depending on the amount of adsorption, and if it is longer than this, it may damage the surface of the InP single crystal wafer, which is not preferable from the viewpoint of preserving crystallinity. After sputtering is completed, vacuum container 1 is heated to 10-8 again.
After evacuation to ~10-gTorr, it is sufficient to proceed to the process of laminating the thin film. The above conditions can be used instead of InP single crystal wafer.
-yAs y (0≦x<1.0<y<1) can be similarly used.
以上説明したように、化合物半導体結晶表面上低速イオ
ンによりスパッタし、しかる後に真空を破る過程を経る
ことなく薄膜堆積を行うことにより不純物を包含しない
半導体結晶−薄膜界面を形成することが可能である。As explained above, it is possible to form a semiconductor crystal-thin film interface that does not contain impurities by sputtering slow ions onto the surface of a compound semiconductor crystal and then depositing a thin film without going through the process of breaking the vacuum. .
第１図はスパッタ処理の有無による結晶表面汚染の程度
を比較したオージェ電子分光分析結果を示す図、第２図
は本発明の実施例における真空容器内の構成を示す図で
あるみ
図において、１・・・真空容器、２・・・化合物半導体
（ＩｎＰ ）単結晶ウェニハ、３・・・イオンガン、４
・・・電子銃、５・・・ＣＭＡ、６・・・ホルダー、７
．・、イオンポンプ、８・・・Ａｒガス導入口。
代理人弁理士内雄 鮒
第１図
０ θ２ ０．４ （１６°８
１オー シエ＠手 エネルキ”〜 （ＫｅＶ〕第Ｚ図FIG. 1 is a diagram showing the results of Auger electron spectroscopy comparing the degree of crystal surface contamination with and without sputtering treatment, and FIG. 2 is a diagram showing the configuration inside the vacuum container in an example of the present invention. 1... Vacuum container, 2... Compound semiconductor (InP) single crystal wafer, 3... Ion gun, 4
...Electron gun, 5...CMA, 6...Holder, 7
．．・Ion pump, 8...Ar gas inlet. Representative Patent Attorney Uchio Funa Figure 1 0 θ2 0.4 (16°8
1 O sie @ hand energy” ~ (KeV) Diagram Z
Claims (1)
スパッタすることを特徴とする化合物半導体結晶表面の
処理方法。 ２、 化合物半導体結晶としてＩｎＰまたは工ｎ１−ｘ
Ｇａｘｐ □−７ＡＳｙ （０≦ｘ ＜ １ ＋ ０
＜ ｙ≦１）単結晶を用い、イオンとしてＭを用いる仁
とを特徴とする特許請求の範囲第１項記載の表面処理方
法。 ３、 Ａｒイオンスパッタの条件を、Ａｒ Ｗ囲気圧
力ｌないし５ｘｌＯＴｏｒｒｓイオン加速電圧ＩＫＶ以
下、イオン電流１０ｍＡ以下、スパッタ時間１分以内に
設定する仁とを特徴とする特許請求の範囲第２項記載の
表面処理方法。[Scope of Claims] A method for treating the surface of a compound semiconductor crystal, which comprises performing ion sputtering on the surface of the compound semiconductor crystal within the vacuum vessel. 2. InP or InP as a compound semiconductor crystal
Gaxp □-7ASy (0≦x<1+0
<y≦1) The surface treatment method according to claim 1, characterized in that a single crystal is used and M is used as an ion. 3. The method according to claim 2, wherein the conditions for Ar ion sputtering are set to an Ar W ambient pressure of 1 to 5xlOTorrs, an ion acceleration voltage of IKV or less, an ion current of 10 mA or less, and a sputtering time of 1 minute or less. Surface treatment method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2717683A JPS59152620A (en) | 1983-02-21 | 1983-02-21 | Surface treatment of compound semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2717683A JPS59152620A (en) | 1983-02-21 | 1983-02-21 | Surface treatment of compound semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59152620A true JPS59152620A (en) | 1984-08-31 |
Family
ID=12213754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2717683A Pending JPS59152620A (en) | 1983-02-21 | 1983-02-21 | Surface treatment of compound semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59152620A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63166229A (en) * | 1986-12-27 | 1988-07-09 | Sumitomo Special Metals Co Ltd | Eliminating method for surface process denatured layer on insb semiconductor wafer |
| CN114042684A (en) * | 2022-01-12 | 2022-02-15 | 北京通美晶体技术股份有限公司 | Indium phosphide wafer and mixed cleaning process thereof |
-
1983
- 1983-02-21 JP JP2717683A patent/JPS59152620A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63166229A (en) * | 1986-12-27 | 1988-07-09 | Sumitomo Special Metals Co Ltd | Eliminating method for surface process denatured layer on insb semiconductor wafer |
| JPH0530300B2 (en) * | 1986-12-27 | 1993-05-07 | Sumitomo Spec Metals | |
| CN114042684A (en) * | 2022-01-12 | 2022-02-15 | 北京通美晶体技术股份有限公司 | Indium phosphide wafer and mixed cleaning process thereof |
| CN114042684B (en) * | 2022-01-12 | 2022-03-22 | 北京通美晶体技术股份有限公司 | Indium phosphide wafer and mixed cleaning process thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2674488B2 (en) | Dry etching chamber cleaning method | |
| EP0047002B1 (en) | Plasma etching apparatus | |
| JPH05315098A (en) | Process device | |
| JPH0555184A (en) | Cleaning method | |
| JPS59152620A (en) | Surface treatment of compound semiconductor | |
| JPH04336426A (en) | Manufacture of semiconductor device | |
| JPH09148255A (en) | Cleaning method in reaction container | |
| JPH05326477A (en) | Method for removal of halogen from semiconductor substrate surface | |
| JPH0239523A (en) | Method of forming film on semiconductor substrate | |
| JPH09263931A (en) | Vacuum treatment and vacuum treating device | |
| JP2558273B2 (en) | Surface cleaning method | |
| Thomas et al. | Lattice defects and surface properties of clean germanium | |
| JPH05198515A (en) | Semiconductor treatment device and semiconductor pretreatment device | |
| JPS59162200A (en) | Cleaning of surface of silicon substrate | |
| JPH07316809A (en) | Production of thin film of aluminum nitride | |
| Ramm et al. | Dry hydrogen plasma cleaning for local epitaxial growth | |
| JPH04199708A (en) | Plasma etching method | |
| JPH03211280A (en) | Method for degassing cvd device | |
| JP3446352B2 (en) | Vacuum evacuation method for vacuum pre-chamber | |
| JP2544129B2 (en) | Plasma processing device | |
| JPS6057634A (en) | Formation of surface protective film | |
| JPH0212914A (en) | Etching device | |
| JPH06158270A (en) | Production of high yield strength film for laser | |
| JPH1112722A (en) | Magnesium oxide for vacuum-deposition | |
| JPS643840B2 (en) |