JPS59152410A - Focus state display device of camera - Google Patents

Abstract

PURPOSE:To execute a display conforming to a present state of a focus state by performing a load averaging processing to a detecting data of a focus state by using a load which becomes the maximum at the present time point and decreases gradually to the past. CONSTITUTION:A defocus signal xn from a defocus quantity operating circuit 14 of a focus detecting circuit 2 is subjected to an averaging processing by an operating circuit 26, sent to a deciding circuit 28, and compared with reference levels Z1, Z2 stored in a storing circuit 42. When the defocus quantity is above the reference level, it is decided to be non-focusing, an L2 or L3 lamp of a display device 34 is flickered through a displaying circuit 32, and when the defocus quantity is below the reference level, it is decided to be a focused state, and a lamp L1 is turned on. At the time of averaging by the operating circuit 26, a load (1-alpha) is given to an average data yn-1 of the previous focus cycle time, a load alpha is given to the present data xn, and the average is taken. alpha is a larger value than (1-alpha). In this way, a display conforming to a present state of a focus state is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention periodically detects the focus state of a photographic lens.
Camera focus status display device that visually displays this:
This is related.

Conventional technology (as described below)
A camera has already been proposed in which a subject image is formed, the subject image is scanned, and the focus state of the photographic lens is periodically detected and displayed.

By the way, when detecting the focus state of the 'JfA Me lens using a focus detection device, the data on the detected focus state (defocus amount, etc.) contains errors due to various error factors, so it is necessary not to move the photographing lens. Even in this case, it varies depending on the focus detection operation. If such a focus state detection result is displayed as it is, the amount of actual change in the amount of defocus may be distorted while the photographer is moving the photographic lens from an out-of-focus state to an in-focus position. There is no particular problem as long as the amount of defocus is larger than the variation in the amount of defocus detected by the focus detection device. If the camera stops, the focus status display will change between in-focus and out-of-focus every cycle of the focus detection operation, making the display unsightly and confusing the photographer. This will present a situation.

A camera that detects the focus position using a focus detection device and automatically moves the photographing lens to the detected focus position.
In this case, focus detection is performed multiple times with the photographic lens stopped, and the results are averaged to determine the focus position, thereby processing errors in focus detection and focusing. Detection accuracy is improved.

However, with focus aid cameras that display the detected focus status and manually move the photographic lens to focus while looking at the display, it is actually necessary to stop the photographic lens and check the focus detection results multiple times. Cameras that require the user to perform operations such as displaying the average focus status, moving the photographing lens slightly according to the display, and then stopping the camera to average and display the focus detection results from multiple times are actually It cannot be established as a superior product.

In order to clarify the features of the present invention, a conventionally known example shown in FIG. 13 and subsequent figures will be specifically explained.

FIGS. 13A and 13B show the optical configuration of a light receiving section of a known focus detection device. In FIG. 13A, a large number of small lenses 11 to 7n are arranged at positions equivalent to the film plane with respect to the photographic lens L1, and CCD elements a1 and bi are arranged on the rear surface of each of these lenses. However, 1=
1. 2. ...n. Element groups al, a2...a
A light beam (represented by 81) that has passed through the lower part of the lens L1 in the drawing is incident on the element groups bl, b2 .・
...bn is the ray (S) that passed through the upper part of the lens L1.
(represented by 2) will enter. When in focus, the elements a1 and bl receive light from the same point on the subject, and when out of focus, the light from the same point on the subject does not enter the pair of elements a1 and bl, but the direction of the out-of-focus, change It shifts depending on the By detecting the direction and magnitude of this shift, the defocus pose including the direction can be determined.

J in Fig. 13 and below, element group a in Fig. 13 A, 1,
An example of a configuration in which a2...an and bl, b2...bn are arranged in a different format is shown. The lens L2 is a condenser that is equivalent to or near a film. Imaging lenses L3 and L4 are arranged on the rear surface of this lens L2 with the optical axis O as the axis of symmetry, and these lenses L3. Element groups al, a2...an(!:bJ,, b2...bn
are placed respectively.

FIG. 14 is a diagram showing an example of the configuration of the light receiving section of the COD in the device shown in FIG. It is designed to receive light that can be considered to reflect the intensity of the light incident on the whole. This photodiode PD is C
A trap is used to monitor the CD integration time. 15th
The figure is a circuit diagram showing an example of a COD integration time monitor circuit using a photodiode PD. When integrating the CCD, the capacitance component C of the photodiode PD is charged with a constant voltage E1 via the analog switch SW, and the CCD
Switch SW is made non-conductive at the same time as CD integration starts.

From this point on, the charge in the capacitive component C is discharged by the photocurrent of the photodiode PD, which is proportional to the intensity of the incident light, and the voltage level at the cathode of the photodiode PD begins to decrease. When this voltage level drops to a predetermined voltage E2, the output level of the comparator Com is inverted from 1 low to 1 high.After the switch SW is cut off, the output level of the comparator Com is
The time it takes for the output of the switch to reach the 6" high voltage level is used as the integration time of the CCD. The timing of turning off the switch SW, that is, the timing of starting the integration, is
It is designated by the program of the microcomputer MC, and its control signal is given via the CCD control block CB. When the microcomputer MC issues the timing to start integration, it starts a software-based timekeeping operation using an internal counter, and enters a state in which external interrupts are disabled. When the comparator Com outputs a "high" voltage signal, the c c D fill side] block CB outputs an interrupt request signal to the microcomputer MC in response to the "high" voltage signal. In response, the microcomputer lvj C The program jumps to the interrupt routine and stops the print count operation of the counter mentioned above.

Thus, on the counter! Information on the integration time of /'1ccD
The axis of force '+ is distorted. CU) ensured integration time J
If fJ is longer than the I activity corresponding to a predetermined low angle level, it can be determined that the subject is at a low angle of 181 degrees and cannot be brought into focus. Manotsu 1iif preserved integral time '+l'j,
corresponds to a predetermined high brightness level [(Mi 1-11
If the value becomes 1 or more than lJ'ヮ, this information is used to suppress the distortion in Table j-, so as to cause a subsequent distortion. When the microcomputer MC moves to the interrupt routine, it stores the integral data of C and CD in a predetermined R-AM area memory. The integrated data of the CCD is output to the CCD control block CD as an analog voltage in a time-series manner through a transmission line of 1 V from the CCD.

In the CCD control block CB, analog voltage signals from the CCD are sequentially converted into digital values. It is stored in the memory at a predetermined location in the RA 1tlI as converted digital integral data. The CCD control block CB continues to control the required CCD even after outputting the interrupt request pulse.
The number of pulses corresponding to the number of 7 dikes is outputted to the interrupt terminal at regular intervals. In synchronization with this pulse, the microcomputer IAC takes in the integral data from the CCD control block CB into the memory.

FIG. 16 is a flowchart v-1- showing an interrupt process for storing integral data of the apparatus shown in FIG. 13A.

From the CCD in FIG. 12, for example, elements al and bl.

a2. b2. ...The integral data can be output in the order of an and bn. In Figure 16, step knee l
Address Na of the memory that stores the integral data of element al of the CCD or pointer P T R1,: Seven strokes, C
CD; (memory address N1 for storing child BL integral data) or register 5AV for temporary pointer value saving
E is set, and the number of blame data N ('= 2
n) is sent to the counter D CN T. The step knee 2 detects the arrival of a pulse to the interrupt terminal, and when the pulse arrives, the step knee 3 applies it to the input/output port. Send integral data to accumulator. At step knee 4, the data of the accumulator is stored in the memory at the address indicated by the pointer PTR. In step I-5, the address of the memory where the next data is to be stored is specified. In this case, 1 is added to the contents of pointer PTR, and the result is
H, then pointers PT, R and register S
The contents of AVE can be exchanged with each other. Step ■−
At step 6, the counter D C1 dimension T is subtracted, and whether or not the result becomes 0 is checked at step knee 7. If it is not 0, return to step knee 1. In the above manner, until the contents of the counter D C1,I T become ○, the step number I' is repeated until the data is stored in the predetermined memory. The flow progresses.

As a result, as shown in FIG.
a, Na+1. Na+2. -・-・Na+n-1 has element a1. , a2. ,a3. ...an
The integral data of R'Alvi is stored respectively, and the deaf R'Alvi's a(, response Nb, NT:+4-1.N b4-
2. -...N b+n-1 has elements bl, b2.
-o3. ...bn integral data are stored respectively. When data storage is finished, the flow is step knee 8
The program moves to , sets the return address to the address of the next processing step, and returns.

The present invention provides a device that periodically detects and displays the focus state6.
When the photographic lens approaches the in-focus position, the display changes between in-focus and out-of-focus due to an error in detecting the focus state, creating an unsightly situation that confuses the photographer. In order to avoid such problems, the first objective is to stabilize the display by averaging the focus state detection data of each time the focus state is detected.

Furthermore, when simply averaging multiple pieces of data, the position of the photographing lens is different for each piece of data while the photographing lens is being moved toward the in-focus position, so the averaged data is This is the average value of the focus state at the midpoint of the movement range of the photographing lens during the time when the data was collected, and does not indicate the focus state at all current photographic lens positions.
The display of the focus state will be delayed from the current state, resulting in a situation where the photographing lens has passed the actual focus position by the time the focus is determined. A second purpose is to provide an averaging means that can display a state that is jointly with the current state without displaying a state that is delayed from the current state due to the delay.

Structure The present invention periodically detects the focus state, and uses a weighted average method to apply the maximum static suppression to the current data and smaller static suppression to the past data for multiple data including the current data. Data processing is performed on the state detection results to display the focus state, and the degree to which the current data is given more weight can be switched between while the photographing lens is in the out-of-focus position and after it has been determined that it has entered the in-focus range. To provide a camera focus state detection device that performs weighted averaging that places particular emphasis on current data while a photographic lens is in an out-of-focus region.

Embodiment An embodiment of the present invention is shown below in FIG. First, the embodiment shown in FIG. 1 will be briefly described. The part surrounded by dotted line 2 in the figure is a focus detection circuit, and this circuit detects the defocus amount and defocus direction of the photographic lens. This detection data Xn undergoes averaging processing in the arithmetic circuit 26 and is applied to the determination circuit 28. The determination circuit 28 determines whether the averaged defocus amount is within the focusing range by comparing it with a reference level. The reference level is stored in the constant storage circuit 42 in advance (Zl, 'Z2).

When the amount of defocus is equal to or higher than the reference level, the determination circuit 28 determines that the focus is out of focus, sends a signal to the display circuit 32, controls the display device 34 in the viewfinder, and displays the triangular mark L2 or L depending on the direction of defocus. -Turn on one of 3. If the defocus amount is below the reference level, judgment circuit 2
8 is determined to be in focus and the circle mark L1 in the display device 34 is displayed.
lights up. As mentioned earlier, the focus detection circuit 2 periodically performs focus detection, and outputs defocus amount data xn for each detection cycle.

Here, the subscript n appended to X represents the detection cycle number. FIG. 2 shows an example of changes in the output XQ of the focus detection circuit 2. In cycle numbers 1 to 3, the photographic lens is moved toward the in-focus position. After cycle number 3, the photographic lens is assumed to have entered the in-focus range and is not moved. However, the focus detection signal changes every cycle as shown in the figure, and until now, with the let This is where the meaning of averaging comes into play. Averaging is performed using current data and past data for each cycle of the focus detection operation, and various averaging methods are possible. In this embodiment, an antistatic value 1-α is given to the average value 7n-1 obtained during the previous focus detection cycle, an antistatic α is given to the current data xn, and the average of xn and yn-1 is calculated. 7
1'1-axn+(1-a)yn-1 is the current average value y
A weighted average method is used to determine n. Two values of α, α1 and α2−α1+Δ2, are preset in the constant storage circuit, and the selection circuit 40 selects α1. Either α2 is selected and used. The meaning of α is that if it is 1, the average calculation will not be performed if only the current data is used, and α−〇 means that the previous data will be used as the average value.Generally speaking, α is a value in the range from 0 to 1, and the larger this value is, the more weight is given to the current data. In the case of this embodiment, two α's such as α2>αworking are prepared, and until the determination circuit 28 makes a determination of focus, α2 (the larger one is used to perform a weighted average that emphasizes the current data). When a focus judgment is made, α1 is used to average the current and past data with uniform static suppression7.In other words, the judgment circuit 28 outputs a binary code signal of 00 when in focus. ．When out of focus, front focus is 0
After outputting the pin 100 determination signal, the memory circuit 36 stores the previous determination signal and controls the selection operation of the selection circuit 40 in the current calculation. I will explain in detail later how to change the value of α before and after the focus judgment, but while the photographer is moving the photographic lens toward focus, past data is viewed equally with the current data. From this time, the judgment result is
Because the response to changes in the focus state and state will be delayed due to past data with a larger amount of focus deviation, select the dog @ value α2 as α, and take a picture after the focus is determined. Since the lens hardly moves, in addition to the current data, past zones are also given a certain weight when viewing. This completes the general description of the embodiment shown in FIG. 1, and next, each embodiment shown in FIG. 1 and the following will be described in detail.

The embodiment according to the present invention shown in FIG. 1 is used in a single-lens reflex camera, and the light receiving part of the focus detection element 2 is disposed at the bottom of a mirror box, and the subject light flux passing through the photographing lens via a well-known optical system is The received light flux is guided to the light receiving section. As the focus detection element 2, for example, a known device known as a TC top manufactured by Haneuni i is used. This focus detection device has a line sensor 4 in the light receiving section, and this line sensor is composed of a photodetector element COD of charge type f type, and transfers and outputs the charge accumulated in the integral time, and also outputs this output. A predetermined algorithm calculation process is performed on the defocus amount and its direction to be detected. This detection operation is performed repeatedly, and the defocus signal is output intermittently.

Further, the focus detection element 2 is provided with an AGC circuit that outputs a signal proportional to the total amount of integrated charge every moment, and automatically stops the integration operation when this signal reaches a predetermined level. In other words, the product of the illuminance of the light-receiving surface and the integration time is kept constant, and the average level of the output is always constant, so that it is convenient for the subsequent signal processing system, regardless of the subject brightness. .

The defocus-oak calculation algorithm is disclosed in, for example, Japanese Patent Application Laid-Open No. 5'7-45510 or US Pat. No. 4,333.
A detailed explanation is given in No. 007, and this can be used as the first example. Subject contrast Cn
For example, in H44-1, a value calculated based on the following formula is used.

Cnt= Z l cti −aq゛, (E1 Here, al represents the output of element a1. The contents of this equation are as follows: It is the sum of the absolute values of the differences, and the higher the contrast of the subject, the larger the total value Cn is as a general rule.For a flat subject with no contrast, the total value is Vio.The licensor 4 is a control circuit. The AGC circuit is included in the control circuit 6. When the transfer operation is started, the line sensor 4 outputs a voltage signal corresponding to the charge accumulated by each photodiode. is output from the sample hold circuit 8 and the licensor 4.
Temporarily holds the voltage signal from. AD conversion circuit 10
'ri converts the analog voltage held in the sample hold circuit 8 into a digital value. The converted digital values are sequentially stored in the storage circuit 12 at addresses designated as children. The information stored in the memory circuit 12 is stored in the arithmetic circuit 14
A predetermined algorithm calculation process is performed to calculate the defocus amount and its direction, and the defocus amount and its direction are outputted to the output line 20 as a digital defocus signal.

The useless arithmetic circuit 16 calculates a signal indicating the contrast strength of the subject image in the portion received by the line sensor 4 from the information in the memory circuit 12. Furthermore, the timer circuit 18 clocks and outputs the charge accumulation time in the line sensor 4 for each detection cycle.Next, the configuration of the display stabilization circuit 22 will be explained. The arithmetic circuit 26 in which the output line 20 of the focus detection element 2 is connected to the input line 24 has the following equation, where Xn is the defocus signal from the nth detection cycle, and yn is the arithmetic output of the arithmetic circuit 26 for this signal Xn. Performs the operation indicated by the formula.

yll = αx n + (1-a) yn-1-・
-(1,)(]) In the equation, α is either 1 or 1/2, as described below. yn-I is the defocus signal Xn from the (n-1)th detection cycle.
This is the calculation output of the calculation circuit 26 for −1.

In addition, for the defocus signal XI of the first detection cycle, the above α is initialized to α-1 to become y knee Xl, and Xl is output as yl as it is to the next stage determination circuit 28 and storage circuit 30. given to. The arithmetic circuit 26 calculates the average of the defocus signal Xn of the latest detection cycle and the signal yn-1 obtained from the previous defocus signals when α-1/2 is obtained as described later. . Here, by expanding equation (1) in the case of α-1/2, equation (2) is obtained.

yn=, Xn+original (2Xn-1+'=yn-2)→X
, n+j, Kn-1 +-H? +n-2 +・----+
fiXn411... (2) As is clear from equation (2), the output of the arithmetic circuit 26 gives the most weight to the latest data, and the weight decreases as the data goes back to the past. This method calculates the weighted average value of multiple pieces of data. This is because, as described above, there are variations in the defocus signals of each detection cycle for the same distance, so the error is reduced by taking the average value of a plurality of defocus signals. At this time, the reason why the most weight is given to the latest data and the influence of past data is lightened is as follows.

If the photographing lens is stationary relative to the film plane and the subject is still at a certain distance from the camera, then
When calculating the average value of a plurality of defocus signals, it is not necessary to weight each one. However, in reality, the photographic lens is manually moved toward the in-focus position, and the distance between the subject and camera can still change, so it is difficult to compare the latest defocus signal with the past defocus signal. If equal weight is given, error factors other than the above-mentioned variations will have a large influence. For this reason, past data should be given less weight.

The determination circuit 28 compares the defocus signal yn from the arithmetic circuit 26 with a predetermined focus threshold 2, determines in-focus/out-of-focus, and calculates the result an as shown in Table 1 ((2-bit It is output as a signal. Depending on this output, any of the display light emitting diodes L1, L2, and L3 is turned on.
This is an 1-bit signal output from the 1-bit signal that indicates whether the contrast of the subject has reached a predetermined level (C).If the contrast has reached the predetermined level (C), it is assumed that focus detection is impossible, and the determination circuit 28 outputs -1'' as the output an.

The display circuit 32, which receives the signal an, is a light emitting diode L of a known display means 34 provided in the viewfinder.
l, L2. ．． Drive L3.

The storage circuit 36 temporarily stores the signal dn until the output yn1 of the arithmetic circuit 26 for the output Xn-1-1 of the (n+1)th detection cycle is given to the determination circuit 28, and selects the stored value. It is applied to circuits 40, 44, 48 and arithmetic circuit 54. The selection circuit 40 determines, in response to the output dn~1 of the determination circuit 28 for the ri-1st defocus signal Xn-1, before executing the calculation of the first equation using the nth defocus signal Xn. Two constants α1-1. are stored in the constant storage circuit 38. α2=1/2(7) Either one is selected and input to the arithmetic circuit 26. signal dn −
When 1 is 00'' indicating focus, the constant α2-1/2 is selected, and weighted average processing is performed on defocus signals traced back from the latest defocus signal Xn expressed by the second equation. In other cases, the constant α1-1 is selected, and the arithmetic circuit 26 directly outputs the input Xn as the output yn.In the out-of-focus area, the photographing lens is moved toward the in-focus area, and the Since the position is changed, if you average multiple defocus signals from the past obtained in such a case, even if the lens has actually reached the in-focus area, the average processing calculation result will be based on past defocus signals. Averaging processing is not performed because the responsiveness of focus judgment deteriorates and becomes unstable due to the data at the time of focus.

Next, the constant storage circuit 42 and the selection circuit 44 constitute a first hysteresis circuit 45 that provides hysteresis characteristics to the determination circuit 28, and the constant storage circuit 42 and the selection circuit 44 constitute a first hysteresis circuit 45 that provides a hysteresis characteristic to the determination circuit 28, and the constant storage circuit 42 and the selection circuit 44 constitute a first hysteresis circuit 45 that provides a hysteresis characteristic to the determination circuit 28. One of the two constants 21 and 22 stored in the constant storage circuit 42 is input to the determination circuit 28 as a focus determination reference value. two constants 21 and 22
When the photographing lens is initially in the out-of-focus area and is moved toward the in-focus area, the smaller constant 21 is used as the focus judgment reference value, and the in-focus value corresponding to constant 21 is used as the focus judgment reference value. If it is determined that the photographing lens is in the focus area, the larger constant 22 is prepared as the focus judgment reference value for the defocus signal of the next detection cycle, that is, the focus area is initially set narrow. By adjusting the focus with that narrow area as a target and expanding the in-focus area once the target area is reached, it is possible to prevent the display from fluctuating rapidly due to variations in the defocus signal.

The values of the constants zi and zz are determined experimentally to appropriate values.

Note that when the constant 22 is given to the judgment circuit 28, the difference ΔZ between the two may be added to the constant 21, or when the constant Zl is given, ΔZ is subtracted from the constant 22. Moyoi constant storage circuit 462 and selection circuit 48
is the second circuit for providing hysteresis characteristics to the judgment circuit 50.
A hysterin circuit 49 is configured. The determination circuit 50 is
Determine whether the contrast signal from the focus detection element 2 has reached a predetermined level. Generally speaking, the reliability of the defocus signal tends to decrease as the contrast of the object in the area corresponding to the focus detection area decreases. However, if contrast does not exist, defocus cannot be detected. Therefore, the contrast judgment level is set in advance, and if the contrast signal does not reach the judgment level,
It is assumed that defocus detection is impossible, and the judgment circuit 28 outputs 11'' indicating that it cannot be detected.Similarly to the contrast circuit 28, a hysteresis characteristic is given to stabilize the judgment result. The constants 01, 02'/'i stored in the constant storage circuit 46 are the first and second constants, respectively.
The constant 02 is set to be larger than 01 by a predetermined value C. These constants CI and C2 are determined practically.

In each case, the constants of each IYJ stage circuit are selected according to the output an-1 of the Ki-1 circuit 36. , most recent detection) - cycle defocus (judgment result c of the determination circuit 28 for the output of the previous detection cycle with respect to K Xn and contrast signal Cn)
The constant selected by in-1 is used, and the arithmetic circuit 26,
A predetermined operation will be executed in the determination circuit 2, 8.50.Next, the constant storage circuit 52, the arithmetic circuit 54, and the counter
When the photographic lens is in the focus position, the circuit consisting of
This constitutes a main part of a detection number limiting circuit which prevents the number of detection operations per unit time from exceeding a predetermined number of times. The licensor 4 accumulates charge for an integration time of 40 μsec to 400 msec or more depending on the intensity of the incident light. On the other hand, it takes, for example, 5 minutes to perform predetermined data processing from the end of the integration, output the focus judgment result, and perform the display operation.
A constant data processing time of about 0 msec is required. CCD
If we limit the integration time to a maximum of 400 ms, the period of - detection cycles, that is, the sum of the integration time and data processing time, will be approximately 50 ms to 450 ms. Therefore, the period of the detection cycle will be 50 ms. In this case, the detection operation is performed 20 times per second. However, when such a detection operation is performed in the case of focusing, as described above, since there are variations in each defocus signal, the focus display element L
1 and the out-of-focus display element L2 or L3 may alternately light up in a dizzying manner, which confuses the photographer. Therefore, in the case of focusing, the period of the detection cycle is limited to the shortest period, for example, about 100 msec, to alleviate display flicker. In this way, when the integration time τn is set to a predetermined constant time τQ, for example, 5
If it is shorter than 0 msec, the difference Δτ (-τ〇-τn)
Delay the detection cycle and start the next detection cycle. Returning to the circuit diagram, the constant storage circuit 52 stores the take corresponding to τ0 for a certain period of time. The arithmetic circuit 54 receives the signal τn from the timer circuit 18 at the end of the integration, and outputs the signal Δτn shown in Table 2 to the counter 56 in accordance with the signal dn-1 from the storage circuit 36.

The second table counter 56 displays the judgment result dn-1 in the judgment circuit 28 on the display circuit 32. After being outputted to the storage circuit 36 and subjected to display and storage operations, Δτn is counted based on a count start signal given from the system control circuit 58, and after the time count is finished, a time count end signal is output. Here, the counter 56 is configured to immediately output a timing end signal in response to the counting start signal when Δτn-Q· is given.

The system control circuit 58 instructs the focus detection element 2 to start a new detection cycle in response to the clock end signal. Note that when the camera is out of focus, limiting the number of detections will degrade the response speed from the out-of-focus display state to the in-focus display state, so the number of detections is not limited as described above.

Next, the operation of the circuit shown in FIG. 1 will be explained. When the photographer presses the detection switch 60, the system control circuit 5 immediately initializes the output of the memory circuit 36 to "01" and instructs the focus detection element 2 to start integrating the COD. When the initial settings of the memory circuit 36 are made, the display stabilization circuit 22
Each part is defined as shown in Table 3.

Now, the integration of the CCD starts. After a period of time corresponding to the illuminance of the light receiving surface of the CCD has elapsed, the integration operation is stopped, and then the integration of the CCD starts.
The charges accumulated in each cell of D are transferred and inputted as a voltage signal to the sample and hold circuit 8, where they are sequentially converted into digital values by the fi A-D conversion circuit 10 and stored in the storage circuit 12. Then, after a required number of calculations have been completed, a defocus signal and a contrast signal are output from the calculation circuits 14 and 16. On the other hand, the timer circuit 18 is reset when the CCD starts integrating, counts clock pulses during the integration period, and outputs the count value τn when the integration is stopped.

Note that the CCD integration is performed over a predetermined period of time (for example, 200
m seconds), the system control circuit 58 is equipped with a function that forcibly commands the integration to stop after a certain period of time without waiting for a stop command from the AGC. It is desirable to prevent this from taking a long time.

Now, when the defocus signal X1 and the contrast signal Ctl from the first detection cycle are output, since the arithmetic circuit 26 has been initialized to α-1, the output y1
The i′1fxl is outputted as a signal and applied to the determination circuit 28 and the storage circuit 30.

On the other hand, the determination circuit 50 compares the initially set contrast comparison reference value C1 and the contrast signal Ctl,
The result is given to the judgment circuit 2. If the contrast of the rock object is sufficient and C1 (Ctl), the judgment circuit 2
On the day, the focus judgment reference value Z1 and the defocus signal y l (
= x 1 ) and outputs the comparison result cll, which is applied to the display circuit 32 and the storage circuit 36. Now, if the front pin is detected as a result of the determination, the display element L2 is lit. The photographer should follow this display.
Turn the distance ring and move the photographic lens toward the in-focus position.

By the way, the arithmetic circuit 5414 gives its output Δτn to the counter 56, but in the first detection cycle, Δτn is
Since τn=o, the counter 56 immediately sends back a count end signal in response to the count start signal from the system control circuit 58. Thus, the focus detection element 21 enters the second detection cycle. Subsequently, system control circuit 58 causes storage circuits 30 and 36 to output the stored contents.

That is, the output of the memory circuit 30 is y n −1= 71 (=
xl), and the output of the memory circuit 36 is dn-1=d
It becomes 1. Therefore, the constants from each selection circuit 40, 44.4Q selected by the signal dn-1 are K as shown in Table 4.

Table 4 Next, as in the case of the first detection cycle, the focus detection element 2 sends the integration time +=+ data τ2 to the calculation circuit 54 after the completion of the integration of C'CD, and also calculates the defocus amount Xn. It is calculated and output to the arithmetic circuit 26. Arithmetic circuit 54
outputs the output Δτn (-Δτ2) as shown in Table 2 above in response to the signal dn-1 (-d l ).

On the other hand, the arithmetic circuit 26 calculates y2−αX2 based on equation (1).
+(1-α)yl... Perform the calculation shown in (3). If the first focus is here, α
-1/2 is used, and the average of the first and second defocus amounts is taken as the output y2. If the first time is out of focus, α-1 is used, and the second defocus amount X2 is output as the output y2 regardless of the previous y'l. The determination circuit 28 compares the signal y2 and the output 2 of the selection circuit 44 and outputs the determination result d2 as shown in Table 1. In this case, the first result from the previous time is in focus,
As Z=Z2, a focus zone that is slightly wider than zl used in the previous time is set, and if the previous time was out of focus, a narrower focus zone is subsequently set.

When the determination result a2 is obtained, it is transmitted to the display circuit 32 and the second detection result is displayed. Then, the counter 56 starts the operation at Δτ2 at B', and when the clock end 1 word is issued, the system control circuit 58 starts the third detection cycle. For the third and subsequent whistle detection cycles, the same process as the second one described above is repeated.

The system control circuit 58Vi constantly monitors the state of the switch 60, and when the switch 60 is opened, the power supply circuit is automatically turned off, for example, 15 seconds after that point, and the series of focus detection operations is completed. Good too. To summarize the above operation, if the previous judgment result is out of focus, the current defocus amount
It is determined whether or not the focus zone is within a narrow focus zone, and the next detection cycle begins. If the previous judgment result is in focus, average processing is performed with the previous defocus equivalent amount yn-1, and as a result, it is determined whether yn is in the in-focus zone set for the wide eye. Determine whether At this time, a limit is placed on the length of the detection cycle for relatively bright objects.

By the way, when the amount of differential debris Xn is determined in accordance with a predetermined algorithm in the focus detection element, a sufficiently reliable answer may not be obtained depending on the output value of each cell of the CCD. For example, the contrast of a fracture object is low;
In cases where there is almost no difference between the outputs of each cell of the CCD, or in cases where the field of view is too dark and the amount of charge stored in the CCD is small, the focus detection element will be limited in its detection ability. Since it is stored with a skewer, in such a case, the judgment circuit 5
In response to the output of 0, the determination circuit 28 outputs a signal indicating that detection is not possible, and in response, display elements L2 and L3 blink to display a warning. In this case, the determination circuit 50j
However, a hysteresis characteristic is added to prevent the warning display from changing rapidly with the normal display. Now tube m
The second judgment result dm is undetectable and there is no j (dm≠”1
1”), that is, when there is sufficient contrast, the second (
After the m+1)th detection cycle, the contrast is O.
A low judgment level C1 is given to the judgment circuit 50 as a contrast judgment reference value, and compared with the contrast signal Ctm+1 from the focus detection device 2.

If the m-th judgment result dm is undetectable (
clm-"11"), that is, when a warning is displayed due to insufficient contrast, the contrast signal Ctm-1-1 of the (m+1)th detection cycle [for the determination circuit 50
is given a higher judgment level C2. FIG. 3 shows such a hysteresis effect at an undetectable level. By providing the determination circuit 50 with hysteresis characteristics in this manner, instability of the display near the warning display determination level can be reduced.

FIG. 4 is a configuration diagram showing an embodiment in which the in-focus state display device of the present invention is configured using a microcomputer (for example, Intel 80C48). This device is
A CCD block 62 arranged at the bottom of the mirror pocket surface of the single-lens reflex camera 61, a COD control block 64 including an A-D conversion circuit that controls the CCD and digitizes the output of the CCD, and a microcomputer 66 connected thereto. AF switch 0 for instructing focus detection, a buzzer 68 for emitting a short sound when in focus, and a light emitting diode Ll for indicating the focus state.
L2. It is composed of L3 etc.

The following flags and counters are reserved in the RAM area of the microcomputer 66.

The flag FPF is set to "l" () at the beginning of the first detection cycle, and is cleared from the second detection cycle.The 7 rung LcF is determined to be below the contrast level or a predetermined level. When it is set, “1” is set,
When it is determined that the brightness of the subject is above a predetermined level, it is cleared to O''.Flag LLF is set to "1" when it is determined that the subject brightness is below a predetermined level. It is set to "1" to indicate a pin, and is cleared to 0- to indicate a back pin. Flag 5FYn is a weighted average processed tare signal. If the 4-1 cass signal is a front pin, it becomes ``1'', and if it is a rear pin, the trap is cleared to ``O''.Flag ■
1+F n is set to 6" when the defocus signal Yn of Seishin is judged to be in the focus zone, and cleared to "O" when it is judged to be far from the focus zone. Flag FFn-1 holds the previous focus judgment result, and when the previous judgment result is in focus, it is set to “1”.
When out of focus, it is cleared to 1rO.

The flag BF is used in the process of controlling the warning display operation to display a warning by blinking the display light emitting diode when it is semi-determined that the focus cannot be detected due to insufficient contrast.

It is used to determine the maximum integration time of the counters Tn, Ts, and ccD, and consists of a total of 2 bytes consisting of the upper 1 byte l-Tn and the lower 1 byte Ts. At the same time as the CCD starts integrating, this counter starts subtracting from the predetermined value of 1.

The time required to count the total number of set distributions corresponds to the maximum integration time. The counter BCTR is used as a timer to define the lighting time and extinguishing time when controlling the light emitting diodes L2 and L3 to blink as a warning display, and is set at the initialization step. A timer counter TCTRd is equipped with a microcomputer as a counter, and uses the microcomputer's internal clock pulse as an input signal, and allows the timekeeping operation to be freely programmed by controlling the gate provided at the input section with a timer counter control command. I can do it. This internal clock nocleus is a divided version of the microcomputer's basic man cycle. Further, when the count value of the timer counter TCTR overflows, the timer flag TF is automatically set to "1". This timer flag TF can be used to test its contents depending on the program, and the program can be conditionally branched depending on the test result. Note that when this timer flag T'F is tested by a program, it is automatically cleared to "o" at that point. This flag TF is used to control the display operation as described later.

FIG. 5 is a flowchart 1 showing the overall operation flow of the focus display device shown in FIG. Tostenov S-2 turning on the power switch (not shown) in Figure 5
The following initialization settings are automatically performed by the microcomputer software.

16 Set the program counter to “O” 2. External interrupt disabled state 1 (Yes 3. Block input to timer counter T CTR 4.
- Clear the timer flag TF to 0''.The next initialization setting is performed by software.

1. CCD1'! 1. Supply of the clock to the control block 64 is started. 2. The initial value Con of the counter BCTRK is set.

Next, in step S-3, the light emitting diodes L, L2 . At the same time, the timer flag TF is cleared to 60'' to prevent the display subroutine described below from functioning, thereby blocking the input clock pulses to the timer counters TC and TR. Subsequently, in step S-4, the flag FPF is set to "1" indicating that it is the first detection cycle.The step knob S-5 checks whether the AF switch 60 is on. If it is off, move the steering knobs S'-4 and S-5 and press the AF switch 6.
When 0 is turned on, it enters a standby state. AF switch 60
When CCD is turned on, the command to start the integration of CCD at step S-6 is CCD;+jlh wholesale block 6.
4, and when the 411th minute of the CCD is completed, the integral data is taken into a predetermined memory of the microcomputer in step S-'79 in response to an interrupt request signal generated in the CCD control block 64. .

Note that the detailed contents of step S-6 will be described later based on the flowchart of FIG. In step S-8, the output data of the CCD is processed by a predetermined algorithm to determine the defocus angle including direction and contrast. Since this arithmetic processing requires zero time, for example, about 50 milliseconds, several display subroutines (Fig. 9) are inserted in the middle of the arithmetic processing routine to prevent the warning flashing display described later from becoming unnatural. . Step S-
At step S9, the on/off state of the A1-□ slot 1 notch 60 is checked again, and if it is off, the process returns to step S-3. If it is on, the process moves to step S-10, where the contrast determined in step S-8 is compared with a predetermined value C. A flowchart showing the contents of steps 5-10 is shown in step 6. Referring to this flowchart, in the case of the first detection cycle FPF=1, C=CI ((C2) is used, and if this is exceeded, the low contrast flank LIC
F:・If it has been reset to 0" and has not exceeded it, press L.
CT and l are counted as "1". From the second detection, the reference value C is selected between CI and C2 as described above based on the comparison result of the first detection cycle. C1 is used when the low contrast flag that indicates the previous result is "○" and the contrast is determined to be the era name, and on the other hand, "1" is set as a contrast flag. When it is determined that the contrast is insufficient, C2 is used.The result of comparison with the reference value thus selected is set in the low contrast flag LCF.At this time, the previous content is lost.

Next, in step 5-11, a calculation is performed to obtain a weighted average Yn of the latest defocus amount Xn and the past defocus amount Y n -1. In the following step 5-12, it is determined whether the defocus amount Yn calculated in step 5-11 is within a predetermined focusing zone. A flowchart showing the contents of this step is shown in FIG. At step 11-1 in FIG. 7, it is checked by checking the shift flag FPF whether the flow in question is the first detection cycle. Step 1 for the first detection cycle
1-3', and the narrower value z1 is prepared as the focus determination value Z. In the second detection cycle or after, the flow moves to step 11-2 and the focus flag FF is set.
The previous focus determination result is checked starting from n. The previous focusing result is step 11-7 or! l-1:l'l-8
When in focus, it is “1”, and when out of focus, it is O”
has been cleared. Now, as a result of checking the 9 in-focus flag FFn, if the result is out of focus, the process moves to step 11-3, and if the result is poor focus, the process moves to step 11-4. Step 11-
4, the wider value Z2 is prepared as the focus determination value 2. In step 11-5, the focus flag F
The contents of Fn are set to another focus flag FFn-1. This step is not related to the current focus determination operation, and the set information is used in a later step.

Next, in step 11-6, it is determined whether the defocus amount Yn is within the prepared focus determination value Z.

If the image is in focus, the process moves to step 11-7, and the focus flag FFn is set to "1," and if the image is out of focus, the process moves to step 11-8, where the focus flag FFn is cleared to ``O''. As described above, based on the previous focus judgment result, the judgment value Z for the current focus judgment is selected and the hysteresis characteristic is given.Next, in step 5-13, in step S-10, the low contrast flag LCF is selected. The content set in is checked, and if the contrast is not low, proceed to the next step 5-14.Step 5-1
At step 4, the value of the focus flag FFn is checked, and if it is the focus flag, the process proceeds to the next stage knob 5=15. In step 5-15, it is determined whether the flow is the first detection cycle by checking the Y flag FPF. In the case of the first detection cycle, the process moves to step 5-18, and the light emitting diode indicating focus is turned on. If it is not the first detection cycle, the process moves to step 5-16 and the focus flag IFFn-,1 is checked to check the previous focus determination and result. If it is out of focus, move to step 5-18. If the previous result of the split was out of focus and the current result is in focus, an in-focus display is made in step 5-18. Continuing from the previous time, this time as well, if the object is in focus, fd is applied, and if the brightness is high, the process moves to step S-1'7 and the period of the detection cycle is extended. Now, step 5
Following step 5-18, in step 5-19, the light emitting diode L''- indicating the focus is lit and a buzzer sounds for a short time (for example, about 0.2 seconds) to audibly indicate that the focus zone has been entered. In the following step 5-20, it is checked whether the AF' switch 60 is turned on.

If it has been inserted, the process moves to step 5-22, and if it has not, the process moves to step 5-21.

In step 5-21, the lit light emitting diodes are turned off. In step 5-22, the flag Fll is cleared to O. Following this step, the flow moves to step S-6. Next, COD integration step S-6
The flowchart of FIG. 8 showing the contents will be explained. In step 6-1, a signal instructing the start of integration is output, and then in step 6-2, the low luminance flag LLF is set to “
○". In step 6-3, the microcomputer is set to a state where it can accept interrupts, and the process moves to the next step 6-4. In step 6-4, the pulse meter corresponding to the predetermined maximum integration time of 400 msec is The value is the counter Ta,
Set to T7. As mentioned above, this counter consists of 2 bytes, upper Tn and lower Tl.
The count value T n max corresponding to the longest integration time of rnK is entered, and OF'FnA (= 2
56) is set.

In step 6-5, it is checked whether the AP switch 60 is turned on. If the counter is turned on, the contents of the counter will be incremented by $, but the CCD integration will be completed before the contents of the counter become 0 by the end of the count, and an interrupt pulse indicating this will be sent to the CCD control. When the block 64 occurs, the counter subtraction operation is stopped and the process moves to the interrupt processing routine. If no interrupt occurs, the CCD integration is forcibly terminated at the end of the time measurement of 400111 seconds, the low luminance flag LLF is set to "1", and the process moves to the next step IC. Step 6-6 to 6-
The flow up to 10 is a subtraction count of the counter. In step 6-6, one count is subtracted from the content of the lower counter Tl, and in step 6-7, it is checked whether the content of the counter 'rz has become O or not. If it is not 0, return to step 6-5. In this way, the counter T/
The process cycles between steps 6-5 and 6-7 until becomes O. When the counter T/ becomes 0, step 6-8VC described below
Then, in step 6-9, the upper counter Tn is decremented. In step 6-10, the counter Tn
It is checked whether or not it has become 0. If it is not 0, the process returns to step 6-5. Thus, the flow cycles between steps 6-5 and 6-1O until no interrupt occurs and the key current T/', Tn becomes 0. The time required for this round is approximately 400 msec. In step 6-11, the CCD
The integration is forcibly terminated, and then in step 6-12 the low brightness flag L'lLC is set to 1''.

This means that the subject brightness is low. In any case, when the integration is completed, an interrupt occurs, and the microcomputer 66 enters step S-7 of interrupt processing to take in the integrated data. However, in step 6-5, AF
When it is detected that the switch 60 is in the off state, the microphone-computer 66 enters the interrupt disabled state, and the COD
Stop the integration and return to step S-3.

Step 6-8 is a subroutine for display operations, the flowchart of which is shown in FIG. In this figure, in step D-1, it is checked whether 1" has been set in the timer flag TF, and if it is O", the process returns. The display operation subroutine is used only when the timer 7 rung TF is set to 1". When the timer flag TE is checked, it is automatically cleared to 0". In step D-2, the low contrast flag LCF is checked, and if the brightness is not low, the focus state display routine moves to step knob D-3. In step D-3, the latest focus judgment result is set. The focus flag INFn is checked, and if the focus is in focus, the process moves to step D-4 in which the light emitting diode L1 is turned on.

If the focus is out of focus, the sign flag S F Y n indicating the direction out of focus is checked in step D-5, and the light emitting diode L2 or L3 is turned on depending on whether the focus is on the front or the back.

If the contrast is low, the process moves to steps D to 8, which is a flow Vi warning display routine, and a check is made to see if the blinking flag BF is present. If this flag is “1”, step D
-13, the counter BCTR is decremented, and then, in step D-14, a check is made to see if the color BCTR has reached O. Since the counter BCTR is set to the constant Non at the slap S-2 of initialization, the flow continuously passes through the NorL rotation step D-13 during which the low contrast state continues.

During this time, the light emitting diodes L2 and L3 are turned on simultaneously in step D-15. In step D-13, counter BC
When it is detected that TR has become O, )p- proceeds to steps D-16 and D-1'7, clears the flag BF, and sets the constant Noff in the counter BCTR.

Here, the constant Nof is the light emitting diode L2. It specifies the period during which L3 is turned off, for example, 71 N v
3 times the value of n: (determined. In other words, the ratio of the lighting and extinguishing periods of the light emitting diodes L2 and L3 at the time of warning is set to 1:3. However, it is not necessary to limit the ratio to this ratio. Now, the flag BP is cleared and the state is “○”, the flow goes to step D
You will be guided towards -9. In the case where the low contrast state continues, step D-9 is successively passed through step D-9 a constant Noff times. During this time, the light emitting diode L2. L3
is turned off.

When it is detected in step D-10 that the counter BCTR has become O, in step D-11, the blinking flag BP is
is set to 1", and the constant Non is set to the counter BCTR in D-12. Therefore, in the next step D-8, the flow is directed to step D-13. In this way, as a warning display. Flashing lighting control of the light emitting diodes L2 and L3 is performed.Furthermore, the flashing flag BF
may be set to 4 cents at the step of initialization S-2, but there is no problem whether it is initially set or cleared.

The operation of the display subroutine will be explained based on the above explanation of the display subroutine and the entire flowchart in the 5th episode. In step S-3, the timer counter TCTR is set to a stopped state and the timer flag TF is initialized to O''. Since the reverse display LE and D are also OFF, even if the flow jumps to the display subroutine in the first detection cycle, the T in step D-1 in FIG.
Since it is F-"O", an immediate return is required so that no display operation is performed and the light emitting diode remains off. At the end of the first detection cycle, clock input to the timer counter TCTR is permitted in step 5-22 of FIG. TCT
R generates an overflow pulse and sets the timer flag TF.
Since the value is set to 1'', if it is TF-1'' at the time of jumping to the display subroutine, the focus adjustment state or warning display as described above is displayed and the process returns. Note that when the display operation is performed with TF="l", the timer flag TF is cleared to O, so the flow jumps to the display subroutine when the next overflow pulse is set to "1". However, no display operation is performed.

FIG. 10 is a flowchart showing the contents of step S-11 of the weighted average calculation shown in FIG.

At step F-0 in FIG. 10, the value held by memo +)Yn is transferred to memo 1JYfi-1 as the previous average value in preparation for the processing after step F-1. In step F-1, the flag FPF is checked and if "1" indicating the first detection cycle is set, the flow moves to step F-2, where the flag IFFn is checked. At this point, the flag FFn retains the previous focus determination result. If the previous judgment result is out of focus, the flow jumps to step F-15, and if it is in focus, the flow goes to step F-3.b6゜In this step F-3, the defocus amount yn used in the previous focus judgment is -1 sign i
p njJ Bin 1 (Whether it is from 1 or from the rear pin side is checked in flag SFY. At this point in time, flag IFFn with the contents of flag SFY
Similarly, the previous judgment result is retained. Note that even if the defocus signal is in the in-focus zone, it still has a polarity that indicates front focus or back focus. 5FY=“1” in Ste Knob F-3, i.e. front pin 11)
If so, the flow moves to step F-4, where the sign of the defocus signal
FX is checked, and if 5FX="1", that is, the front pin, the flow moves to step F-5, and if 5FX="0", that is, the rear pin, the flow moves to step F-13. On the other hand,
If the flag F-3 is S F Y - "O", that is, the rear pin side, the flow moves to step F-7, and the sign of defocus tXn from the current detection cycle is flagged as in step F-4. 5FX-1'', that is, the front pin, the flow moves to step F-8, and when SFX="0'', that is, the rear pin, the flow moves to step F'-5. That is, F-3, F-4,'
The process in each step of F-7 refers to the previous defocus direction SFY and the current defocus direction SFX to check whether the defocus direction has changed or not. If so, step F-5
If there is a change, the process moves to step F-8. If the direction of the teff residue does not change, proceed to step F.
-5, the previous average value yn-1 and the current value Xn
Only -1 and Xn are added together, and the total value is divided by 2 in step F-6 to obtain a new average value Yn. In this case, there is no change in the defocus direction, so there is no need to rewrite the flag SFY. If the previous and current defocus directions are different, averaging processing is performed in consideration of the sign from step F-8 to steps F and -6. First, in step F-8, it is checked whether or not Xn is equal to O. If they are equal, the process moves to step F-13, where the previous average value Yn-1 is set as the previous and current total value Yn, and then step Carrier lag Cy is 0” with F-14
is cleared and then divided by 2 in step F-6. Since there is no average this time, there is no need to rewrite the flag SPY.

If X n -1,0 at step knob F-8, the absolute value Y of the average value of the previous defocus is determined in step F-9.
Subtract the absolute value of the current defocus amount Xn (=lxnl) from n-1 (= 1yn-11), and use the result as Yn
Then, in step F, 10, carry flag cy
The magnitude relationship between Yn-1 and Xn is determined based on the following. This is because the focus direction has changed between the previous time and this time, so it is not possible to calculate the average value by adding only the defocus sizes of the previous time and this time.

Note that subtraction is actually performed by taking the complement of the subtracted number and performing an addition operation. If the carry flag Y is set as a result of the addition, the result of the addition is used as is as the result of the subtraction. In this case, the flow is step F-1
4 to step F-6. Carry flag C
If Y is cleared, it corresponds to the result of complement ratio subtraction of the result of addition. However, since the sign is inverted only at this time, the previous content of the sign flag SFY is inverted in step F-12. Next, in step F-6, a shift average value is determined. As described above, when the previous determination result is in focus, a weight of 1/2 is given to the defocus amount Xn of the current detection cycle, and the average value with the past defocus amount is calculated.

As a result, the weighted average yn, that is, Yn and SF
'Y is obtained and provided to the focus determination chamber in step 5-12. On the other hand, if the first mouth detection cycle or the previous judgment result is out of focus, step P-'15
．． In F-16, the current measured value Xn, that is, the absolute value
n and the defocus direction SFX are respectively transferred to the memory Yn and the flag SFX as the current processed value yn, and are used for determining the focus of the steering knob 5-12.

To summarize the above explanation, the first detection cycle or IJ: 1) If the determination result of i+ times is out of focus, the current measurement value is adopted as the 11th one without JJ1i tun average total average. Focus judgment (1) If the 11th judgment result indicates that the object is in focus, average processing is performed taking into account the sign between the previous average processing value yn-1 and the current measurement value Xn. . Since averaging processing is not performed in the out-of-focus state 74, it is very useful to be able to display the latest measurement take from time to time without being dragged down by past measurement values. The time delay in display transition from focus to focus can be minimized, and in the focused state, the instability of the display of measurement values every time can be improved. If the averaging process is repeated, the weight of the past measured value Yn-i (i is an integer) relative to the latest average value Yn will decrease in proportion to 2iVC, and so-called weighted averaging process will be performed. This weighted average processing is effective when the positional conditions between the camera and the subject change due to movement of the subject, camera shake, etc.

FIG. 11 shows a routine 70 for suppressing display flicker at high brightness in step S-1'7 of FIG.
-It's Chigito. As mentioned above, when the subject is of high brightness, the COD integration time is short, several + milliseconds or less.
The number of detection cycles per unit time "39" increases. Therefore, the number of display operations per unit time also increases, making it easier for the display to flicker.
The integration time τn of D is the predetermined time τo (-50 msec)
If it becomes shorter than , a waiting time Δτ is created and the detection cycle time is extended by the waiting time to limit the increase in the number of detection cycles per υ unit time and suppress display flickering. It is. In FIG. 11, if the low brightness flag LLF is checked in step H-1 and the subject is low brightness and 1" is set, the flow changes to step 5-22.
If the image quality has been reduced, the process moves to step H-2 to proceed with flicker suppression processing. Note that the information on the COD integration time is obtained by the integration routine shown in Figure 8. In FIG. 8, during the CCD integration, the counter Tn is decremented, and when the COD integration ends midway, the flow jumps to the interrupt routine in response to an interrupt request signal from the CCD control block 64, and the counter Tn decrement the count. The operation is aborted. Therefore, the counter Tn has a value T that is obtained by subtracting the count value during integration from the initial value T n maX.
n remains. Here, with reference to the graph of FIG. 12, consider an integral time variation τO in which the waiting time is exactly O, and let the remainder of the counter Tn corresponding to this integral time τOK be TO.

The value of TO is determined by considering the operability of the camera, the degree of suppression of display flicker, and display responsiveness to determine the shortest detection cycle, and then subtracting the calculation time from that value. .

In step H-2, the value To that corresponds to τ0 is subtracted from the count value remainder Tn stored in the counter Tn, and the result ΔT is stored anew in the counter TnK.

In step H-3, check whether the subtraction result is O or not.
If so, the process goes to step 5-22, and if not O, then in the next step H-4, the carry variable cy generated as a result of the subtraction (complement addition) in step H=2 is checked.

The calculation result in step H-2 is negative ΔT (O that is c
If y=O, this means no waiting time is required and the flow jumps to step 5-22.

When Cy=1, that is, the subtraction result in step H-2 is positive Δ
T) In the case of O, the detection time cycle is too short, and the count value ΔT newly stored in the counter Tn in step H2 is set as one cycle of the loop from step H-5 to H-10 and back to H-5. The system waits for a considerable amount of time, that is, the period of ΔT, while checking the state of the A'F switch 60 and controlling the display.

In step H-5, the state of the AP switch 60 is checked, and if it is off, the process moves to step S-3. If it is on, the process moves to step H-6 and the counter Tl is decremented by 1. Next, the process moves to step H-'7, and it is checked whether the contents of the counter T/ have reached O or not. If it is not 0, the process returns to step H-5, and the flow cycles between steps H-5 and H-'7 until Tl=Q.

When Tl=01, the process moves to step H-8. Step H
-8 is the subroutine for display shown in FIG. 9 i'rC.

When the process moves to step H-9 following step H-8, the content Tn of the counter Tn is decremented, and step H-1
0, it is checked whether T n = 0 or not.

If T n≠0, the flow returns to step H-5. In this way, the flow continues between steps H-5 and H-10 until T a = 0.
The tour will include a tour between 10 and 10.

When T n = O in step H-10, the flow moves to step 5-22. As above, the 11th
In the routine shown in the figure, a count value ΔT corresponding to the waiting time is obtained, and the time required to subtract this count value until it becomes O is applied to the waiting time.

Effects According to the present invention, since the focus state V)' data obtained periodically is averaged and displayed, the photographic lens is at the in-focus position &f''.
This eliminates the instability of the display caused by the difference in focus state data detected every cycle of the focus state detection operation even when the camera is close to the camera. While the out-of-focus area is known, data closer to the current time is given more weight, so the response of the average value of the detection data of the focus state to a change in the position of the photographing lens is faster, and therefore the photographer can check the focus state. When operating the photographic lens with IJ-coded on the display, the response of the display itself may be delayed and the photographic lens may have passed the correct focus position before the in-focus display is displayed. Occurrence can also be prevented.

[Brief explanation of the drawing]

Figure 1 is a block diagram □ showing an embodiment of the present invention, Figure 2 is a graph showing an example of changes in the output of the focus detection circuit, and Figure 3 is a graph showing changes in the display caused by this output. , FIG. 4 is a block diagram showing another embodiment of the present invention, FIGS. 5 to 11 are flowcharts showing the operation of the same embodiment, and FIG. 12 is a graph explaining the setting of the integration time in focus detection. , FIGS. 13A and 13B are side views showing optical interception of the light receiving section of a known focus detection device, FIG. 14 is a plan view showing the configuration of the light receiving section of a CCD, and FIG. 15 is an integral time monitoring circuit of an ecD. An example circuit diagram, Figure 16'/''i
The flowchart of the interrupt operation, FIG. 17, is a memory map of areas related to the above operation in the RAM. Agent Hiroshi Mai, Patent Attorney Figure 7 Figure 13 Figure f3 B Figure 14

Claims (1)

[Claims] A hint state detection device that detects the defocus direction and defocus amount of the photographing lens and outputs a defocus signal, and compares the defocus amount with a reference level to determine in-focus or out-of-focus. Depending on the determination circuit and the display device that displays the result of this determination, the amount of defocus in the current focus state detection operation cycle and the defocus amount in one or more past focus state detection operation cycles that follow this time are determined. A calculation means for performing a weighted average calculation based on the number of layers in which the amount of light changes from this time to the past is provided, and a control means for switching the number of layers to be applied to the data according to the determination of focus/out-of-focus is provided. The weighted average value of the defocus amount obtained by the calculation means is given to the judgment circuit, and when the previous judgment result is out of focus, the data in the current detection cycle is used more than when the judgment result is in focus. A camera focus state display device characterized in that the number of layers to be emphasized is switched.