JPS59152408A - Focus detecting device of camera - Google Patents

Abstract

PURPOSE:To stabilize a focus detection unsuitable signal being in the vicinity of a focus detection possible level by preparing two kinds of high and low reference levels, comparing a detecting signal of a contrast with the low reference level, and comparing it with the high reference level in case said signal is below the reference level. CONSTITUTION:A light of an object is made incident to a CCD4 of a focus detecting device 2 through a photographic lens, its output is processed, and a defocus signal xn and a contrast signal cn are outputted to a display stabilizing circuit 22 from a defocus quantity arithmetic circuit 14 and a contrast arithmetic circuit, respectively. The signal cn is sent to a deciding circuit 50, a low level signal c1 in two high and low reference signals c1, c2 prepared in a constant storing circuit 46 is selected, sent to a deciding circuit 28 and compared with the cn. When the cn is lower than the c1, a detection impossible signal is sent to a display means 34 through a displaying circuit 32, and lamps L2, L3 turn on and off. By the following cycle, the signal cn is compared with the high level reference signal c2, and a focus detection impossible signal is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a focus detection device for a camera, and more particularly to a focus detection device suitable for detecting focus depending on the brightness distribution state in an object image.

[Prior Art] When determining focus depending on the luminance distribution of a subject image in some way, it becomes difficult to determine focus when the contrast of the subject is insufficient.

and compare it with a predetermined reference level.
If the contrast of the subject does not reach the standard level,
Cameras designed to provide warning displays have been proposed.

In such a camera (in this case, if the contrast of the subject is exactly the same as the above predetermined reference level, even if the same camera is used for focusing, it will be divided by the change in the subject itself). Alternatively, there may be various error factors such as noise in the contrast detection circuit (therefore, the detected contrast may fluctuate above or below the reference level, resulting in an unstable state where a warning is issued or stopped, and the camera is in an unstable state). This causes a situation that confuses the user.In order to understand this point more concretely, an example shown in FIG. 13 will be explained.

FIG. 13A and FIG. 1:3B show the optical configuration of a light receiving section of a known focus detection device. FIG. 13A (Here, a large number of small lenses 11 to ln are arranged at a distance equal to +d1i from the film surface with respect to the photographing lens L1, and a CCD element a1゜l is placed on the rear surface of each lens.) has been done. Then, i=1, 2, . . . n. Element group al, a
2... ant A light beam (represented by Sl) that has passed through the lower part of the lens L1 in the drawing enters the element ibl,
A light beam (representatively represented by S2) that has passed through the upper part of the lens L] enters b2...bn. , when in focus, elements ai and bl receive light from the same point on the subject, and when out of focus, light from the same point on the subject enters the pair of elements a1 and bl. Depending on the situation. By detecting the direction and magnitude of this shift, the amount of defocus including the direction of focus can be determined.

FIG. 13B shows the element group al in FIG. 13A.

A2...a I] and bl, b2...bn are arranged in different formats. The lens L2 is a condenser lens arranged at or near the film equivalent.

An imaging lens L; 3° L4 is arranged on the rear surface of this lens L2 with the optical axis 0 as the axis of symmetry, and these lenses (L3. In the imaging direction of L4, element groups al, a2=an, bl, b2,・・b
n are arranged respectively.

14M is a diagram showing an example of the configuration of the light receiving section of the CCD in the device of FIG. 13B, in which a photodiode PD is arranged near the element group in addition to the element groups al, a2...20]. Element B) - This photodiode PD is designed to receive a ray of light that is considered to reflect the intensity of the light incident on the entire device. This photodiode PD is used to monitor the integration time of the CCD. CC used
FIG. 3 is a circuit diagram showing an example of an integration time monitor circuit of D. C
Integration 1 of CD...: Then, the capacitance component C of the photodiode PD (this is charged with a constant voltage E1 via the analog switch SW, and the switch SW is turned off at the same time as the integration of the CCU starts. From this point on, the capacitance component C
The charging ru load of the photodiode I is proportional to the incident light intensity.
) I) is discharged by the photocurrent of photodiode PD
The 'TLL pressure of the cathode levels and goes down. this"
When the voltage level drops to a predetermined positive pressure E2, the output level of the comparator % Om reverses from ``low'' to ``high''.
The output of li:f is used as the integration time of the CCD until it reaches a "high" voltage level (i:f).

The switch SW is in the cut-off state [The timing of rubbing, that is, the timing of starting integration, is specified by the program of the microcomputer MC, and its control signal is given via the CCD control block CB. When the microcomputer MC issues a timing to start integration, it starts a software-based time counting operation using an internal counter and enters a state in which external interrupts are disabled. Comparator Com?
When the high voltage signal is output, the CCD control block CB outputs an interrupt request signal to the microcomputer MC in response to the high voltage signal. In response to this, the program of the microcomputer MC jumps to the interrupt routine and stops the counting operation of the above-mentioned counter. In this way, information about the integration time of the CCD is secured in the counter. Using this secured integration time, if this is longer than the time corresponding to a predetermined low brightness level, it can be determined that the subject has low brightness and focus detection is impossible. In addition, the secured integration time information is used as a warning to suppress display flickering, as will be described later, when the time becomes shorter than the time corresponding to a predetermined high brightness level. When the microcomputer MC moves to the interrupt mill, it stores the CCD integral take into a predetermined RAM area. The integrated data of CCV) is output to the CCD control block CB as an analog voltage in a time-series manner in synchronization with the transfer port from CC1). CCI);
In the regular block CB, analog voltage signals from the CCD are sequentially converted into dental values. The converted Tenkle value is stored in memory at a predetermined location in the RAM as an integral take. After outputting the interrupt request pulse, the CCD I control block CB continues to output the required number of CCD multiplier pulses in one cycle to the interrupt terminal. In synchronization with this pulse, the microcomputer MC takes in the integral take from the CCD control block CB into the memory.

FIG. 16 is a flowchart showing an interrupt process for storing integral data in the apparatus of FIG. 13A. From the 12th L CCD, for example, elements al and bl.

a2. Integral data is output in the order of b2..."+1+bn. In FIG. 16, step I-1 is CCL.
) is placed in the pointer PTR, and the address Nb of the memory that stores the integral take of the element b1 in the CCD is placed in the pointer value temporary save register 5AVE.
The counter product theta number N (=2n) is set in the counter DCNT. In step I-2, the arrival of a pulse to the interrupt terminal 2 is detected, and when the pulse arrives, in step J-3, the integral data given to the input/output port is sent to the accumulator. In steps 1 to 4, the memory of the accumulator is stored for one month at the address indicated by the pointer P'FR.

In step I-5, the address of the memory where the next succeeding data is to be stored is specified. In this case, 1 is added to the contents of pointer PTR, the result is stored in pointer PTR, and then the contents of pointer PTR and reno star 5AVE are swapped with each other.

Step I-('i is subtracted from the counter DCNT, and step I-7 determines whether the result is 0 or not.
will be checked. If not υ, return to step i-1. The contents of the counter DCNT are O as in μm.
Steps 1-1 and 1 of E-7 until the take is stored in the specified memory (3)
70- goes around the heart. As shown in Figure 17, the address of the RA is N a.

Na-! -1. Na+2 ・-' Na-n-1 has element al.

2121 iT 3...211] are each stored in A1, and RAM addresses Nb and N
b-], Nb-←2...N b-n-1: this (
Ma element bl, b2. l) 3...1] Each of the 5 molecules of 1) is stored. The flow that ends when the data is processed moves to steps 1-81, sets the return address to the address of the next succeeding processing step, and returns idly.

Purpose The present invention aims to solve the problem of detecting γ′ζ (
The present invention provides a device for stabilizing the display.

111Jr l The present invention detects the contrast of the subject, compares it with a predetermined reference level, and sets the reference level to a circuit that determines whether or not to issue a warning. The focus detection and contrast detection operations are repeated periodically, and judgments are usually made using the lower reference level (contrast or smaller), and in one operation cycle, the contrast of the subject is lower than the reference level. When it is determined that
In the next operation cycle, the higher reference level is used for determination. In this way (rubbing), the judgment operation will have hysteresis characteristics.

Considering the case where the blade edge is close to the reference level of the lower contrast of the subject, the lower reference level is normally used, so the subject contrast is determined to be above the reference level and a warning is issued. If the contrast detection fluctuates due to various reasons and the subject contrast is determined to be below the above standard, the contrast will be switched to the standard in the next operation cycle, so the detected contrast will be low. Even if the reference level exceeds 10,000, the warning will continue as long as the detected contrast does not exceed the reference level. (If it is determined to be below the level, the higher base yarn level will be used in the next operation.) In the next operation cycle, the lower reference level will be applied.

Note that the present invention is applicable when focus detection is performed depending on the brightness distribution of the subject, but when it is said that it depends on brightness or cloth, focus detection is performed by performing analytical calculations on the brightness distribution function of one image. In addition to methods that perform this, Shio's method also includes a method that detects whether or not the focus is correct based on whether or not the contrast of the subject light at the front and back of the camera's film-equivalent surface matches.

Actual example: The embodiment described below is a focus detection system that detects whether the focus is in focus and also detects the defocus direction and defocus amount of the photographic lens depending on whether the contrast is large or small. This is a focus detection device having a means for instructing the direction of defocusing and displaying the focus within the camera pointing. A level corresponding to the contrast I, which is the limit at which focus detection can be carried out reliably, is prepared in advance as the lower reference level mentioned above, and a warning is displayed in the viewfinder when the contrast of the subject falls below this reference level. In this embodiment, a hysteresis characteristic is also provided for the in-focus display to eliminate various causes of display instability at the time of focusing.

In order to understand the concept of the present invention, an outline of the embodiment shown in FIG. 1 will be explained. The portion surrounded by dotted line 2 receives the light transmitted through the photographing lens, operates periodically, and periodically outputs the defocus amount and direction of the photographic lens as well as a contrast signal.

The contrast signal Cn is sent to the determination circuit 50. One of the two high and low reference levels C1 and C1+ΔC prepared in advance in the constant storage circuit 46 is selected by the selection circuit 48 and applied to the determination circuit 50. Judgment circuit 50
The determination result is sent to the focus state determination circuit 28. The determination circuit 28 controls the display circuit 32 in accordance with the focus state, and displays information regarding the focus state on the display means 34 in the finer window. When a determination signal (contrast is low) is sent from the determination circuit 50 that is lower than the reference level, the determination circuit 28 outputs an undetectable signal (a) and displays a triangular mark on the display means (this indicates that the apex is in the direction of the photographic lens). L2 and L3 flash at the same time (instructing the distance name and the direction in which the ring should be turned) to display a warning that the focus cannot be detected.At the same time, this signal indicating that the focus cannot be detected (as will be explained later, this signal 142 hint) (coded as "11") is stored in the circuit 36 described below.

The selection circuit 48 is operated by this notation. That is, when an undetectable signal is not stored in the storage circuit 36 (in the first operation cycle, the reference level C1 is selected and applied to the determination circuit 50, and when an undetectable signal is stored, the next operation cycle Then select C2.

7 in FIG. 2 is a diagram for explaining the operation of the above-mentioned embodiment. The number on the horizontal axis is the output order number of the contrast signal output from the focus detection element 2, and the vertical 4 itl yn indicates the defocus amount output from the focus detection element 2, as shown by the broken line (0 change). In this graph, numbers 1 to 4 are the process of moving the photographic lens toward the focus position.C1 is the reference level that gives a low contrast level, and C2 is the reference level that gives a high contrast level. In Fig. 3B, the ○ mark indicates that the focus can be detected, and the
The focus can be detected up to the 4th position, and the focus cannot be detected at the 4th position, and the setting level is set to a high value. , at the 8th position, the judgment that the focus cannot be detected is escaped, and from the 4th to the 7th position, the focus can be detected. At the 8th position, the setting level is switched to narrow again. Figure 3 A shows the focusing zone. The blinking of the focus display is shown in the same format as Figure 3B when the camera is fixed at C straddle.Compared to B, the frequency of changes in which focus cannot be detected has increased, and the present invention makes it easier to focus. It has been shown that the stabilizing effect of undetectable warning can be obtained.
Having finished the general description of the embodiment shown in the figure, the same-diameter embodiment will be described in more detail below.

(See next page) The embodiment according to the present invention shown in FIG. 1 is a single-lens reflex camera (
The light-receiving section of the focus detection element 2 used for this purpose is disposed at the bottom of the mirror honk, and the light beam from the object that has passed through the photographic lens via a well-known optical system is exclusively directed to the light-receiving section. Focus detection element 21
In this case, for example, a known device known as T, C top manufactured by Honeywell is used. This focus detection device has a line sensor 4 in the light receiving part, and this line sensor is composed of a charge accumulation type photodetection element CCD, and transfers and outputs the charge accumulated in the integral time, and outputs the charge. Based on this, a predetermined noalcoholism calculation process is performed to detect the amount of defocus and its direction.

This detection operation is performed repeatedly, and the defocus signal is output intermittently.

Further, the focus detection element 2 is provided with an AGC circuit which momentarily outputs a signal proportional to the total load of the integral and automatically stops the integral operation when this signal reaches a predetermined level. In other words, the product of the illuminance I on the light-receiving surface and the integration time τ is kept constant, and the average level of the output is always kept almost constant regardless of the subject brightness so that it is convenient for the subsequent signal processing system. . The line precipitator 4 is controlled by a signal from the control circuit 6 to store and transfer charges. AGC
The circuit is included in the control circuit 6. When the transfer operation is started, the line sensor 1 sequentially outputs a voltage corresponding to the accumulated charge by each type i. The sample bold circuit 8 temporarily holds the voltage signal from the line sensor 1. The A/D conversion circuit f\:510 converts the analog voltage held in the sample and hold circuit 8 into a Tenkle value. The converted tenkle values are sequentially stored in the storage circuit 12 at addresses designated as children. The information stored in the memory circuit 121 is given to the arithmetic circuit 14, where it undergoes a predetermined algorithm calculation process, calculates the defocus amount and its direction, and outputs it to the output line 20 as the Deinotal tear orcus signal. .

Further, the arithmetic circuit 16 calculates a signal indicating the contrast intensity of the subject image in the portion received by the line sensor 4 from the information in the memory circuit 12. Further, the timer circuit 18 measures and outputs the charge accumulation time τn in the line sensor 4 for each detection cycle.

Next, the configuration of the display stabilization circuit 22 will be explained. The arithmetic circuit 26, in which the output line 20 of the focus detection element 2 is connected to the input line 24, assumes that the tear orcus signal from the nth detection cycle is Xn, and that the arithmetic output of the arithmetic circuit 26 for this signal Xn is Y11. The calculation shown by the following formula is performed.

yn-αxn+(1-α)yn-1・・・・・・・・・
(1) In equation (1), α [ is either 1 or 1/2 as described below. yn-1 is the nth
-Tear Orcus Signal xn by First Detection Cycle-
This is the calculation output of the calculation circuit 26 for the calculation 1.

In addition, for the defocus signal x1 of the first detection cycle, the above α is initialized to α-1 so that y1=xl, and Xl is directly output as yl to the next stage judgment circuit 28 and storage circuit. given to 30. The arithmetic circuit 26 calculates the average of the defocus signal xn of the latest detection cycle and the signal y n -1 obtained from the previous defocus signal when it becomes α-1/2 as will be described later. be. Here, by expanding equation (1) in the case of α-1/2, equation (2) is obtained.

・・・・・・・・・(2) (2: As is clear from the formula, the output of the arithmetic circuit 2G gives the most weight to the latest data, and outputs multiple data whose weight is reduced according to the past data. This is to calculate the weighted average value of the data.As mentioned above, the defocus signal of each detection cycle for the same distance (there is some variation, so it is necessary to take the average value of multiple defocus signals. The reason for this is to give the most weight to the latest data and reduce the influence of past data for the following reason. If the subject is stationary and the subject is at a certain distance from the camera, multiple defocuses 1
゛In order to find the average value of the iris, we divide each [this weight (
There's no need to do anything. However, in reality, the photographing lens is manually moved toward the in-focus position, and the distance between the subject and camera can change, so it is difficult to match the latest defocus signal with the past defocus signal. If equal weight is given, error factors other than the dispersion of the individual will have a large influence. For this reason, less weight is given to the data from h.

The determination circuit 28 compares the defocus signal yl) from the arithmetic circuit 26 with a predetermined focus threshold Z, determines in-focus or out-of-focus, and calculates the result dr+ as shown in Table 1. Output as a signal. In response to this output, display light emitting diodes LL, L2. Either L3 is lit. In Table 1, C represents the determination circuit 5, which will be described later.
A 1-hint signal output from 0 indicates whether the contrast of the object has reached a predetermined level I or not.

If the contrast reaches a predetermined level and is not 0, it is assumed that focus detection is impossible, and the output dn is output from the constant circuit 28.
"11" is output as the result.

Table 1 Cy n: Z Judgment Result Output dn Table
Indication (detection ability) yn<-Z Rear pin 10
L3 lit 1 Undetectable 11
L2. A display circuit 32 having an L3 point blinker (In) as an input drives light emitting diodes L1, L2, and L3 of a display means 34 of a known type provided within the finer.

The memory circuit 36 stores the output yn+1 of the arithmetic circuit 26 for the output x n + 1 of the (n+1)th detection cycle.
The signal dn is temporarily stored until it is given to the determination circuit 28, and the stored value is given to the selection circuits 40, 44, 48 and the arithmetic circuit 54.The selection circuit 40 stores the n-th defocus signal In order to perform the calculation of the first equation using Constant α1-1.α2 = 1
/2 is selected and input to the arithmetic circuit 26. When the signal dn-1 is "00'' indicating focus, the constant α
2=1/2 is selected, and weighted average processing is performed on defocus signals obtained in the past from the latest defocus signal xn shown in the second equation. For cases other than focusing, constant α1=
1 is selected, and the arithmetic circuit 26 outputs the input X as the output y n.
11 is output as is. In other words, in the out-of-focus area, the photographing lens is moved toward the in-focus area and changes its position moment by moment, so if you average multiple defocus signals from the past obtained in such cases, Even if the lens actually reaches the in-focus area, the average processing calculation result is not the same as the past out-of-focus data. They don't do it.

Next, the constant storage circuit 42 and the selection circuit 44 are connected to the determination circuit 2.
A first hysteresis circuit 45 is configured to provide a hysteresis characteristic to the constant storage circuit 42, and the two constants 71 stored in the constant storage circuit 42 are configured in response to a signal 'd n -1+ from the number storage circuit 36 as shown below. or Z2 is input to the determination circuit 28 as a focus determination reference value. two constants Z
1 and Z2 are in the ratio of 1 to 5 where Zl<Z2, and when the photographing lens is initially in the out-of-focus area and is moved toward the in-focus area, the smaller constant 71 is used as the focus judgment reference value. is used, and the constant Z 1. When it is determined that the photographing lens has entered the corresponding focus area, the larger constant 72 is prepared as the focus judgment reference value for the next detection cycle's defocus 1n@ (in other words, the initial Set the focus area narrowly, adjust the focus by adjusting the narrow area to the target area, and then widen the focus area once the target area is reached. This prevents flickering.The constant Zl
, Z2 are experimentally determined to be appropriate values. When the constant Z2 is supplied to the determination circuit 28, the difference ΔZ between the two may be added to the constant Zl, or when the constant 71 is supplied (ΔZ may be subtracted from the constant 72). Constant storage circuit 46 and selection circuit 48 are 1
A second hysterin circuit 49 is configured to provide a hysterin characteristic to the constant circuit 50.

The determination circuit 50 determines whether or not the contrast signal from the focus detection element 2 has reached a predetermined level.The reliability of the determination signal tends to be low, and if there is no contrast, defocus cannot be detected. . Therefore, a contrast judgment level is set in advance, and if the contrast signal does not reach the judgment level 1, it is assumed that defocus detection is impossible, and the judgment circuit 28 indicates +1 that detection is impossible.
1111 is output. Contrast determination circuit 50
Similarly to the judgment circuit 28 of Thea Orcus, a hysterinous characteristic is given to stabilize the judgment result.

Constants C1 and C2 stored in the constant storage circuit 46 constitute the first and second contrast judgment values, respectively, and the constant 0
2 is set larger than C1 by a predetermined value ΔC. These constants C1 and C2 are determined experimentally.

In the above case, the selection circuits 40, 44, and 48 select the fault of each preceding stage circuit in accordance with the output dn-1 of the circuit 36 (all shown in FIG. 6). That is, the most%
The child focus signal x n and the contrast Lj 5"r Cn l of the new detection cycle are broadly selected by the judgment result d n -1 of the judgment circuit 28 for the output of the detection cycle 6.) A predetermined operation is executed by the calculation circuit 26 and the determination circuits 28 and 5LJ.

Next: This circuit consists of a constant storage/distribution circuit 52, a value calculation circuit 54, and a counter 5G; 4. Located at the photographic lens or focus position i.
Finally, the main part of a detection number limiting circuit is constructed so that the number of detection operations per unit time [1] exceeds a predetermined number of times. The line sensor 11 accumulates charge over an integration time of 4 (J 71 seconds to 40υn1 seconds or (j) depending on the intensity of the incident light. On the other hand, from the end of integration, a predetermined take process is performed to determine focus. A certain amount of data processing time, for example about 5U + η seconds, is required to output the results and perform the display operation.If the integration time of CCI) was limited to a maximum of 400 msec, it would take -11 detection cycles. The period, that is, the sum of the integration time and the take processing time, is usually 50 msec to 450 msec. Therefore, if the detection cycle period is 50 msec, 20 detection operations are performed per second. In the case of focus, when such a detection operation is performed, as mentioned above, since there is variation in each tear orcus, the focus display element L1 and the out-of-focus display element L2 or L3 will alternately display the focus display element L2 or L3. In some cases, the lights may turn on repeatedly (1:+), which confuses the person in the shadow. Therefore, when focusing, limit the detection cycle period to the shortest period, for example, about 100 msec, to prevent flickering on the display. In order to do this, at the time of focusing, if the integration time τ■] or a predetermined constant time τ0, for example 50 msec, is shorter, the difference Δτ(
-τ〇-70) Delay the height detection cycle and start the next detection cycle. Returning to the circuit, the constant storage circuit 52 stores the take corresponding to τ0 for a certain period of time. The arithmetic circuit 54 receives the signal τn from the timer circuit 18 at the end of the integration.
In response to the signal dn-1 from the memory circuit 36, the signal Δτn shown in Table 2 is outputted to the counter 56.

Table 2 dn l Δτn 11 ((Humble 00) The counter 56 outputs the judgment result dn-1 from the judgment circuit 28 to the display circuit 32 and the storage circuit 32, and after display and storage operations are performed in each, the system The counter 56 measures Δτn based on the counting start signal given from the control circuit 58, and outputs a timing end signal after the counting ends.Here, when Δτn=O is given, the counter 56 immediately starts counting in response to the counting start signal. System control circuit 58 configured to output a timekeeping end signal responds to the timekeeping end signal by:
The focus detection element 2 is commanded to start a new detection cycle.

Note that if the number of detections is limited when out of focus, the response speed from the out of focus display state to the in focus display state will be degraded, so the number of detections is not limited as described above.

Next, the operation of the circuit shown in FIG. 1 will be explained. Now, when the photographer presses the detection switch 60, the system control circuit 58 immediately initializes the output of the memory circuit 36 to 011 degrees and instructs the focus detection element 2 to start integrating the CCD. Once the initial setting of the memory circuit 36 is made, each interval of the display stabilizing circuit 22 is defined as shown in Table 3 based on the initial settings.

Table 3 Output α of initialization output selection circuit 40 α2=1 selection circuit 44
Output Z of the Z1 selection circuit 48 Output CC1 of the arithmetic circuit 54 Output Δτ O Output of the display circuit 32 Output of the OFF judgment circuit 50
When the corresponding time has elapsed, the integration operation is stopped, and the charges accumulated in each cell of the CCD are transferred as a voltage signal to the sample-and-hold circuit 8 (which is inputted to the A-D converter circuit 10 and sequentially converted into digital signals). The defocus signal 2 and the contrast signal are outputted from the arithmetic circuits 14 and 16 after the If'r calculation has been completed. On the other hand, the timer circuit 18 C
The CD integration 1ffJ start clock pulse is set, the clock pulse is counted during the integration period, and the count value τn is set when the integration is stopped.
Output. However, if the CCD integration requires more than a predetermined period of time (for example, 200 msec), use A.
The system control circuit 58 is provided with a function to forcibly command the integration to stop when a certain period of time has elapsed to wait for a stop command from the GC, to prevent integration from taking a long time when the subject is dark. It is desirable to do so.

Now, when the focus signal x1 and contrast signal Ctl from the first detection cycle are output,
Since the arithmetic circuit 26 has been initialized to α-1, it directly outputs xl as the output yl, and provides it to the judgment' circuit 28 and the storage circuit 30.

On the other hand, the determination circuit 50 compares the initially set contrast comparison reference value C1 and the contrast signal Ctl.
The result is given to the determination circuit 28. If the contrast of the object is sufficient and C1<Ctl, the judgment circuit 2
8 is the focus judgment reference value z1 and the defocus signal yl (=
xl) and outputs the comparison result d1, which is displayed on the display circuit 32.
and is applied to the memory circuit 36. Now, if n is detected as the front pin as a result of the determination, then the display element L2 is lit. Who is the photographer? Following the display, turn the focus ring and move the photographic lens toward the in-focus position.

By the way, the arithmetic circuit 54 outputs the output Δτn to the counter 5.
6, but in the first detection cycle number,
Since the counter 56 is initialized to Δτn-0, the counter 56 immediately sends back a count end signal in response to the count start signal from the system 1 β 118 circuit 58. The focus detection element 2 thus enters the second detection cycle. Subsequently, the system control circuit 58 causes the memory 1q paths 30 and 3G to output the memory yoku.

That is, the output of the memory circuit 30 is yn-1-yl(=)<])
Therefore, the output of the memory circuit 3G becomes dn-1-dl. Therefore, each selection circuit 40 selected by the n-th groove number d
, 44. The constants from 48 are as shown in Table 4.

4th expression α cutting bribe, 30 selection circuit (40) selection circuit (44
) selection circuit (48) force (dn-1) output α)
output is Z) Output (c) 0 11 (undetectable)' (Q!2=l) ZI
C2 Next, as in the case of the first @rosu cycle, the focus detection element 2 sends the integral time data τ2 to the arithmetic circuit 541 after the completion of the CCU integration, and also calculates the defocus salt Xn and sends it to the arithmetic circuit 541. Output to 26. In response to the signal dn-1 (-di), the arithmetic circuit 54 outputs an output Δτn (-Δτ2) as shown in Table 2 above.

On the other hand, the arithmetic circuit 26 calculates y2−αx2 based on the formula
+(1-α)yl...13) is performed. If the first moon is in focus here, α-1/2
The average of the first and second defocus amounts is taken as the output y2. If W1 is out of focus, α-1 is used, and the second defocus gx2 is output as output y2 regardless of the previous yl. The determination circuit 28 compares the signal y2 with the output 2 of the arrester circuit 44 and outputs the determination result d2 as shown in Table 1. In this case, if the result of the previous or first time was in focus, a slightly wider focus zone than the zl used last time is set with z-22(!l-, and regardless of whether it was the previous time or out of focus) , a narrower focusing zone is successively set.!l!iJ When the fixed result d2 is obtained, it is transmitted to the display circuit 32 to display the second detection result, and on the other hand, the memory It is transmitted to the circuit 36 and stored.Next, the counter 56 starts the timing operation of Δτ2, and when the timing end signal is issued, the system control circuit 5
8 issues a command to start the third detection cycle.

For the third and subsequent detection cycles, the same process as the second detection cycle described above is repeated.

Note that the system control circuit 58 monitors the state of the switch 60 during operation, and when the switch 60 is opened, the 1
The camera may be configured to automatically turn off the power supply circuit after 15 seconds to complete the series of focus detection operations.

To summarize the above operation, if the previous judgment result is out of focus (in this case, only the current tear orcus ff1xn is targeted, regardless of the previous result, Determine whether the L It is determined whether the eye is within the set focus zone.At this time, a restriction is placed on the shortening of the production cycle period for relatively bright subjects.

By the way, in the focus detection element, when the defocus amount xn is determined according to a predetermined algorithm, a sufficiently reliable answer may not be obtained depending on the output value of each cell of the CCD. For example, if the contrast of the subject is low,
In cases where there is almost no difference between the outputs of each cell of the CCD, or in cases where the field of view is so dark that the amount of charge stored in the CCD is small, the focus detection element is out of its detection capability. In such a case, the judgment circuit 50 outputs a signal indicating that detection is not possible. It will be done. In this case, the determination circuit 50 is also provided with hysteresis characteristics to prevent the warning display from being replaced with the normal display rapidly.

Now, the nth] judgment result dm is not undetectable (d
m\"l 1"), that is, when there is sufficient contrast, in the i (m-4-1)th detection cycle, the contrast judgment circuit 50 determines that the contrast is low as the standard value. Level C1 is calculated and compared with contrast borrowing Ct+11+1 from focus detection device M2. In addition, if the 171st determination result d m is undetectable (d m = "11"), that is, if a warning is displayed due to insufficient contrast, the 171st determination result d m is
Core trust signal Ctm of the η+1)th detection cycle
-1-11 On the other hand, a higher judgment level C2 is given to the judgment circuit 50. The hysterin effect at such a level that it is impossible to perform is shown in FIG. 3. By providing the determination circuit 50 with hysteresis characteristics in this manner, instability of the display near the warning display determination level can be reduced.

FIG. 4 is a configuration diagram showing an embodiment in which the focus state display device of the present invention is configured using a microcomputer (for example, Intel 8, OC48). This device consists of a CCD block 62 arranged at the bottom of a mirror box of a seven-lens camera 61, a CCD control block 64 containing an A-D conversion circuit that controls the CCD and digitizes the output of the CCD, and a microcomputer. 66 and an AF switch 60 connected thereto for instructing focus detection.
Buzzer 68 for emitting a short-duration sound when in focus
and a light emitting diode Ll for displaying the focus status.
, L2. It is composed of L3 and the like.

The following flanks and counters are reserved in the RAM area of the microcomputer 66.

The 7lag FPF is set at the beginning of the first detection cycle (this ++ 1 ++) and is cleared from the second detection cycle. The flag LCF is set to 1' when the contrast is determined to be below a predetermined level. The flag LLF is cleared to "0" when it is determined that the brightness of the object is equal to or higher than a predetermined level. The flag LLF is set to "1'' when the brightness of the subject is determined to be lower than a predetermined level. 7 lag SFX is set to "1" when the defocus signal in each detection cycle indicates the front focus, and is cleared to "011" when it indicates the rear focus. 7 lag 5FYn is subjected to weighted average processing. +1 if the defocus signal is the front focus
Sent to 111 and cleared to It O++ for back pins. The flank IFF 11 is set to "1" when it is determined that the latest defocus signal)'l] is in focus/non-focus, and is set to "1" when it is determined that it is out of focus. Cleared to "0".

7 rank I F F n -1 holds the focus judgment results of OiJ times, and when the previous judgment result or focus is
It is cleared to 7' at 111, and when out of focus, it is cleared to 0°.

7 rank BF is used in the process of controlling the warning display operation when it is determined that the focus cannot be detected due to insufficient contrast.

The counters Tn and Te are used to determine the maximum integration time of ccD and are composed of a total of 2 bytes from the upper 1 byte Tn of 3t1 and the lower 1 byte Te. This counter starts counting by subtracting from a predetermined value at the same time as the CCD starts integrating.

The time required to count all the cent values is the maximum integration time. The counter BCTR is used as a timer to define the lighting time and extinguishing time when controlling the light emitting diodes L2 and L3 to blink as a warning display, and a constant Ncn is set in the initialization step. The timer counter TC"rR is provided as a counter in the microcomputer. It receives a long pulse from inside the microcomputer as an input signal, and can freely measure time by controlling the gate provided at the input section with the timer counter control command. This internal clock pulse is a divided basic machine cycle of the microcomputer.Also, when the count value of the timer counter TCTR overflows, the timer flag TF is automatically set to "'1". This timer flag TP can be used to test the contents of the program, and the Tefrogram can be conditionally branched based on the test results.
When this timer 7 lag TF is tested by the program, it is automatically cleared at that point. This flag TF is used as a control number for the number display a, which will be described later.

FIG. 5 is a 70-chart showing the 15tE deviation of the overall operation of the focus display device shown in FIG. In FIG. 5, when the power switch (not shown) is turned on, step S-
2, the microcomputer software 1 automatically performs the following initialization settings.

] Rub the floclumkaunk with “o” +.

2 Disable external interrupts.

3 Prevents input to the queue counter TCTR.

11. Clear the Kuima flag T F to ++ O++.

The software also performs the following initialization settings.

], CCI) jfilJ tll Supply of flocs to pronk 6 and 1 is started.

2. Set the initial value Con to count BCTR.

Next, in step S-3, the light emitting diodes L, L2 . Since an operation that does not turn on any of L3 cannot be performed and the display subroutine described later does not function, the timer flag TF is cleared to ``O++'' and the input clock pulse to the timer counter TCTR is blocked.Subsequently, step S- 4, "1'+1" indicating that it is the first detection cycle is sent to the 7-lag FPF. In step S-5, it is checked whether or not the AF switch 60 is on, and if it is off, steps S-4 and 3-5 are repeated and the state is in standby until the AF switch 60 is turned on. . When the AF switch 60 is turned on (when this happens, a command to start CCD integration is output to the CCD control block 64 in step 56, and when the CCU integration is completed, an interrupt request signal is generated from CCDff1'j kl front clock 4). In response to this, step 5-7 (here, the integral data is taken into a predetermined memory of the microcomputer. The detailed contents of step S-6 will be described later based on the 70-chart in FIG. 8). In step S-8, the output take of the CCD is processed by a predetermined algorithm to determine the focus amount and contrast including direction.

Since this arithmetic processing takes about 50 milliseconds, for example, several display subroutines (Fig. 9) are inserted in the middle of the arithmetic processing routine to prevent the flashing warning display described later from becoming unnatural. There is. In step S-9, the on/off state of AF switch 0 is checked again, and if it is off, the process returns to step S-3. If it is on, step S-101 is reached and the contrast determined in step S-8 is set to a predetermined value (Direct C and L Hi: 1). Step 5-
70-Char-1- showing the contents of 10 is shown in FIG. Referring to this 70-chart, the first detection cycle F
When P F = 1, C=C1 (<C2) is used, and when this is strictly enforced, the low contrast flag LCF is reset to it O++, and when it is not exceeded, LCF is set to "Lll". be done.

From the second detection, either C] or C2 is selected and used as the reference value C based on the comparison result of the first detection cycle, and the low contrast flank representing the previous result is used. When the LCF is "0" and the contrast is determined to be sufficient (-01 months, the contrast is determined to be insufficient after 1"' or the contrast is determined to be insufficient. If there is, C2 is used.The comparison result for the selected diagnosis value is sent to the low contrast flag LCF.At this time, the previous content is lost.

Next, in step 5-11, the weighted average Yn of the latest tefocus iXn and the past tefocus amount Ynl is calculated.
A calculation is performed to find In the subsequent step 5-12, it is determined whether the telefocus amount Yn calculated in step 5-11 falls within a predetermined focusing zone. A flowchart showing the contents of this step is shown in FIG. At step 11-1 in FIG. 7, it is checked by checking the flag FPF whether the flow in question is the first detection cycle. For the first detection cycle, step 11-
Moving on to step 3, a narrow value Z1 of 10,000 is prepared as the focus determination value Z. In the second detection cycle or thereafter, the flow moves to step 11-2, and the results of the 04th in-focus determination are checked from the 7th in-focus IFFn to the 04th detection cycle. The previous focusing result is determined in step 11-7 or 1l-8i, and if in focus, + (if 111 is still out of focus, focus 7 to 0'')
Cleared by lag IFFn. 4 Now, as a result of checking the focusing flag IFFn, if the result is out of focus, the process goes to step 11-3, and if it is in focus, the process goes to step 11-4. Proceeding to step 11-4, the wider value Z2 is prepared as the focus determination value 2. In step 11-5, the contents of the focus flap IFF'n are assigned to another focus flag IFFn-1.

This step is not related to the current focus determination operation, and the set information is used in the subsequent step 5-16. Next, it is determined whether the defocus amount Yn is within the focus determination value Z of 2t prepared in step 11-6. In the case of focus, move to step 11-7 and set the focus flag ■F
When Fn1 is out of focus, the process moves to step 11-8 and the focus flag IFFn is cleared to 0.In this way, the previous focus judgment result is set to 1. Therefore, the judgment value Z for this focus judgment is j IJ
:j A break hysterin characteristic is given.

Next, in step 5-13, the content set in the low contrast flag LCF in step 5-10 is checked, and if the contrast is not low, the next step 5-14 is performed.
Proceed to. In step 5-14, the contents of the focus flag IFFn are checked, and if the flag is in focus, the process proceeds to the next step 5-15. In step 5-15, it is determined whether the flow is the first detection cycle by checking the 7-lag FPF. In the case of 31 detection cycles, the process moves to step 5-18, and the light emitting diode indicating focus is turned on. If it is not the first detection cycle, proceed to step 5-16 and set the focus flag IFF
By checking n-1, the previous focus determination result can be investigated. If it is out of focus, proceed to step 5-18.

In other words, if the previous result was out of focus and the current result is in focus,
In step 5-18, focus is displayed. If the image is in focus this time as well as the previous time, the process moves to step 5-17, and in the case of high brightness).17, the period of the return cycle is extended. Now, following step 5-18, step S-
] 9, the light emitting diode L1 for in-focus display is turned on and a buzzer is sounded for a short time (for example, about 02 seconds) to audibly indicate that the focus zone has been entered. In the following step 5-20, it is checked whether the AF switch 6° is turned on. If it is loaded, step 5-
Step 22, and if a is not inserted, step 5-21
Move to. In step 5-21, the lit light emitting diodes are turned off. 7 lag FP in step 5-22
Clear F to ++011. Following this step, the flow moves to step S-6.

Next, the following table shows the contents of the CCD integration step S-6.
The 70-chart in the figure will be explained. Step 6-1
A signal instructing the start of integration is output at step 6-2, and then, at step 6-2, the low luminance 7 lag LLF is cleared to IO1'. In step 6-3, the microcomputer is placed in a state where it can accept interrupts, and the process moves to the next step 6-4. In step 6-4, the pulse count value corresponding to the longest integration time of 400 msec is entered into the counter Tn+Te. As mentioned above, this counter is the upper Tn,
It is composed of two bytes of the lower Te, and initially a count value Tnmax corresponding to the maximum integration time is set in the counter Tn, and FF (=256) is written in the counter Te. In step 6-5, it is checked whether the AF switch 0 is turned on. If it is, the contents of the counter will be decremented from then on, but before the count ends, that is, before the contents of the counter reach 0, the CC
When the integration of D is completed, an interrupt pulse indicating this is sent to CCD1.
When this occurs from the lJ control block 64, the counter subtraction operation is stopped and the process moves to the interrupt processing routine. If no interrupt occurs, the CCDF will display “
1'J is set and moves to the next step.

Steps 6-6 to 6-10 are the flow of counter subtraction counting. In step 6-6, one count is subtracted from the contents of the lower counter Te, and step 6-
At step 7, it is checked whether the contents of the counter Te have become 0 or not. If it is not 0, return to step()-5. In this way, step 6-5 until Karan Te becomes 0.
and convert the lid of 6-7. Counter Te is 0 (when this happens, the process moves to Ste'knob 6-8, which will be described later, and then step 6
-9, the upper counter Tn is decremented by 1. In step 6-1O, it is determined whether the counter Tn has reached 0 or not, and 4 is counted. If it is not 0, the process returns to step 6-5.

Thus, unless an interrupt occurs, the counters Te, T
70 steps between steps 6-5 and 6-10 until n becomes 0.
- is in progressive form. The time required for this progression is approximately 400 msec. Step 6-11 forces the CCD integration to end, and then step 6-12 sets the low brightness flag L.
, LC is cented to ++ 1 ++. This means that the subject brightness is low. In any case, when the integration is completed, an interrupt occurs and the microcomputer 66
Then, the process enters step S-7 of interrupt processing for importing integral data. However, if the AF switch 60 is in the OFF state in step 6-5 of L1, the microcomputer 66 enters an interrupt disabled state, stops the CCD integration, and returns to step S-3.

Step 6-8 is a subroutine for displaying lectures, the flowchart of which is shown in section 9. With this diagram in mind,
In step D-1, it is determined whether or not 11111 is set in the timer flag TF.If it is 0°, the process returns.In other words, the timer flag TF is set to 11111.
”, the display operation subroutine is used. When the timer flag TE is checked, it is automatically cleared to “0” (step D-2).
Then, the low contrast flag LCF is checked, and if the brightness is not low, the process moves to step D-3, which is a focus state display routine. In step D-3, the focus flag INFn in which the latest focus determination result is set is checked, and if the focus is in focus, the light emitting diode L1 is turned on in step D.
-Move to 4. If the image is out of focus, the sign flag 5FYn indicating the direction out of focus is checked in step D5, and the light emitting diode L2 or L3 is lit in response to the front focus and rear focus.

)-4 machines with low contrast, the flow moves to step 1)-8, which is a warning display routine, and the flashing flag B F
is checked. If this 7 lag is α of 111, it is applied across the counter BCTR in step D-13, and then in step D-14, the counter BCTR is set to 0.
It is checked whether the Counter B C'F
R is the constant No at the initialization knob S-2.
Since n is set, the flow continues as many times as Step D as long as the last state continues.
Pass through -13.

This 1. At step Di-5, light emitting diodes L2 and L
;3 are lit at the same time. When it is detected in step D-13 that the counter BCTR has become 0, 70- proceeds to steps D-16 and D-17, clears the 7 rung BF, and sets the constant Noff in the counter BCTR. Here, the constant Noff is the light emitting diode L2. Delete L3 (which regulates the period, for example, 3 of the constant Non)
(This is determined by the value of g. In other words, the ratio of the light-emitting diodes L2 and L3 during the period of 1 m between turning on and turning off at the time of threat is 1:3.

However, this ratio (there is no need to limit it. Now, flag B
'F is cleared and ++OI+ state, the flow is guided to step D-9 10,000 times. As long as the low contrast state continues, 70- continues step -D-9 a constant Noff times. pass.

During this time, the light emitting diode L2. L3 is turned off.

In step D-10, the counter BCTR is set to 0 [If it is detected that this has occurred, in step D-11 it flashes 7 rungs BF
is sent, and the counter BC' is sent to D-12.
A constant Non is sent to TR. Therefore, in the next step D-8, the flow is directed to step D-13. In this way, the light emitting diodes L2 and L3 are controlled to blink as a warning display. Incidentally, the blinking flag BF may be set at the initialization step S-2, but there is no problem whether it is initially set or set.

The operation of the display subroutine will be explained based on the above explanation of the room display subroutine and the fifth overall flowchart. In step S-3, the timer counter T CT
R is stopped and timer flag 1'F is "o"
” Since this has been initialized and the display LE'L is also turned off, in the first detection cycle, even if the display subroutine 70- jumps, step D in Figure 9 is not executed. Since TF-"'0" is at -1, by returning immediately, display -=, i'- is not performed and the light emitting diode remains off. At the end of the first detection cycle, step 5-
Since the clock input to the timer counter TCT ■< is permitted at 22, the timer counter TCTR generates over 70 pulses at predetermined intervals in the 42nd and subsequent detection cycles in the evening, and the timer flag TF becomes 1.
Since it is set to 111+, if it is TF-"l ++ at the time of jumping to the display subroutine, the above-mentioned focus adjustment dog state display or q notice display is performed and the return is made. Note that TF -, +1111 when display intercropping is performed, timer 7 lag TF is cleared to 0++, so the blue routine number displayed by the flow is a child that is sent to "1" by the occurrence of the next over 70- pulse. Even if you jump, the display ND operation will not be performed.

Figure 10 shows step 5 of the weighted average calculation in Figure 5.
It is a 70- chart showing the contents of -11. At step F-0 in the Hto diagram, the process from Sten 7'F-1 onwards is carried out, and the value being composed in the memory Yn at that point is transferred to the memory Yn-1 as the previous average value. Step F-1
If the 7-lag FPF is checked and 11111 indicating the first detection cycle is detected, the flow moves to step F-2 and the flag IFFn is checked. At this point, the 70g IFFn still holds the previous focus determination result. If the previous determination result is out of focus, the flow jumps to step F-15, and if in focus, the flow moves to step F-3. In this step F-3, the sign of the defocus amount yn-1 used in the previous focus determination, that is, whether it is on the front focus side or on the rear focus side is checked using the flag SFY. At this point, the contents of the flag SFY are also the same as 7 Raku I i' F n (the niJ judgment results are still being written. Note that even if the tefocus signal is in the in-focus zone, the front focus or There is no difference in saying the polarity indicating the rear pin.Step F-:3
If S F N' = "1", that is, the front pin function, then 7
0-, the process moves to step F-4, and the sign of the focus signal xn from the current detection cycle is determined by the flag SFX+. Move to -5, 5FX-
In the case of "O11", that is, the back pin transmission, the flow moves to step F-8.In addition, in the case of "0゛'", that is, the rear pin transmission in step F-31, the flow goes to step F-7.
As in the case of step F-4, the sign of the defocus amount xn in this detection cycle is checked using the flag SFX, and 5FX=i+111, that is, the front focus is aligned, and the flow moves to step F-8. X = “O”
That is, the crystallization of the rear pin moves to step F5. -The processing in each step of F-3, F-4, and F-7 is performed by combining the previous defocus direction 1tE2 S F'Y and the current defocus direction SFX, and the defocus direction changes. If the defocus direction has not changed, the process moves to step F-5, and if it has changed, the process moves to step F-8. If the defocus direction has not changed, step F-5 (here, the absolute value Y of the average value y n −1 up to the previous time and the current value x n
Only n-1 and Xn are added together, and the sum is divided by 2 in step F-6i to obtain a new average value Y
, n are found. In this case, although there is no change in the defocus direction, it is not necessary to change the flag SFY. :T
In cases where the defocus direction is different from the current defocus direction for the ij time, an averaging process is performed in consideration of the sign from step F-8 to step F-6. First, in step F-8, x'
It is checked whether n is equal to 0 or not, and if it is equal to 9, the process goes to step F-13, and the previous average 1 straight Y n -1
is the total value Yn of the previous and current time, and then step F-1
4 clears the carry 7 lag Cy to ++ 011, and then divides by 2 in step F-6i to get the current average value -
'! ' n can be found. In this case as well, the previous and current normal force values y n -1 and the smoothing of yn in the defocus direction (
There is no need to rewrite 7-lag SFY.

At step F'-81, if xn
-1 (= 1. y n-11) by the absolute value Xn (-1xnl) of the current defocus value, and the result is set as Yn, and in the next step F-10, Y n is determined depending on the carry 7 lag Cy. -1 and the size of Xn 15-
The person in charge is being determined. This is because the focus direction has changed between the previous time and this time, so it is not possible to obtain an average value by adding only the thickness of the defocus between the previous time and this time.

Note that subtraction is performed by adding the complement of the number to be subtracted for real division. As a result of the addition, if 17th rung Cy is set due to carry, the result of the addition is used as is as the result of subtraction. In this case the flow is step F
-14 to step F6. Carry flag Cy cleared I;2. 8 (the complement of the bullet ○result number is 1): 1. However, only in this case, the sign is inverted, so in step F-12i, the sign flag SFY is The previous content is reversed.

Next, the process moves to step F-6 and an average value is determined. As described above, when the previous determination result is in focus, the defocus amount xn from the current detection cycle is given a weight of 1/2, and the average value with the past defocus amount is calculated. This result (weighted average Yn shown in equation 24, that is, Y n
and SFY are obtained, and the focus judgment in step 5-12 is performed. In addition, if the first detection cycle or the previous judgment result is out of focus, step F-1
5. At F-16, the current measured value Xn, that is, the absolute value Xn
and defocus direction SFX are respectively the current processing Yn
The image is transferred to the memo JYn and the 7-lag SFX, and one image is provided in the focusing format in step 5-12.

To summarize the above explanation, if the first detection cycle or the previous judgment result was out-of-focus, the current measurement value for which weighted averaging is performed is used as is, and the result is half-determined. If the previous determination result is in focus, averaging processing is performed taking into account the sign between the previous average processing value Y n -1 and the current measurement value X n. Due to this reason, averaging processing is not performed in the out-of-focus state, so it is possible to display the latest measurement take from time to time without being dragged down by past measurements 11a. It is possible to minimize the time delay in the transition of the display to the focus state, and in the Σ3-focus state 1, it is possible to improve the display instability caused by the paranki of the measured value each time. -Repeat the averaging process twice for the latest average, 3:5 Y ;;
The stop of i (1 is a good value, . . . ) decreases in proportion to ::, and so-called force i ton averaging processing is performed. still,
This weighted average processing becomes effective when the positional conditions between the camera and the subject change due to movement of the subject, camera shake, etc.

FIG. 11 is a flowchart of a routine for suppressing display flicker at high brightness caused by step S-171 in FIG. 5;

As mentioned above, when the subject is of high brightness, the time interval of the CCD is short, on the order of several+n] seconds or less, and the number of detection cycles per unit time becomes large. Therefore, the number of display operations per unit time also increases, and flickers and cracks in the display become easily noticeable. Therefore, if the CCD integration time τ1] becomes shorter than the predetermined time τo (=50 msec), a waiting time Δτ'' is created and the detection cycle time is extended by the waiting time, thereby increasing the unit time. This limits the increase in the number of detection cycles per hit and suppresses display flickering.In FIG. 11, the low brightness flag LLF is checked in step H-1, and it If II+ is set, 70- jumps step 5-22.++ If cleared to 0++, step H-
The process moves to 2, and flicker suppression processing is proceeded. In addition, C.C.
Information on the integration time of D is obtained by the integration routine shown in FIG.

In FIG. 8, during the integration of the CCD, the counter Tn.

is subtracted and counted, and when the CCD integration ends midway, CCD f'i; In response to an interrupt request signal from the block 64, the flow jumps to an interrupt routine.
The subtraction counting operation of the counter Tn is stopped. Therefore, a value Tn obtained by subtracting the count value during integration from the initial value Tnmax remains in the counter Tn. Here, the 12th
Referring to the graph in the figure, consider an integral time τO at which the waiting time is exactly 0, and let TO be the remainder of the counter Tn corresponding to this integral time τ0.

For the first shift of τ0, the shortest detection cycle is determined by considering both the degree of display flickering suppression and display responsiveness, taking into account the operability of the camera, and the value obtained by subtracting the calculation time from that value. It will be done.

In step H-2, the value To corresponding to the above τO is subtracted from the count value remainder Tn stored in the counter Tn, and the result ΔT is stored anew in the counter Tn.

In step H-3, check whether the subtraction result is O or not, and
If so, the process goes to step 5-22, and if it is not 0, then in the next step H-4, the carry-7 lag Cy generated as a result of the subtraction (complement addition) in step H-2 is checked.

If the calculation result in step i-1-2 is negative, ΔT is 0, that is, cy=o, this means that no waiting time is required, and the flow jumps to step 5-22. If cy=t, that is, if the subtraction result in step H-2 is positive ΔTo, the detection time cycle is too short, and the loop returns from step H'-5 to H-10 to H-5. In step H-2, the state of the AF switch 60 is checked for a period corresponding to the count value ΔT newly stored in the counter Tn, that is, the period is the same as ΔT, and the display is controlled while waiting for the elapse of time.

In step H-5, the state of the AF switch 60 is checked, and if it is off, the process moves to step S-3. If it is on, step) (Go to -6 and counter Te
Subtract 1 from . Next, the process moves to step H-7, and it is checked whether the contents of the counter Te have become 0 or not. If it is not 0, the process returns to step H-5, and 70- cycles between steps H-5 and H'-7 until Te=0.

When Te-〇 is reached, the process moves to step H-8. Step H-
8 is a display subroutine shown in FIG. When proceeding to step H-9 following step H-8, the counter T
The content of n is subtracted from Tn, and step H-10
It is checked whether T n = 0 or not.

If not, the flow returns to step H-5. In this way, the flow continues between step ■]-5 and I-I'-10 until T +1 = 0, by repeating the above-mentioned step H.
-5 and I-I-10.

When Tn=U in step H-10, 70- moves to step 5-22. As described above, in the routine of FIG. 11, the count value ΔT corresponding to the waiting time is obtained, and the time required to subtract this count value until it becomes 0 is applied to the waiting time.

(Next page below) Effects According to the present invention, even if the detected object contrast is near the lower limit of focus detection and is fluctuating up and down due to various error factors, there is a wide range of criteria for determining whether or not to issue a warning. Since I gave a range of 1 and made it so that the variable number within that range does not respond, if you think it is possible to detect focus while aiming at a single subject, it becomes impossible to detect focus, and you will think to focus manually. Once again, the situation of being able to detect focus is resolved, and the camera user can enjoy the benefits of automatic focus detection without the problem of being distracted by the camera's display and making operations more confusing. can.

[Brief Description of the Drawings] Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a graph showing hysteresis operation in contrast determination,
FIG. 3 is a graph showing the effect of the same operation, FIG. 4 is a block diagram of another embodiment of the present invention, FIGS. 5 to 11 are flowcharts showing the operation of the above embodiment, and FIG. 12 is a CCD This is a graph for explaining the operation of limiting the shortest integration time, and Figures 13 and below show known examples, and Figures 1 and 3A and 3B show optical parts of known focus detection means, respectively. A side view, FIG. 14 is a plan view showing the configuration of the light receiving section of the CCD, FIG. 15 is a circuit diagram of the CCD integration time monitor circuit, and FIG. 161 is a 70-chart showing part of the above circuit operation.
FIG. 17 is a memory map of the RAAr1 area related to the same operation. Fig. 7 Fig. 11 Fig. 1Z Fig. 4n, D18 Fig. 13 Fig. 9 Fig. 14 Ge D 62

Claims (1)

[Claims] (1) A focus detection means that periodically detects the focus state of the photographic lens and outputs a signal indicating the contrast state of the photographic subject upon receiving the limb photographing light transmitted through the photographic lens; A comparison circuit that determines whether the contrast of the subject is above a predetermined level by comparing it with a predetermined reference level.If the contrast is determined to be below a predetermined level, a signal is generated that generates a warning signal. The comparison circuit uses first and second reference levels of different levels as basic levels to eliminate the generation cycle. The pin + [output of the camera is characterized in that a reference level setting is applied to the comparator circuit so that one of the two reference levels is selected as the reference level in the current operation cycle based on the result number. Device. (2+ The second @ reference level is a level corresponding to a higher contrast state than the first reference level, and the comparison circuit 2. The camera focus detection device according to claim 1, wherein the second reference level is applied to the comparison circuit in the current operation cycle when it is determined that the second reference level is applied to the comparison circuit in the current operation cycle.