JPS59151468A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the variation of the width of an offset region by isolating and demarcating each active region by a field oxide film and forming the offset region to the lower section of the field oxide film. CONSTITUTION:Si3N4 Films 33 are formed selectively on an N type Si base body 31 through an SiO2 film 32. P Type impurity introducing regions 35 are formed, and N type impurity introducing regions 37 are formed. Field oxide films 38 are formed selectively, and the films 33, 32 are removed. An SiO2 film 42 as a gate oxide film is formed on the base body 31, and a gate oxide film 43 is formed. The film 42 on drain and source forming regions is removed. Ions are implanted into the regions 40, 41. A surface protective film 45 is formed on the whole surface of the base body 31, a window for forming an electrode is bored to the film 45, and an SiO2 film 44' is formed and the whole is heated and treated. The regions 35 are changed into P<-> type offset regions 35 and a P<-> type low-concentration region 35' through the heat treatment. According to such a formation, the variation of the width of the offset regions is inhibited, and a protection on a base-body surface between a drain and a gate can be reinforced.

Description

[Detailed Description of the Invention] (a) Technique of the Invention The present invention applies to semiconductor devices, particularly MO8FETs for high breakdown voltages, and provides a MOS FET in which fluctuations in characteristics are suppressed and the number of manufacturing steps can be reduced. Regarding the structure of

(b) Technical Komon MO8 field effect transistors (hereinafter abbreviated as MO8FET) are currently the mainstream in semiconductor devices, especially integrated circuit devices.However, MOS FETs with an unconventional structure are usually used in fluorescent display tubes. The junction breakdown voltage, □, is insufficient for use in high-voltage drive IT devices such as the following! In a MOS FET with a normal structure, the drain breakdown voltage is reduced due to the following factors.

(a) Since the drain region and the gate electrode overlap with each other via a thin insulating film, electric field concentration occurs near the surface of the drain region, causing avalanche breakdown.

(b) The electric field between the drain region and the gate electrode increases, which tends to cause dielectric breakdown of the gate insulating film.

e→ When the channel length is short, the depletion layer extends to the source region, causing a so-called bunch-through phenomenon.

Therefore, in order to realize MO8FET=i with high breakdown voltage, it is necessary to provide means for suppressing and eliminating the above-mentioned factors.

(C) Prior art and problems Many proposals have been made to address the above factors in order to increase the withstand voltage of MOSFETs, but a typical method is to eliminate the overlap between the drain region and gate electrode and create a slight gap between them. There is an offset gate structure that provides

Figure 1 shows M of the conventional offset gate structure.
In Figure 0 showing a cross-sectional view of an example of an OS FET, 1 is an N-type silicon semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is a P+ type drain region, and 6 is a P- type □ offset region, 7 is a source region, 8 is an N+ type channel cut region, 9 is an oxide film, 10 is an insulating film, 11 is a drain electrode, 12 is a source electrode, 13
indicates wiring.

A P-type offset region 6 is provided in contact with the ion region 5, which is formed by implanting ions such as boron 03). This structure suppresses the factors (a) and (b) above, resulting in a drain-source breakdown voltage of -40 (V).
) degree has been obtained.

In the conventional example, the P+ type drain region 5 is selectively formed using a mask such as a resist without aligning the gate with the pole 4, which causes variations in the width of the P- type offset region 6. The OP-type offset region 6 has a high resistance in the operating state of the MOS FET, and fluctuations in its width appear as fluctuations in the channel resistance, which is particularly problematic in low impedance circuits.

＋　　　　.

In addition, in the conventional example, the oxide film 9 covering the semiconductor substrate 1 between the P-type train region 5 and the gate electrode 4 is thin like the gate oxide film 3, so that the electrostatic withstand capacity may be insufficient. There is.

It is desired to improve the above-mentioned fluctuations in characteristics and weaknesses.

(d) Purpose of the Invention It is an object of the present invention to suppress fluctuations in offset region width and further strengthen protection on a semiconductor substrate surface between a drain and a gate in a high-voltage MO8FET.

(e) Structure of the Invention The object of the present invention is to provide a semiconductor substrate having a first conductivity type, a gate oxide film disposed on the surface of the substrate, and a first semiconductor region in contact with the gate oxide film. , second and third semiconductor regions disposed near the surface of the base body and having a second conductivity type, and an insulating film separating and defining the first, second and third semiconductor regions; , disposed under the insulating film, in contact with the second or third semiconductor region and the first semiconductor region, and having a smaller concentration of cine fines than the second or third semiconductor region. , fourth and fifth semiconductor regions of a second conductivity type, which are selectively disposed under the insulating film other than the fourth and fifth semiconductor regions, and have a higher concentration of cine fines than the substrate. a sixth semiconductor region of the first conductivity type, which is in contact with the gate oxide film;
and a gate electrode extending over the insulating film on the fourth and fifth semiconductor regions.

Further, the semiconductor device is disposed under the insulating film,
A seventh semiconductor region of a second conductivity type, which has an impurity concentration lower than that of the second semiconductor region, is in contact with or separated from the sixth semiconductor region and is in contact with the second semiconductor region. By including it, the withstand voltage is further improved and stabilized.

(f) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

FIGS. 2(a) to 2(f) are cross-sectional views showing an embodiment of the present invention during its manufacturing process, and the features and effects of the present invention will be explained following the manufacturing process.

FIG. 2(a) If the reference impurity concentration is, for example, 5 x 10" (cFrL-3,
) grade +7) Silicon dioxide (5i02) M with a film thickness of about 10 (nm) on the N-type silicon (Si) substrate 31
A silicon nitride (Si3N) film 33 with a thickness of about 100 nm is formed through the 5isNa film 33 in a region where an insulating film (hereinafter referred to as a field oxide film) for separating and defining each active region is to be formed. selectively remove.

Next, the windows in the inter-element region of the 5isN4 film 33 are covered entirely or with the exception of the vicinity of the drain formation region with a resist film 34.

After that, for example, boron (B) is heated to an energy of 25 (K).
The Pij11 impurity-introduced region 35 is formed by implanting ions at a dose of about 3 x 1012 (['').

Refer to FIG. 2(b), the resist film 34 is peeled off, the area other than the channel cut formation area is covered with the resist film 36, and phosphorus (P) is applied at an energy of 80 (KeV) and a dose of 5×10.
An N-type impurity doped region 37 is formed by implanting ions of about 12 [crrL-2].

Refer to FIG. 2(c), the resist film 36 is peeled off, and the 5isN4 film 33 is removed.
Selective thermal oxidation is performed using as an oxidation-resistant mask to selectively form a field oxide film 38, and remove the Si, N film 33 and the Sin film 32.

The field oxide film 38 formed here separates and defines the gate formation region 39, drain formation region 40, and source formation region 41, and determines their positions and dimensions.

Note that the P-type impurity doped region 35 and the N-type impurity doped region 37 are located under the field oxide film 38.

Refer to FIG. 2'' (d) 81 A film 42 of Sin is formed on the surface of the substrate 31, usually by thermal oxidation, to a thickness of, for example, about 70 (nm).This S10 film 42 becomes a gate oxide film.

-7.- Next, a gate electrode 43f made of polycrystalline silicon is formed by a chemical vapor deposition method or the like. This gate electrode 4
3 is a field oxide film 3 surrounding the gate formation region 39;
8, it can be patterned regardless of the gate length. Next, the drain formation region 40
Then, all 42 parts of the stow film 42 on the source formation region 41 are removed. Next, an oxide film 44'&- is formed to a thickness of about 50 nm on the exposed surfaces of the drain formation region 40 and the source formation region 41. After that, for example, boron (B) is heated to an energy of 25 (KeV) and a dose of i.
xio15[cnL-2] level busy, drain formation region 4
During this implantation, ions are implanted into the field oxide film 38 and the gate electrode 43.
serves as a mask to confine ion implantation to both regions defined above.

Refer to FIG. 2(e), a surface preservation film 45 such as phosphosilicate glass (PSG) is applied to the base 31.
Provided on the entire surface.

A window for forming an electrode is provided in the iSi film 45, and a 5102 film 44' is formed at low temperature in place of the Sin film 44 from which the window is removed.

Next, heat treatment is performed for the purpose of activating the ions implanted so far and smoothing the surface of the PSG surface protective film 45. This heat treatment determines the depth of P-type activation in the drain region 40 and source region 41, and this heat treatment is performed in a nitrogen (N) atmosphere. It takes about 10 minutes.

Also, by this heat treatment, the P-type impurity introduced region 35 is separated from the P-type offset region 35 and the P-type low concentration region 35.
), the N-type impurity introduced region 37 becomes an N''ffi channel cut region 37.

Refer to FIG. 2(f), the SiO2 film 44' is removed, and a drain electrode 46, a source electrode 47, and a
Gate wiring 48 and the like are provided.

As is clear from the manufacturing process example described above, according to the present invention, since the drain region 40 is defined by the field oxide film 38, it is possible to eliminate variations in the width of the offset region as in the conventional example described above. Not only is this possible, but it also eliminates the need for a mask for selectively introducing impurities into the P+ type region.

Further, a thick field insulating film 38 is provided on the surface of the offset region 35, which alleviates the electric field concentration effect between the end of the gate electrode 43 and the drain region 40, and improves electrostatic resistance.

In the above embodiment, the P-type low concentration region 35' is provided between the drain region 40 and the channel cut region 37, separated from the channel cut region 2 region 37. Even when the region 35' is not provided or when the region 35' is in contact with the channel cut region 37, the present invention can be applied to achieve the object.

Furthermore, in the above embodiment, MO8FETk is formed on an N-type substrate, but it is obvious that it can be implemented similarly on an N-type well layer. The present invention can also be applied to MOS FETs.

ω) Effects of the invention 11-Sumi poles, 48 indicate gate electrode wiring 6 As explained above, according to the present invention, with respect to a high voltage MO8FET, each active region is formed with a field oxide film determined by a selective thermal oxidation mask. By separating and defining the feed oxide film and providing an offset region under the feed oxide film, variations in the width of the offset region and thus the channel resistance are suppressed and the characteristics thereof are made uniform;
Furthermore, the effect of alleviating electric field concentration between the gate electrode and the drain region can be obtained, and an increase in electrostatic capacity can be expected.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing a conventional example of a high voltage MO8FET.
FIGS. 2(a) to 2(f) I'i are sectional views showing the manufacturing process of an embodiment of the present invention. In the figure, 31 is an N-type silicon substrate, 33 is a silicon nitride film, 35 is a P-type offset region, 35' is a P-type low concentration region, 37 is a furnace type channel cut region, and 38 is a field oxidation J[, 40 4 is a drain region, 41 is a source region, 42 is a gate oxide film, 43 is a gate electrode, 44 is an oxide film, 45 is a PSG insulating film, 46 is a drain electrode, 4
7 is So 12- 342 5 83 1 Q floor Kanichi + Ha 343-

Claims (2)

[Claims] (1) A semiconductor substrate having a first conductivity type, a gate oxide film disposed on the surface of the substrate, a first semiconductor region in contact with the gate oxide film, and a semiconductor substrate disposed near the surface of the substrate. second and third semiconductor regions having a second conductivity i; Insulation that separates and defines each of the second and third semiconductor regions.
and is disposed under the insulating film, is in contact with the second or third semiconductor region and the first semiconductor region, and has a cine fines concentration higher than that of the second or third semiconductor region. a fourth and a fifth semiconductor region of a second conductivity type, which are selectively disposed under the insulating film other than the fourth and fifth semiconductor regions; 1. A semiconductor device comprising: a sixth semiconductor region of a first conductivity type having a large conductivity; and a fifth gate electrode extending over the insulating film on the previous semiconductor region. (2) disposed under the insulating film, in contact with or separated from the sixth semiconductor region, and in contact with the second semiconductor region, the impurity concentration is lower than that of the second semiconductor region; 2. The semiconductor device according to claim 1, further comprising a seventh semiconductor region of a second conductivity type. □