JPS5915135Y2 - pulse modulator - Google Patents

pulse modulator

Info

Publication number
JPS5915135Y2
JPS5915135Y2 JP1978172740U JP17274078U JPS5915135Y2 JP S5915135 Y2 JPS5915135 Y2 JP S5915135Y2 JP 1978172740 U JP1978172740 U JP 1978172740U JP 17274078 U JP17274078 U JP 17274078U JP S5915135 Y2 JPS5915135 Y2 JP S5915135Y2
Authority
JP
Japan
Prior art keywords
circuit
overload
pulse
load
detection device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1978172740U
Other languages
Japanese (ja)
Other versions
JPS5588539U (en
Inventor
克治 朝井
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1978172740U priority Critical patent/JPS5915135Y2/en
Publication of JPS5588539U publication Critical patent/JPS5588539U/ja
Application granted granted Critical
Publication of JPS5915135Y2 publication Critical patent/JPS5915135Y2/en
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 この考案はパルス変調器、特にその過負荷保護回路に関
するものである。
[Detailed Description of the Invention] This invention relates to a pulse modulator, particularly to its overload protection circuit.

従来の過負荷保護回路を有するパルス変調器として第1
図に示すものがあった。
The first pulse modulator with conventional overload protection circuit
There was something shown in the figure.

図において1は直流電源、2は充電回路、3はシャント
回路、4はサイラトロン等のスイッチ素子、5はパルス
成形回路(以下PFNと称する)、6はクライストロン
等の負荷、7はゲート回路、8はトリガー発振器、9は
過負荷検出回路である。
In the figure, 1 is a DC power supply, 2 is a charging circuit, 3 is a shunt circuit, 4 is a switching element such as a thyratron, 5 is a pulse shaping circuit (hereinafter referred to as PFN), 6 is a load such as a klystron, 7 is a gate circuit, and 8 9 is a trigger oscillator, and 9 is an overload detection circuit.

次に動作について説明する。Next, the operation will be explained.

直流電源1の直流電圧は充電回路2を通じてPFN5に
充電される。
The DC voltage of the DC power supply 1 is charged to the PFN 5 through the charging circuit 2.

トリガー発振器8からのトリガーはゲート回路7を通し
てサイラトロン等のスイッチ素子4を点弧させると、P
FN5に貯えられた電荷は5−4−6の回路を通じて放
電され負荷6にPFN5で定められたパルスが発生する
When the trigger from the trigger oscillator 8 passes through the gate circuit 7 and fires the switch element 4 such as a thyratron, P
The charge stored in FN5 is discharged through the circuit 5-4-6, and a pulse determined by PFN5 is generated in the load 6.

今負荷6に異常が生じ過電流が流れると過負荷検出回路
9によって過負荷が検出され7のゲート回路7を開いて
トリガーはスイッチ素子4に供給されない。
If an abnormality occurs in the load 6 and an overcurrent flows, the overload detection circuit 9 detects the overload, opens the gate circuit 7, and no trigger is supplied to the switch element 4.

このようにして負荷の異常を検出しトリガーを停止させ
パルス出力を発生させない。
In this way, an abnormality in the load is detected, the trigger is stopped, and no pulse output is generated.

尚、シャント回路3は異常時に生じた過電流によりPF
N5に貯えられた逆電荷を放電させるものである。
In addition, the shunt circuit 3 is closed due to overcurrent that occurs during abnormality.
This is to discharge the reverse charge stored in N5.

従来の装置はこのように過負荷保護回路を負荷回路に直
接接続し検出するものであるから必然的にパルスのピー
ク値検出をする必要があり、ゲート回路は複雑となり高
価となる欠点があった。
Conventional devices connect the overload protection circuit directly to the load circuit for detection, so it is necessary to detect the peak value of the pulse, which has the disadvantage of making the gate circuit complicated and expensive. .

この考案は従来の装置の上記のような欠点を除去する為
に威されたもので、シンプルで安価に過負荷保護を遠戚
する事を目的としている。
This invention was developed to eliminate the above-mentioned drawbacks of conventional devices, and aims to provide a distant relative of overload protection in a simple and inexpensive manner.

以下この考案の一実施例を図に基づいて詳細に説明する
An embodiment of this invention will be described below in detail with reference to the drawings.

即ち第2図において、10は過負荷検出装置で、シャン
ト回路3に流れる電流により抵抗に生ずる電圧を検出し
それに応じてゲーと回路7を開くものであり、例えばリ
レー等により構成されている。
That is, in FIG. 2, reference numeral 10 denotes an overload detection device which detects the voltage generated in the resistor by the current flowing through the shunt circuit 3 and opens the gate and circuit 7 accordingly, and is constituted by, for example, a relay.

そしてこの過負荷検出装置のリレー接点出力は、ゲート
回路7に供給されこのゲート回路7を開閉する。
The relay contact output of this overload detection device is supplied to a gate circuit 7 to open and close this gate circuit 7.

尚、1〜8は従来と同様である。Note that 1 to 8 are the same as the conventional one.

このように構成された装置に於て、負荷の異常により貯
えられた逆電荷はPFN5からシャント回路3を通じて
放出する。
In the device configured as described above, the reverse charge stored due to an abnormality in the load is discharged from the PFN 5 through the shunt circuit 3.

よってシャント回路3の抵抗に生じる電圧を過負荷検出
装置10により検出してゲート回路7を開き、トリガー
がスイッチ素子4に供給されるのを阻止し、従来と同様
にパルス出力を停止させるもので゛ある。
Therefore, the overload detection device 10 detects the voltage generated in the resistance of the shunt circuit 3, opens the gate circuit 7, blocks the trigger from being supplied to the switch element 4, and stops the pulse output as in the conventional case. There is.

このシャント回路3に流れる電流波形はパルス波形でな
く、PFN5の容量Cとシャント回路3の抵抗Rによる
時定数RCを有する波形となり過負荷検出装置10はリ
レー等による検出方法で十分でありシンプルで安価とな
る。
The current waveform flowing through this shunt circuit 3 is not a pulse waveform, but a waveform having a time constant RC due to the capacitance C of the PFN 5 and the resistance R of the shunt circuit 3.The overload detection device 10 is simple and sufficient to use a detection method such as a relay. It will be cheaper.

なお、上記実施例では過負荷検出装置10のリレー接点
出力をゲート回路7に供給しているが、この検出装置の
リレーそのものをゲート回路としても良い。
In the above embodiment, the relay contact output of the overload detection device 10 is supplied to the gate circuit 7, but the relay of this detection device itself may be used as a gate circuit.

以上のようにこの考案によれば、過負荷をシャント回路
の電流により検出するようにしたので複雑なパルスピー
ク検出の必要がなくシンプルでより安価に保護回路を構
威しえるものである。
As described above, according to this invention, overload is detected by the current of the shunt circuit, so there is no need for complicated pulse peak detection, and the protection circuit can be constructed simply and at lower cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の過負荷保護回路を有するパルス変調器の
回路図、第2図はこの考案の一実施例によるパルス変調
器の回路図である。 図において、1は直流電源、2は充電回路、3はシャン
ト回路、4はスイッチ素子、5はパルス成形回路、6は
負荷、7はゲート回路、8はトリガー発振器、10は過
負荷検出装置である。 なお図中同一符号は相当部分を示す。
FIG. 1 is a circuit diagram of a pulse modulator having a conventional overload protection circuit, and FIG. 2 is a circuit diagram of a pulse modulator according to an embodiment of this invention. In the figure, 1 is a DC power supply, 2 is a charging circuit, 3 is a shunt circuit, 4 is a switch element, 5 is a pulse shaping circuit, 6 is a load, 7 is a gate circuit, 8 is a trigger oscillator, and 10 is an overload detection device. be. Note that the same symbols in the figures indicate corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電荷を蓄積するパルス成形回路と、導通することにより
このパルス成形回路に蓄積された電荷を負荷を介して放
電させるスイッチ素子と、過負荷時に上記パルス成形回
路に蓄積された逆電荷を放電させるシャント回路と、こ
のシャント回路に流れる電流を検出する過負荷検出装置
とを備え、この過負荷検出装置の動作により上記スイッ
チ素子の導通を停止させ負荷へのパルス出力を停止させ
るようにしてなるパルス変調器。
A pulse shaping circuit that accumulates charge, a switch element that discharges the charge accumulated in this pulse shaping circuit through a load by being electrically connected, and a shunt that discharges the reverse charge accumulated in the pulse shaping circuit in the event of an overload. and an overload detection device that detects the current flowing through the shunt circuit, and the operation of the overload detection device stops the conduction of the switch element and stops the pulse output to the load. vessel.
JP1978172740U 1978-12-15 1978-12-15 pulse modulator Expired JPS5915135Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1978172740U JPS5915135Y2 (en) 1978-12-15 1978-12-15 pulse modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1978172740U JPS5915135Y2 (en) 1978-12-15 1978-12-15 pulse modulator

Publications (2)

Publication Number Publication Date
JPS5588539U JPS5588539U (en) 1980-06-18
JPS5915135Y2 true JPS5915135Y2 (en) 1984-05-04

Family

ID=29177804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1978172740U Expired JPS5915135Y2 (en) 1978-12-15 1978-12-15 pulse modulator

Country Status (1)

Country Link
JP (1) JPS5915135Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0691433B2 (en) * 1985-03-05 1994-11-14 日本電気株式会社 Transmitter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4970564A (en) * 1972-10-27 1974-07-08
JPS4978470A (en) * 1972-11-30 1974-07-29

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4970564A (en) * 1972-10-27 1974-07-08
JPS4978470A (en) * 1972-11-30 1974-07-29

Also Published As

Publication number Publication date
JPS5588539U (en) 1980-06-18

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