JPS59149428A - Phase controller - Google Patents

Abstract

PURPOSE:To shorten a pull-in time and improve start characteristics in the disturbance state of a control system without exerting any influence upon control characteristics in stationary operation by providing a minor control loop which has a phase correcting circuit. CONSTITUTION:The phase correcting circuit which inputs a reference signal R and an output signal C and operates as a correction limiting element is provided to constitute a loop which adds the output D2 of the circuit 6 to a control voltage D1 obtained through a feedback loop. This loop operates for minor control and adds a control voltage D2 for correction proportional to the phase difference between the signals C and R to the control voltage D1, thereby supplying the obtained control signal D to a controlled system 5 through an amplifying circuit 4. Consequently, the pull-in time of a phase controller is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a control method and circuit for shortening synchronization pull-in time in a phase control device.

[Prior art]

Generally, in a phase control device such as a servo control system, feedback control as shown in the block diagram of Fig. 1 is used to control the phase of a rotating object driven by a motor or the like, or a running object. I am doing it.

That is, in FIG. 1, the phase comparison circuit 2 compares the phases of the output signal C containing the phase information of the controlled object 5 and the reference signal R from the terminal 1 containing the reference phase information, and calculates the phase error. Input the signal E to a characteristic compensation circuit 6 such as a phase delay element,
A control voltage D1t- corresponding to the magnitude of the phase error is obtained, amplified by an amplifier circuit 4, and applied to a controlled object 5 such as a motor.
It is supplied as a driving voltage M.

However, even if the feedback control described above is simply performed, the output signal C will undergo a rapid state change at the start of a control operation or immediately after an excessive disturbance enters the control system, and as a result, the phase error signal E will change. Since the signal contains many high frequency components, it has the characteristics of a kind of low-pass filter.
However, there was a problem in that the phase 1 difference information was blocked by the circuit 3. Therefore, there have been inherent problems such as poor responsiveness of the phase control loop, particularly at startup, and a slow synchronization pull-in time.

[Object of the Invention] An object of the present invention is to provide a phase control device that improves the starting characteristics and shortens the synchronization pull-in time during starting without affecting the control characteristics in steady state at all.

[Summary of the invention]

In order to achieve the above object, the present invention provides a phase correction circuit that acts as a minor control for the feedback loose that mainly constitutes the phase control system, and uses the correction circuit to adjust the position between the output signal of the controlled object and the reference signal. A phase correction pulse having a pulse width corresponding to the phase difference is continuously outputted until the phase difference becomes zero, and control is performed based on the output.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 2 shows a block diagram of a phase control device employing the present invention, and FIG. 6 shows an embodiment of a phase correction circuit that is a feature of the present invention. Moreover, FIG. 4 is a diagram showing waveforms of various parts of this phase correction circuit.

The overall configuration of a one-phase control device employing the present invention will be explained with reference to FIG. In FIG. 2, the circuit blocks and signal names are the same as in the prior art example of FIG. 1.

It is indicated by the same reference numerals as in FIG. 1. The present invention differs from the prior art in that a phase correction circuit 6 is provided which takes the reference signal R and the output signal C as input signals and works as a correction control element, and its output D2t-1 is obtained within a normal feedback loop. This is because a loop is configured to add the control voltage D1 to the control voltage D1. This loop acts as a minor control over the original feedback loop. The function and effect will be described later, but the correction control voltage D2vf-1, which is proportional to the phase difference between the output signal C and the reference signal R, is added to the control voltage D1 due to the original feedback looseness, and as a control voltage, By inputting the signal to the amplifier circuit 4, the synchronization pull-in time of the phase control device is completely shortened.

Next, the features of the present invention will be described. The configuration of the phase correction circuit 6 will be explained in detail using FIG. 3. In FIG. 3, the same functional parts and signal names as in FIG. 2 are indicated by the same symbols as in FIG.

In FIG. 3, 7. is an input terminal for a signal X specifying the start of the operation of this phase correction circuit 6, and 8 is an input terminal for an output signal C of the controlled object 5 described above. 9 is a NAND gate to which the signal X and signal C are input, and its output Sx is
RS flip-flop 10 (hereinafter abbreviated as R5F1o)
and is input to the inverter 12.

Further, the signal X is input to the reset input side of R5F10. The output Q1 of the R5F1D is RS Free, Pflo.

The output Q1 is input to the reset input terminal of the D flip-flop 15 (hereinafter referred to as R5F11), which will be described later. 13 is a NAND gate,
The output of the inverter 12 and the D7 lip-flop 15 (
The output Q3 of the DFF 15 (hereinafter abbreviated as DFF 15) is input, and its output Sr is input to the set input side of the RsF 11. The above-mentioned R2T1 is connected to the reset input side of R5F11.
In addition to the output Q1 of 7, a reference signal R from terminal 1 is input. The reference signal R is also input to the clock input terminal of the DFF 15. Further, the output Q2 of R5T11 is inputted to the NPN) run raster 1f0 base via the resistor 16. The transistor 17 (hereinafter abbreviated as Trl 7) is an open collector output type. The emitter of the transistor 17 is grounded, and its collector is connected to the input of the circuit 4 via a resistor 18f. The output Q2 of R5T11 is also input to the inverter 14, and its output is
Input to input terminal. The DI'F 15 interrupts the output from the inverter 14 when the reference signal R falls.

The operation and characteristics of the phase correction circuit 6 whose configuration has been explained above will be explained using the waveform diagram of FIG. 4.

As shown in FIG. 4, when the circuit 6 is not operating, that is, when the signal X is 'L', R2T17 is reset and its output Q1 is 'L', so 7'? 5711
has been reset. Furthermore, since the output Q1 of R2T17 is 1'', the DF 115 is reset and its output Q3 is 1''. Also, since the output Q2 of R5F'X is 'L', Trl7 becomes non-conductive and b
Therefore, the phase correction circuit 6 is separated from the original main control loop.

Next, the start of operation of circuit 6 is specified, and the signal father goes to "L".
When it becomes “B”, )? AIVD gate 9 opens, and signal C from terminal 8 is inverted at gate 9 and output.

Output Sx from this gate 9 (Xl, X2 .
), R2T17 is set, and its W force Q1 changes from °゛L'' to 1B''. Also.

As mentioned above, since the output Q3 of the DFF15 is ``T'', the output Sx from the gate 9 is inputted to the R5T11 via the inverter 12 and the gate 13, and thereby,
R5T11 is set and its output Q2 goes from L” to B
”. After that, the reference signal R(
R5T by R1, R2, Rs,...) in Figure 4
11 is reset, and its output Q2 changes from B'' to 'L''. The period during which the output Q2 of
ψ6. ψ3. ) represents the amount of lead phase of the signal C with respect to the signal R.

The output Q2 of R5T11 is input to the base of Trl7, but during the period ψ when the output Q2 becomes "E", the pulses p, , 8, etc. in FIG.
τ17 becomes conductive, so that the input voltage of the circuit 4 decreases, and the output signal C of the controlled object 5 operates to be delayed in phase. As a result, the phase difference between the output signal C and the reference signal R decreases.

Thus, as shown in FIG. 4, the phase difference between the output signal C and the reference signal R is the pulse p, , P,.

... gradually decreases each time it is output, but once the signal C shifts to a phase delayed state (the relationship between pulses C4 and R4 in Fig. 4) with respect to the signal R, the signal R at that time (
R4) in FIG. 4 causes the DFF 15 to
Take in the data of output "B" from 4 and output it Q3.
becomes L from TS.

Therefore, the signal C(
signal Sx (pulse X4 in FIG. 4) based on signal Sx (C4 in FIG. 4)
) is inhibited at gate 15.

R5T11 is not set and its output Q2 remains at L''.

Therefore, from then on, while C3 is L'', the output Q2 of R5T11 remains L'', and Trl7 becomes non-conductive.
This phase correction circuit 6 is separated from the original main control loop, and the state in which the output signal C and the reference signal R are sufficiently close in phase is shifted to negative feedback control by the main control loop, so that the output Signal C and reference signal R are quickly brought into phase synchronization.

In addition, as mentioned above, R5T1
The period during which the generation of phase correction pulses (pulses p, , p, . . . in Fig. 4) from the Q2 output of 1 is inhibited is the period when the signal Q5 is "L", which is the period when the signal The signal X changes to "L" and the phase correction function is canceled. At the same time, R2T17 is reset, its Q1 output becomes "E", DFF15 is reset, and the signal Q
3 goes from L" to H".

Thereafter, the phase correction operation is started by changing the signal X to B'' again.

As explained above, in the phase control device, even if there is an influence of loop interruption by the circuit 3, the reference signal R and Since the phase correction function operates to compare the phase of the output signal C having a phase error and make the phase difference zero, the synchronization pull-in time can be shortened. Furthermore, this circuit is disconnected from the main control loop during steady state, and has no effect on the control characteristics during steady state.

Furthermore, in this embodiment, based on the phase correction pulse,
Although the method of correcting the control voltage was shown above, the phase correction pulse is input to the input terminal of the drive circuit that specifies the forward or reverse rotation direction of the motor, etc., and reverse braking is applied to the drive body such as the motor. In addition, it is also possible to perform sudden braking using dynamic braking to achieve the same full phase correction function.

Further, in the above embodiment, the phase correction is performed by decelerating a rotating body such as a motor, but conversely, in FIG. 3, the terminal 1
Input signal C to terminal 8, reference signal R'fr to terminal 8, and input signal C to terminal 8.
A pulse having a pulse width proportional to the amount of phase delay with respect to the reference signal R is generated in the same way as above in R5F11, and
Although the output is not shown, it is connected to the circuit 4 via a 7) 7vP transistor of opposite polarity to Trl 7, and the phase is corrected by accelerating a driving body such as a motor according to the amount of phase delay. However, the gist of the present invention is not deviated from the spirit of the present invention even in the case of deviation b.

〔Effect of the invention〕

As explained above, according to the present invention, in a phase control device or the like, even if the control system falls into a disturbed state such as during startup, the synchronization pull-in time can be maintained without affecting the control characteristics during steady state. It can be shortened and the startup characteristics can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional phase control device, FIG. 2 is a block diagram of a phase control device according to the present invention, FIG. 3 is a block diagram of an embodiment of a phase correction circuit that is a feature of the present invention, and FIG. The figure is a waveform diagram of each part.

Claims (1)

[Claims] 1. In a control device that phase-synchronizes a detection signal containing phase information from a controlled object with a reference signal containing reference phase information, obtaining a phase error signal between the detection signal and the reference signal, and a main control loop that performs negative feedback control on the controlled object based on the reference signal; having means for stopping output of the pulse signal after the detection signal becomes phase delayed (or phase advanced) with respect to the reference signal;
A phase control device characterized in that it has a sub-control loop configured to correct the amount of operation on the controlled object so as to act preferentially over the main control loop based on the pulse signal from the above-mentioned means. . 2. In the phase control device according to claim 1, there is provided a flip-flop circuit that is set (or reset) by the detection signal and reset (or set) by the reference signal; It has a latch circuit that latches the output from the flip-flop circuit based on the reference signal (or detection confidence) when the lead-lag relationship is reversed, and the output of the flip-flop circuit is adjusted based on the output from the latch circuit. A phase control device characterized by stopping the set (or reset) operation.