JPS59149051A - Orthogonal synchronous detection circuit - Google Patents

Abstract

PURPOSE:To obtain a synchronous detection circuit which can be demodulated to a modulated wave signal, an envelope of an orthogonal modulated wave signal therein is made constant, such as MSK, OQPSK, etc. by a simple constitution. CONSTITUTION:An orthogonal modulated wave signal is inputted to the data terminals (D) of flip-flops FF1-FF4 from an input terminal IN, and signals of phase of each 0, pi/4, pi/2, 3pi/4 as reference carrier waves are transmitted over the clock terminals (C) of the flip-flops FF1-FF4 as outputs from a shift register SR from a phase-shift circuit PSF. The flip-flop FF1 sets the orthogonal moculated wave signal by a clock of 0 phase and the flip-flop FF2 it by a clock of pi/2 phase, and the flip-flop FF3 sets it by a clock of pi/4 phase, and the flip- flop FF4 sets it by a clock of 3pi/4 phase. An output from a multiplier M5 obtained through multipliers M3, M4 is inputted as the control voltage of a voltage control oscillator VCO through a loop filter LF, and an output from the voltage controloscillator VCO functions as an oscillating output synchronizing with the carrier wave phase of the orthogonal modulated wave signal inputted to the input terminal IN.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a quadrature synchronous detection circuit for demodulating a modulated wave signal of constant amplitude such as an MSK signal.

Conventional technology and problems As a modulation method for transmitting digital signals over wireless lines, MSK (Minimum 5hift K
eying), B P S K (Binary Ph
ase 5hift Keying), QP S
K (Quadrature Phase 5hift
Keying ), and OQ P S K (Of
fset Quadrature Phase Shi
ftKeying) and the like are known. FIG. 1 shows a conventional synchronous detection circuit for orthogonal modulated wave signals using the various modulation methods described above. For example, a 4-phase PSK modulated wave signal applied to the input terminal IN is applied to multipliers M1 and M2, and The output signal of the voltage controlled oscillator VCO is used as a reference carrier wave to multiplier M1, and the reference carrier wave is used as a π/2 phase shifter p.
s to the multiplier M2, respectively, and the in-phase component and quadrature component are outputted from the multipliers M1 and M2, respectively, and the output of each multiplier MIM2 is sent to the rover and the filter FTL1. FI
(2) Discriminator DS1. through L2. The data is added to DS2, and the identification results are output as reproduced data datal and data2.

Further, the sin θ signal component and the cos θ signal component of the outputs of the multipliers Ml and M2, from which unnecessary components have been removed by the low-pass filters FILL and FIL2, are added to the adder AD and the subtracter SB, and are added to the adder AD. is sinθ+cos
θ is output, and the subtracter SB outputs sin θ−cos θ
are output, and the respective discriminators DS3. Added to DS4. The outputs of the discriminators DSL and DS2 are applied to a multiplier M3, and the outputs of the discriminators DS3 and DS4 are applied to a multiplier M4. The output of multiplier M3 is 5
in2θ, the output of multiplier M4 becomes a signal corresponding to cos2θ, and these signals are converted into sin2θ by multiplier M5.
This becomes a signal corresponding to 4θ. This signal becomes a control signal for the voltage controlled oscillator VCO via loop filters I and F, and becomes an oscillation output signal whose phase is synchronized with the carrier wave of the input modulated wave signal.

Here, θ is the phase modulation component and the quadrature modulation signal (3) It means the sum of phase errors θD with respect to the reference carrier wave.

Although such a conventional circuit can demodulate an orthogonally modulated wave signal which is hydrofluoric acid limited and whose envelope line is constant, it has the disadvantage of a complicated configuration.

Purpose of the Invention It is an object of the present invention to make it possible to demodulate a modulated wave signal such as MSK, 0QPSK, etc., in which the envelope of the orthogonal modulated wave signal is constant, with a simple configuration. It is something. Examples will be described in detail below.

Embodiment of the Invention FIG. 2 shows the configuration that is the premise of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts, M6 and M7 are multipliers, FIL3 . FTL4 is a low pass filter, Psi, P
S2. PS3 is a phase shifter of 3π/4, π/2, and π/4, respectively. The QPSK modulated wave signal applied to the input terminal IN is applied to the multipliers Ml, M2 . M6. is input into M7,
From the multipliers Ml and M2, similar to the case shown in FIG.
(4) Components corresponding to sin θ and cos θ are output. Also, multiplier M6. From M7, sin (θ−tπ/
4), a component corresponding to cos(θ+π/4) is output. Therefore, from the multiplier M3 that performs the calculation of sin θ ■ cos θ (■ indicates exclusive OR), the component corresponding to 5in2θ is obtained, and the component corresponding to 5in2θ is also calculated as sin (θ1π/4) ■ cos (θ + π/4). Multiplier M4 outputs components corresponding to (5in2 (θ→−π/4))=cos2θ, respectively.

Also, the output components of these multipliers, 5in2θ and cos
The 2θ components are multiplied again by multiplier M5, and
By calculating in2θ[F]cos2θ, an output corresponding to the 5in4θ component is obtained.

In addition, the orthogonal modulated wave signal whose envelope is constant is
If the bit rate is 1/T, π is continuously
Since the phase changes linearly by /2, if the quadrature modulated wave is sampled with the 0-phase and π/2-phase clocks, the in-phase component and quadrature component data datal, da
ta2 can be obtained (5). For this reason, the present invention has the configuration shown in FIG. 3. In Figure 3, IN is the input terminal, F
FI to FF4 are flip-flops, LF is a loop filter, M3 to M5 are first to third multipliers, VCO is a voltage controlled oscillator, DV is a frequency divider, SR is a shift register, PS
F is a phase shift circuit. The orthogonal modulation wave signal is input to the input terminal IN
are input to the data terminals of flip-flops FFI to FF4, and reference carrier waves O1π/4 . Signals with phases of π/2 and 3π/4 are added as outputs of the shift register SR.

The phase shift circuit PSF is composed of a frequency divider DV and a shift register SR.
The frequency is divided by 8 by V and used as the input signal of the shift register SR, and the output of the voltage controlled oscillator vCo is used as the shift clock of the shift register SR. Signals with phases of π/4, π/2, and 3π/4 are output (6).

Flip-flop FFI is O phase, flip-flop FF
2 sets an orthogonal modulation wave signal using a π/2 phase clock, and the Q terminal output of the flip-flop FFI is the in-phase component data datal corresponding to the output of the discriminator DSI in FIG. The Q terminal output becomes orthogonal component data data2 corresponding to the output of the discriminator DS2 in FIG. These data are sent to multiplier M3
is input. Also, since flip-flop FF3 sets the orthogonal modulated wave signal using a π/4 phase clock, and flip-flop FF4 is set using a 3π/4 phase clock, the Q terminal output of flip-flop FF3 is as shown in FIG. It corresponds to the output of the discriminator DS3,
Further, the Q terminal output of the flip-flop FF4 corresponds to the output of the discriminator DS4 in FIG. Therefore, the multiplier M
3. M4. The output of M5 corresponds to the output of the multiplier with the same sign in FIGS. 1 and 2, and the output of the multiplier M5 becomes the control voltage of the voltage control (7) oscillator VCO via the loop filter LF. Therefore, the output of the voltage controlled oscillator VCO becomes an oscillation output synchronized with the carrier phase of the orthogonal modulated wave signal input to the input terminal IN.

Although the above-described phase shift circuit PSF is constructed from a frequency divider DV and a shift register SR, it is also possible to adopt other constructions.

As mentioned above, the orthogonal synchronous detection circuit according to the present invention has 0
It is possible to apply the present invention to systems that employ either QPSK or MSK modulation method.

As is well known, in a 4-phase 0QPSK modulated wave, 5 inches
(ωt+nπ/2+θn) (n'=O, l, 2
．． The component corresponding to 3) is obtained as the output after synchronous detection. Here, nπ/2 is a phase modulation component, and θ0 is a phase difference component between the orthogonal modulation signal and the reference carrier wave.

Therefore, by multiplying this by 4 using the logical processing according to the present invention,
It is possible to cancel nπ/2 of the phase modulation component.

On the other hand, for MSK modulated waves, the output after synchronous detection is (8) sin(ωt±2πfb-t/4+θn) (note that f
b is the clock frequency of the data).
The component corresponding to -t remains as is. However, this 2πrb- component is extracted simultaneously with 4θ,
Since the frequency is sufficiently high compared to , it can be easily removed by a loop filter LF consisting of a low-pass filter.

For the above reasons, the orthogonal synchronous detection circuit according to the present invention can be applied to orthogonal synchronous detection of MSK modulated waves as well as conventional circuits.

Effects of the Invention As explained above, the present invention has four flip-flops F which input orthogonal modulation wave signals whose envelopes of modulation methods such as 0QPSK and MSK are constant to their respective data terminals.
F1 to FF4 and the four flip-flops FFI to F
To the clock terminal C of F4, a reference carrier wave,
0. π/4° (9) Regenerate and output the output of the phase shift circuit PSF for adding clocks with phases of π/2 and 3π/4, and the flip-flops FFI and FF2 that add clocks with phases of 0 and π/2. and a first multiplier M3 which adds the outputs thereof, and a flip-flop FF3 . The second one that adds the output of FF4
multiplier M4, and the first and second multipliers M3. M4
a third multiplier M5 that adds the output of
5 is applied as a control voltage via a loop filter LF, and the voltage controlled oscillator VCO applies the output to the phase shift circuit PSF, and can perform synchronous detection of orthogonal modulated wave signals with a simple configuration. It is something that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional synchronous detection circuit for orthogonal modulated wave signals, and the second TI! J is a block diagram of a synchronous detection circuit which is a premise of the present invention, and FIG. 3 is a block diagram of an embodiment of the present invention. FF1 to FF4 are flip-flops, LF is a loop (10) filter, M3 to M5 are multipliers, VCO is a voltage controlled oscillator, PSF is a phase shift circuit, DV is a frequency divider, and SR is a shift register. Patent applicant Gobe Tamamushi, representative patent attorney for Fujitsu Ltd., and 3 others (11)

Claims (1)

[Claims] In an orthogonal synchronous detection circuit that synchronously detects an orthogonal modulated wave signal whose envelope line is constant, four flip-flops each input the orthogonal modulated wave signal to a data terminal, and clock terminals of the four flip-flops are connected to each other. a phase shift circuit for adding clocks of respective phases of O9π/4°π/2.3π/4, which are reference carrier waves; 1 multiplier, a second multiplier that multiplies the outputs of the flip-flops that add the clocks with phases of π/4 and 3π/4, and a third multiplier that multiplies the outputs of the first and second multipliers. A quadrature synchronous detection circuit comprising: a voltage controlled oscillator which applies the output of the third multiplier as a control voltage via a loop filter and applies the output to the phase shift circuit.