JPS59144090A - Stack memory device - Google Patents

Abstract

PURPOSE:To attain a memory access using the increment or decrement value and to accelerate the memory access by using selectively plural pointer registers to perform an access to a stack memory. CONSTITUTION:Pointer registers 12a-12c showing the addresses of a stack memory 14 are provided along with addition/subtraction circuits 18a-18c which add or subtract (1) to and from the contents of each pointer register, and a stack control circuit 22 for each addition/subtraction circuit. Then one of registers 12a-12c is defined as a reference register, and other pointer registers are controlled so that they have the contents obtained by adding or subtracting (1) to or from the contents of the reference register. The access of the memory 14 using an address obtained by adding or subtracting one by one to or from the contents of the reference register is carried out by using selectively the pointer registers which received addition or subtraction.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a stack memory device, and is intended to speed up stack access by providing a plurality of pointer registers indicating stack memory addresses.

Prior Art and Problems Stacks are used in computers to temporarily store data read from main memory or to temporarily save register contents when an interrupt occurs. Stack memory is essentially ordinary memory, with addresses and data storage areas, but the way it is accessed is slightly different.

That is, while a normal memory is accessed randomly, a stack uses a method in which access is made sequentially, that is, if a certain address is accessed, the next address is accessed using an address that is +1 or -1 from that address. FIG. 1 is a block diagram showing an overview of a conventional stack memory device.
0 is a central processing unit, 12 is a pointer register, 14 is a stack (memory), and 16 is a data register. To access stack 14, central processing unit 10 writes an address to register 12 through line 11, and accesses stack 14.
4 is accessed by the address, that is, the contents of the register 12, and in the case of reading, the data read from the stack 14 is taken into the central processing unit 10 via the register 16,
In the case of writing, data sent by the central processing unit 10 to the register 16 is written to the stack 14. The next access causes the central processing unit to instruct pointer register 12 via line 12 to increment or decrement its contents;
This is often done using an address that is one larger or one smaller than the above address. Access to a distant address is performed by the central processing unit 10 setting the address in a pointer register.

Stack memory A stack whose main purpose is to temporarily save the contents of registers in particular and restore them again (control stack)
, there are very many increment or decrement accesses. Considering the time required to access the stack, when accessing by loading an address into the pointer register, the instruction is read, decoded, and executed (that is, loaded), and the stack is accessed by this, and the stack is accessed by incrementing or decrementing. Similarly, reading, decoding, and executing the instruction in question involves +1 or -1 processing, stack access based on the processed register contents, and requires the same machine cycles as loading.

OBJECTS OF THE INVENTION The present invention aims to improve the disadvantage that even in the case of a stack address by incrementing or decrementing, an address signal for the stack is generated after an operation is performed on a pointer register, resulting in a delay in stack access. .

Structure of the Invention The present invention provides a stack memory device having a pointer register indicating an address of a stack memory and an addition/subtraction circuit for adding or subtracting 1 to the contents of the pointer register, in which a plurality of sets of pointer registers and addition/subtraction circuits are provided,
In addition, a control circuit for these adder/subtracter circuits is provided, and one of the pointer registers is set as a reference register, and the other pointer registers are controlled to add and subtract 1 from the contents of the reference register, so that the contents of the reference register are The access to the stack memory using the address added or subtracted by 1 is performed by selectively using the pointer register which is added or subtracted by 1 to the contents of the reference register. This will be explained with reference to.

Embodiment of the invention FIG. 2 shows an embodiment of the invention. The same parts as in FIG. 1 are given the same reference numerals. As is clear from a comparison with FIG. 1, in the present invention, three pointer registers are provided, each of which is provided with an addition/subtraction circuit 18a-18C, and a selection circuit 20 and a stack control circuit 22 for these registers.

In this example, one pointer register 12a is used as a reference, and the other two registers 12b and 12c have values that are incremented or decremented, that is, values that are +1 and -1 from the contents of the reference register 12a.

In this circuit, in the case of access based on the contents of the reference register, the stack control circuit 22 sends the selection circuit 20 to the reference register 12.
Instruct to select a. On the other hand, in the case of access using a value obtained by decrementing the contents of the reference register, the selection circuit 20 selects the register 12b, and at the same time the addition/subtraction circuit 1
8a to 18c contain 1 of the contents of each register 128 to 12C.
In the case of access by incrementing the contents of the reference register by instructing subtraction, the selection circuit 20 selects register 1.
2C is selected, and at the same time instructs the addition/subtraction circuits 18a to 18c to add 1 to the contents of each register.

When accessing the stack by storing a new value in a pointer register, the value is stored in the pointer registers 128 to 12C, and then the selection circuit 20 selects the register 12a, subtracts 1 to the addition/subtraction circuit 18b, and subtracts 1 to the addition/subtraction circuit 18C. Instructs to add 1.

To explain this with a concrete example, as shown in Figure 3, command 1
Load address 100 into the pointer register, instruction 2 reads the address that is +1 to the contents of the pointer register, and instruction 3 further reads the address that is +1 to the contents of the pointer register. Instruction 1 is read, decoded, and executed, and address 100 is loaded into pointer registers 12a-12c.

Pointer registers 12a to 12C from central processing unit 10
This means that the data (address) sent to is the same. 3 data transfers are required to make the data different), so at the time of the above loading, the pointer registers 12a to 12c
The contents are all the same and are 100 in this example. The contents of the registers are updated in the next machine cycle, and the contents of the reference register 12a remain as they are, and the contents of the decrement and increment registers 12b and 12C are incremented by -1 and +1 to become 99,100. Although not mentioned in this example, if the next instruction is a stack access, the selection circuit 20 selects the reference register 12a, and stack access is performed using its contents 100 as an address.

In this example, the next instruction 2 is PR+1 read, and the period T2
This instruction is read, decoded, and executed. The above register update overlaps with this read cycle. Since instruction 2 is a P R+ 117- code, execution is performed by the register 12c with the content of +1, that is, the stack 14
Address 101 is read out. Next, in period T3, instruction 3 is sequentially output, decoded, and executed. During this sequence, registers are updated, in this case, +1 processing is performed on all registers 128 to 12C, and the execution is executed when the instruction is PR1+117.
Since it is a - code, the register 12C having the content of +1 is used. After executing this instruction, all registers are updated. As is clear from Fig. 3, if the instruction requires incrementing and accessing, an increment register can be used, and this instruction is decoded and processed by +1.
There is no need for a two-step process of subsequent access.

The same applies to the case of decrementing and accessing, there is no need to perform -1 processing and access, and a one-step operation of selecting the decrement register is sufficient. In this way, according to the present invention, the stack access time can be shortened.

Also, set an address in the pointer register, access the stack with that address, then access the stack with the incremented address, access the stack with the incremented address, etc.
In this case, the selected pointer registers are 12a, 1
2c, 12c..., set an address in the pointer register, access the stack with that address, then access the stack with the decremented address, and then access the stack with the decremented address. In this case, the selected pointer registers are 12a, 12b, 12b, etc.
・It is. This is followed accordingly, and register updating is performed during the read cycle of the next instruction. In the case of pipeline processing, the execution of the preceding instruction and the reading of the subsequent instruction are performed in parallel, so this is slightly different from the above, but the execution cycle usually takes 2 to 3 machine cycles, and then the stack access is completed. Since the contents of the sloppy pointer register can be changed, even in the case of vibe line processing, the third
In other words, shortening of access time can be expected. Although three sets of pointer registers are provided in the embodiment, three or more sets may be provided by adding a pointer register storing +2.

As described in detail, according to the present invention, three pointer registers are prepared, one of which is a reference register, and the remaining two have values obtained by subtracting 1 and adding 1 to the contents of the reference register. Therefore, accessing the stack using an increment or decrement value can be performed by selecting a pointer register, and the effect of speeding up stack access can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of a conventional stack memory device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation. In the drawing, 10 is a central processing unit, 12 is a pointer register, 14 is a stack memory, 16 is a data register, 18
2 is an addition/subtraction circuit, 20 is a selection circuit, and 22 is a stack control circuit. 0 ('') ('J - 000 ◆ Pot life Q-Kan

Claims (1)

[Claims] A pointer register indicating the stack memory address,
In a stack memory device having an addition/subtraction circuit that adds or subtracts 1 to the contents of the pointer register, a plurality of sets of pointer registers and addition/subtraction circuits are provided, a control circuit for these addition/subtraction circuits is provided, and one of the pointer registers is The reference register is used as a reference register, and other pointer registers are controlled to add or subtract 1 from the contents of the reference register, and access to the stack memory using an address that adds or subtracts 1 from the contents of the reference register is based on the contents of the reference register. 1. A stack memory device characterized in that execution is performed by selectively using a pointer register that is added or subtracted by 1 to .