JPS5914360A - Booster circuit - Google Patents

Abstract

PURPOSE:To raise the voltage of a power source to four times value or larger with a simple configuration by providing a first capacitor charged by the voltage of the power source and a second capacitor connected in series with the first capacitor in three or more stages. CONSTITUTION:A first booster circuit is composed of a capacitor C1 charged by the voltage of a power source, a capacitor C2 and MOS transistors Tr1-Tr4, a second booster circuit is composed of capacitors C3, C4, MOS transistors Tr5- Tr6, and a third booster circuit is composed of capacitors C5, C6 and MOS transistors Tr9-Tr12. A clock signal is alternately varied in high and low level stages, and the transistors Tr1-Tr12 are alternately turned ON and OFF in response to the state, thereby obtaining four times of the output voltage of the power source E from a capacitor C6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a booster circuit that boosts an input voltage by four times or more.

[Technical background of the invention]

Generally, booster circuits are known to consist of diodes and capacitors, but in small electronic devices such as electronic watches, silver batteries are used as the power supply source, so the supplied voltage is It is extremely low at 1.5V.

[Problems with background technology]

Additionally, some display devices for watch ICs (integrated circuits) used in recent electronic wristwatches require a voltage of 6V, but circuits that quadruple the input voltage have not been considered in the past. .

[Purpose of the invention]

Jin's invention was made in view of the above points, and its purpose is to provide a booster circuit that boosts the input voltage by four times.

[Summary of the invention]

A first capacitor charged (by the power supply voltage) and a second capacitor connected in series to the first capacitor are
A power supply voltage is alternately applied to the first capacitor and an input voltage is alternately applied to the series body of the first and second capacitors.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the basics of a booster circuit. In the figure,
Input voltage VIN is taken out as output voltage votrt via switch SW, capacitor C1, and switch SW4. Power supply voltage VIAT h is input to the connection point between the capacitor CI and switch SW4 via switch SW1.

Further, the connection point between the switch SW2 and the capacitor C1 is grounded via the switch SW3. Furthermore, the connection point between the switch SW and the output VOUT is the capacitor C.
! grounded via.

FIG. 2 shows a quadruple booster circuit according to the present invention, in which the clock signal -
5 is input to the dirt electrode.8) Transistor Tr1, switch SW.

An n-channel MO8) transistor Tr2, in which the clock signal φ is inputted to the dart electrode, serves the function of
A p-channel MO in which a clock signal φA is input to the dirt electrode as a device that functions as a switch SW (8), an n-channel MO in which a clock signal φA is input to an f-) electrode as a device that functions as a run source Tr3 and a switch sw4. This is done by the lungisme Tr4. Second
The figure shows the booster circuit shown in Figure 1 connected in three stages.
A clock signal stone is input to the dart electrode as a function of the second-stage switch SW of the n-channel MOS transistor Tr5.A clock signal φ is input to the dart electrode as a function of the second stage switch SW. The clock signal φ serves as the h-channel MOS transistor Tr6 and the second stage switch SW.
p-channel MO8) transistor Tr7 in which B is input to the dart electrode; clock signal φB is input to the dart electrode as a function of the second stage switch sw4;
Channel MO8) is implemented by transistor Tr8. An n-channel MO whose clock signal 5 is input to the f-) electrode serves as the third stage switch SW1.
8) An n-channel MO in which the clock signal φC is input to the dart electrode as a transistor that functions as a transistor Tr9, a switch SW in the third stage; A p-channel MO8 in which the signal φC is input to the gate electrode.
) Transistor TrJc A clock signal φC is input to the n-channel MOS transistor Tr12 to function as the third stage switch SW4.

Next, the present invention configured as described above will be explained in detail. First, the operation of the booster circuit shown in FIG. 1 will be explained. First, the switches SW and SWs are closed and the capacitor CIK power supply voltage v1 is charged. Next, when switches SW and SWs open and switches SW and SW4 close, capacitor C! is the input voltage (VI
N) 10 power supply voltage (Vmm unevenness is charged.

Next, the operation when boosting the voltage by four times will be explained using FIG. The operation of the circuit shown in FIG. 2 will now be described assuming that the clock signal φA=φm=φC=φ.

It is assumed that the capacitances of capacitors C1 to C6 are all equal, and the voltages v1 to v6 are respectively set by capacitor C! The voltage is set to be charged to ~C-.

Here, consider the case where the black signal φ changes from low level to high level. And, Kuro ypm φ is a loan (capacitor C1 before changing to Lucara Hi-Rail)
The charging voltage of C6 is Vl(N-1) ~ vs(N
-1), the voltage after the clock signal φ changes from o = L/bevel to high level is Vl (N) ~ Va (N)
In this case, the following relationship holds true.

Vl (N)' = V (N) = EVz (N) + V
s(N)-Va(N)=O・V4(N)+V5
(N) −Vs (N) = ()Vs(N)+V鵞(
N) Vs(N)=Vz(N 1)Vs(
N)+V4 (N)-Vs (N)=V4 (N-1)
Vs (N) +Vs (N) =V+ (N-1)-
EHowever, V, (N-1)=V, (N-1)=V, (
When N-1)=-E, the following equation is obtained.

Vs @= (5Vl (N-1)+2V4 (N-1
)+V@(N-1)+7E)/13Vj(N)=
(5V2(N-1)+2V4 (N 1 )+Vs (
N1) 6K)/13Vs(N)=(3V2(N
-1)+V4(N-1)+2Vl(N1)+E)
/13Va@”= (2Vl (N 1 ) +6V4
(N-1)+3Vs (N1) 5F)/1
3VsH= (Vl(N 1 ) 3V4 (N 1
)+5V8 (N 1)4E )/13Vs @=
(Vl (N-1)+3V4 (N-1)+8Vs (
N1)-9E)/13Here, the input pulse is 1
Each time the voltage changes from a low level to a high level, the lightning pressures v1 to v6 take on the above-mentioned new values. As is clear from FIG. 2, the output voltage V01 pvo! #VO8 is equal to v, e v4# "6, respectively. Here, the voltage v
The calculation result with the initial condition that 1 to v6 are all zero is the fourth
As shown in the figure.

Note that %E=1.5V.

Next, a modification of this invention will be explained using FIG. In the same figure, one more step-up circuit is added to the one shown in FIG. 2 to boost the input voltage and voltage by 45 times.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and by adding a booster circuit, a booster circuit with a capacity greater than 100% can be realized.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a booster circuit capable of boosting an input voltage by four times or more with a circuit configuration of a few square meters.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basics of a booster circuit, Fig. 2 is a diagram showing a booster circuit showing an embodiment of the present invention, Fig. 3 is a diagram showing a modified example of the invention, and Fig. 4 is a diagram showing a clock signal. FIG. 3 is a diagram showing changes in output voltages VOI to VOI with respect to φ. Tri, Tr2. TrJ, Tr5. Tr6. Tr8eT
r9*Tri O, T r 12・=n channel MO8
) transistor, TrJ, Tr7. TrJJ-p channel MO8) Lanzosta.

Claims (1)

[Claims] a first capacitor charged by a power supply voltage; means for supplying an input voltage to the first capacitor and a second capacitor connected in series to the first capacitor; 9. A booster circuit comprising means for connecting three or more stages of circuits each comprising a capacitor.