JPS59143475A - Method for reducing number of lines of picture signal - Google Patents

Abstract

PURPOSE:To reduce a picture signal with 3 lines or more to the one consisting of only one line to convert a reproduced picture into a proper picture signal by providing a facsimile device with a subscanning line density converter. CONSTITUTION:A picture of an original is read out by an optical sensor 1 in the fascimile device, amplified and waveform-shaped by an amplifier 2 and then inputted to a binary-coding circuit 3. The circuit 3 converts the picture information into a binary signal and the subscanning line density converter 4 executes line number reducing processing which converts four lines into one line in regard to said signal. An encoder 6 encodes and compresses the line-reduced signal through a read/write buffer memory 5 and sends the compressed signal to a communication line. The density converter 4 is constituted of four buffer memories BU1-BU4 storing binary signals for one line, a buffer controller BUC controlling read/write of binary signals for one line and a logical processing circuit CLO. Thus, a picture signal with 3 lines or more is reduced to the one consisting of only one line to convert the reproduced picture into a proper picture signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to the compression of image signals in image reading by facsimiles and the like, and particularly to the reduction of the number of image signal lines by reducing several lines of image signals to one line of image signal.

■Prior art For example, in a facsimile machine, there are cases in which the calligraphic information read by the reading device is processed (transmitted) as is, and cases in which the sub-scanning resolution is lowered for the purpose of increasing the transmission speed, that is, a continuation of the read calligraphic information. In some cases, two lines (A, B) are reduced as one line (C), and each pitch 1-C of the signal is obtained through various processes as described below.

C,'; = B';, x c zero - 1 + A;.

C'W = A zero x CW-, + Bq.

C enemy=A":+B":.

C blasphemy == A’m, or (,’=Ben.

However, these methods create a 1-line image signal from a 2-line image signal, and there is no conventional method for reducing the number of lines to obtain a 1-line image signal from a 3-line image signal. Conventionally, there is no method for reducing the number of lines in which an image signal of one line or several lines is created by referring to an image signal of .

However, recently there is a demand for high-resolution image reading. For example, if an image is read at 16 dots/mm in the main scanning direction and 15.4 lines/mm in the sub-scanning direction, this is compared to the conventional main scanning 8. When transmitting to a facsimile with dots/mm and sub-scanning speed of 3.85 lines/mm, it is necessary to reduce 2 bits to 1 bit in the main scanning direction and reduce 4 lines to 1 line in the sub-scanning direction. .

■Purpose The first object of the present invention is to provide a method for reducing the number of lines of an image signal, which can reduce an image signal of 3 or more lines to a 1-line image signal. A second object of the present invention is to provide a method for reducing the number of lines of an image signal by which an image signal of one line or several lines can be created.

■Configuration The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an outline of the configuration of an apparatus implemented in an embodiment of the present invention. In FIG. 1, an image of a document is read by an imaging device 1 equipped with an optical sensor, such as a CCU (charge coupled device), amplified and waveform-shaped by an amplifier, and converted into image information by a binarization circuit 3. It is converted into a binary signal (high level 1 or low level 0) indicating presence or absence. The binary signal is subjected to a line number reduction process by a sub-scanning line density converter 4, in this example, converting four lines into one line, and then passed through a read/write buffer memory 5 and encoded and compressed by an encoder 6. It is sent out to the communication line through the modem 7.

FIG. 2 shows the configuration of the sub-scanning linear density converter 4.

In this embodiment, each of the sub-scanning line density converters 4 has one
4 buffer memories (shift registers or R'A"M) that can store binary signals for lines B U 1~
BU4, logic circuit CLO and buffer memory BUI
-BU4 each includes a buffer control BUC that controls reading and writing of one line of binary signals.

In this example, the buffer control BUC controls the first line (Az), the second line (B1) and the third line (C
The binary signals of 1) are respectively stored in buffer memories BU3. 'B
When stored in U2 and BUI, in synchronization with the arrival of the binary signal on the fourth line (Dl), the binary signal is read out one bit at a time from each buffer memory BUI to BU4 and given to the logic processing circuit CLO, and then processed for logic processing. The output c-OUT is stored in the buffer memory BU4. Output C-0UT at this time
is the output E1 for one line obtained by reducing the image signals of four lines (A1 to Dt) of the first group to one line.

The buffer control f3uc then controls the fifth line (
A2 ), 6th line (B2) and 7th line (C2
) are respectively stored in the buffer memory BU3. BU2
and BUI, in synchronization with the arrival of the binary signal on the 8th line (B2), the binary signal is read out one bit at a time from each buffer memory BtJ1 to BU4 and given to the logic processing circuit cr-o, and The logic processing output C-0UT is stored in the buffer memory BU4. Output C-OU at this time
T is an output E2 for one line obtained by reducing the image signals of four lines (A2 to D2) of the second group to one line.

Similarly, when the next three lines of image signals are stored in the buffer memories BU3, BU2 and BU1, the buffer control BUC stores the memories BU] to 4 in synchronization with the arrival of the next line of image signals. The output C-0UT is stored in the memory BU4 while reading out one bit at a time.

FIG. 3 shows a CLOI consisting of m logic processing circuits CL○. In this example, the logic processing circuit CL○1 operates as an ant gate AN which calculates the AND of the image signals of the first line and the second line of an image signal group in which one group consists of four lines.
2. AND gate AN 1 which takes the AND of the image signals of the third and fourth lines, an inverter INI which obtains the inverted signal of the previously output line, the image signals of the first and second lines, and the inverted signal of the previously output line. It is composed of an OR gate ORI which takes the logical sum of , an AND gate AN3 which takes the logical product of this logical sum output and the logical product output of the AND gate ANI, and an OR gate OR2 which takes the logical sum of the outputs of the AND gates AN2 and AN3, OR gate OR2 produces an image signal output with a reduced number of lines. The output of OR gate OR2 is given to buffer register BU4.

With the above configuration, this logic processing circuit CLOI has four consecutive lines as one group, and each group is n (1,
2, 3, 4, ...), and the bit position in the main scanning direction is m (1, 2, 3, 'l, ...),
An, Bn, Cn and D for each line in each group in turn.
Let n be the specific bit information A m , B w ,
Cm and DW, × is logical product, 10 is logical sum, i is the inverted signal of X, and the 4 lines of A n = D n are E
When converting to one line n, E"W= (C":XD'W) X (D'+B':+
E, ”:) + (A”:XB) produces an output.

Table 1 below shows the input/output timings of the logic processing circuit CLOI shown in FIG. 3 and the input/output timings of the buffer registers BUI to BU4.

First, when the image signal of the first line has arrived, the first
The image signal of line A] is input to the BUI for one line. Assuming that one line of image signal is 2048 bits, the first
The image signals of line A1 are A) to Af, and each of the buffers BUI to BU4 only needs to have a memory capacity of 2048 bits.

When the image signal of the second line B1 has arrived, it is stored in the buffer memory BUI, and A1 is stored in the buffer memory B'U2.

When the image signal of the third line C1 has arrived, it is stored in the buffer memory BUI, B1 is stored in the buffer memory BU2, and A1 is stored in the buffer memory BU3.

When the image signal of the fourth line D1 has arrived, it is stored in the buffer memory BUI, C] is stored in the buffer memory BU2, B1 is stored in the buffer memory BU3, and the output E1 of the OR gate OR2 is stored. However, the read/write buffer memory 5 is used as an output to reduce the number of lines.
and stored in buffer memory BU4.

Similar operations are repeated thereafter.

FIG. 4 shows another configuration example CL of the logic processing circuit CLO.
O, '2 is shown. This is applied to N2. to an AND gate that ANDs the first line and the second line. Inverter INI obtains an inverted signal of the previous output (Eo).

3rd line, 4th line and inverted signal of previous output
It is composed of an AND gate ANI which takes the logical product of the two outputs, and an OR game 1 to ○R2 which takes the logical sum of the outputs of the game 1-AN1 and AN2. In this example, the logic processing circuit CLO2 is C adventureXD')XE:":ten(
Δ';xH';) is output.

FIG. 5 shows another configuration example of the logic processing circuit CLO.
3 is shown. This is an AND gate AN which takes the logical product of the third line and the fourth line, an inverter INI which obtains the inverted signal of the previous 1113 output signal, and a logical product of the first line and the second line and the inverted signal of the previous output. And gate A
N2. and OR game 1 to OR2 which take the logical sum of the outputs of AND gates ΔN1 and AN2, and in this example, the logic processing circuit CLO3 is as follows:
: Outputs XD zero).

FIG. 6 shows another configuration example CL of the logic processing circuit CLO.
Indicates O4. This is an OR gate OR5 which takes the logical sum of the first line and the second line, an OR gate ○R4 which takes the logical sum of the second line and the third line, an OR gate ○R3 which takes the logical sum of the third line and the fourth line, OR gate OR6 which takes the logical sum of the fourth line and the first line, and ant game 1 which takes the AND of the outputs of OR game 1-〇R3 to ○R6.
-A N 4, B72 (A'';
Output DW)X (D treasure + A eagle).

FIG. 7 shows yet another configuration example C of the logic processing circuit CLO.
Indicates LO5. This is an analog game that takes the AND of the first line and the second line.
It consists of an AND gate AN1 that takes the logical product of the lines, and an OR gate OR2 that takes the logical sum of the outputs of both AND gates ANI and AN2. ) is output.

The following Table 2 illustrates the outputs of each of the logic processing circuits CLOI-5.

There are 16 combinations of image signal states (1,, O) for each of the four lines A m , B yn , C% and D in Table 2.
There is a street. For comparison, Table 2 shows four lines of simple logical sums (OR). As shown in Table 2.

In simple OR, one line is black (if 1 is the black level) or white (if 1 is the white level), but in any of the logic processing circuits CL○] to 5 used in the present invention, 4 lines In response to the appropriate black and white distribution of the image signal, a one-line signal with an appropriate distribution of black and white is obtained. For this reason, the reproduced image does not become too dark, and there are no many image omissions, and an appropriate image signal can be obtained.

In addition, although the manner in which four lines of image signals are converted to one line of image signals has been explained above, by reading the output every two lines of input, two lines of image signals can be converted to one line of image signals. Similarly, by reading the output every three lines of input, three lines of image signals can be converted to one line of image signals.

,・a effect As described above, according to the present invention, four lines of image signals are converted into one
It is possible to reduce the image signal to a line image signal, and in addition, the reproduced image does not become too dark or have many image omissions, and an appropriate image signal can be obtained.

4(2) lines may be reduced to 2(1) lines, and some 5X may be implemented by reducing 3 lines to 1 line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of the configuration of a device implementing the present invention in one embodiment, FIG. 2 is a block diagram showing the configuration of the sub-scanning line density converter 4 shown in FIG. 1, FIG. , Figure 5,
FIGS. 6 and 7 are block diagrams showing examples of the structures of logic processing circuits C and LO shown in FIG. 2, respectively. Cj O, C1,,01-5: Logic processing circuit patent applicant Ricoh Co., Ltd. Procedural Amendment Yari) April 1, 1980 Commissioner of the Japan Patent Office Kazuo Wakasugi 1, Indication of Case Patent Application No. 017974, 1988 No. 2
, Title of the invention: Method for reducing the number of lines in an image signal ゛3
．． Relationship with the case of the person making the amendment Patent applicant address 1-3-6 Nakamagome, Ota-ku, Tokyo Name
(674) Ricoh Co., Ltd. Representative Hama 1
) Hiro 4, Agent 103 Phone: 03-864-60
52 Address: 2-27-6-5 Higashi Nihonbashi, Chuo-ku, Tokyo, Claims column and Detailed Description of the Invention column of the specification subject to amendment. 6. Contents of amendment (1) The entire text of the scope of claims column on pages 1 to 5 of the specification is corrected as follows. "2. Claims (1) A logically processed value such as AND or OR of the binary image signal of at least one line and the binary image signal of one line before; Binarized image signal and 3
Logical product with the binarized image signal before the line. A logical processing value such as logical sum and : is subjected to logical processing such as logical product and logical sum, and : is ≧2, and a line of binary image signal is obtained as one line of binary image signal. How to reduce the number of signal lines. (2) The method for reducing the number of lines of an image signal according to claim (1), wherein k = 4. (3) ANDing of the binarized image signal of at least one line and the binarized image signal of one line before; the binarized image signal of at least two lines before and the binarized image signal of three lines before; The image according to claim (2), wherein the logical product of How to reduce the number of signal lines. (4) OR of the binarized image signal of at least one line and the binarized image signal of one line before; the binarized image signal of at least two lines before and the binarized image signal of three lines before; The image signal according to claim (2), wherein a 4-line binarized image signal is obtained as a 1-line binarized image signal by ANDing at least two of; How to reduce the number of lines. (5) Continuous 4 lines are considered as one group, each group is n (1, 2,: 3, 4...), and the bit position in the main scanning direction is m (1, 2, 3, 4). ，・・・・
), and each line of each group is An, Bn,
Specify the specific bit information as Cn and Dn as Am, B
m, CMl, and D;, x is the logical product, 10 is the logical sum, and D is the inverted signal of (CWXDW)X (A)+B
The method for reducing the number of lines of an image signal according to claim (3), wherein (A zero x B). (6) Each group is defined as n (1, 2, 3, 4,...), with four consecutive lines as one group, and the bit position in the main scanning direction is m (1, 2, 3, '4).・・・・・・
), and each line of each group is An, Bn,
As Cn and Dn, specific bit information is A'W, B, CW, and D zero, X is logical product, ten is logical sum, Y is the inverted signal of
When converting to a line, E= (C) x D zero) X "[+ (A zero x B))
A method for reducing the number of lines of an image signal according to claim (3). (7) Four consecutive lines are considered as one group, each group is n (1, 2, 3, 4,... mountain), and the bit position in the main scanning direction is m (1, 2, 3, 4,...・・・・・・
), and each line of each group is in turn An, Bnt C
Specific bit information as n and Dn as A':, B'':
, C; and D, × is logical product, 10 is logical sum, i is the inverted signal of X, and the 4 lines of A n −D r+ are E
When converting to one line n, EW= (A':X'B':) x "huge + (c=X1.
) True) A method for reducing the number of lines of an image signal according to claim (3). (8) Each group is made up of four consecutive lines (n (1, 2, 3, 4,...), and the bit position in the main scanning direction is m (1, 2, 3,...). ４、・・・・・・
・), and each line of each loop is sequentially An, Bn,
Specific P1~ information as Cn and Dn A y ,
B m, (-m and D W, × is logical product,
When 10 is a logical sum, i is an inverted signal of W)X
(Cz+D'W) (9) Each group is made up of four consecutive lines, n (1, 2, 3, 4, ...), and the bit position in the main scanning direction is m (1, 2, 3, 4,・・・・・・
), and each line of each group is An, Bn in order.
, C'n and Dn as A'
M, B? Let lI, C, 'I'll and D be zero, × be the AND, 10 be the OR, V be the inverted signal of X,
A n = D When 4 lines of n are to be converted to 1 line of En, E'! ;= (A':XB'W)+ (CenXD';)
A method for reducing the number of lines of an image signal according to claim (3). (2) On page 11, line 2 of the specification, E zero = (C zero x D zero) X (D zero ten B zero ten EW) +
(A'XB zero), E zero = (CzXD force X (A'W+B+E'L+)
+ Correct it to (A测XB'W). (3) On page 13, line 10 of the specification, ? = (CWXDW)
:XB'W). (4) In the first line of page 14 of the specification, “E'W= (A'!;XBτ)XEzero +((,'X
, D), E enemy = (A x B enemy) X E knee + +
Correct it to (cenex Dm; ). (5) Page 14 of the specification, lines 12-13, E:= (
A=xB虞)x <B=+cen)x(Czero+Deagle)×
(D70 AI, E deflation = (A zero + B zero) x (B zero ten C eagle) x (c: +p
:) x Corrected to (D+A;). that's all

Claims (9)

[Claims] (1) A logically processed value such as AND or OR of the binary image signal of at least one line and the binary image signal of one line before; The binary image signal of at least two lines before and 3
Logical product with the binarized image signal before the line. Performs logical processing such as logical AND, logical sum, etc., and obtains a line of binary image signals as one line of binary image signals if ≧2; A method for reducing the number of lines in an image signal. (2) The method for reducing the number of lines of an image signal according to claim (1), wherein k=4. (3) ANDing of the binarized image signal of at least one line and the binarized image signal of one line before; the binarized image signal of at least two lines before and the binarized image signal of three lines before; The image according to claim (2), wherein the logical product of How to reduce the number of signal lines. (4) OR of the binarized image signal of at least one line and the binarized image signal of one line before = the binarized image signal of at least two lines before and the binarized image signal of three lines before. The image signal according to claim (2), wherein a 4-line binarized image signal is obtained as a 1-line binarized image signal by ANDing at least two of; How to reduce the number of lines. (5) Each group is made up of 4 consecutive lines, n (1, 2, 3, 4,...), and the bit position in the main scanning direction is m (1, 2, 3, 4,・・・・・・
), and each line of each group is An, Bn,
A m with specific bit information as Cn and Dn,
B yn , Cm and D; binding, × is logical product, 10 is logical sum, Y is the inverted signal of c=xD zero) x (D=+B=+pa +(
A method for reducing the number of lines of an image signal according to claim 3, wherein A=xB zero). (6) Each group is made up of 4 consecutive lines, n (1, 2, 3, 4, ...), and the bit position in the main scanning direction is m (1, 2, 3, 4,・・・・・・
・), and each line of each group is An, Bn, C in order.
Specific bit information as n and Dn? +1,
B 'n'+, Cm and 1)'! l! II, × is a logical product, + is a logical sum, T is an inverted signal of X,
When four lines of An-Dn are to be converted to one line of En, Een=(Cexpansion×Dzero)×100+(A'XB)) Claim (3) Method for reducing the number of lines of an image signal described in Section 1. (7) Each group is defined as n (1, 2, 3, 4, ...), with four consecutive lines as one group, and the bit position in the main scanning direction is m (1, 2, 3, 4,・・・・・・
), and each line of each group is An, Bn,
A 'Ill specific bit information as Cn and Dn
t' B m , C'I'l+ and D desecration, ×
is the AND, + is the OR, Y is the inverted signal of X, and A n
When four lines of −Dn are converted to one line of En, the claim No. ) The method for reducing the number of lines of an image signal described in section 2. (8) Each group is defined as n (1, 2, 3, 4, ...) with four consecutive lines as one group, and the bit position in the main scanning direction is m (1, 2, 3, 4,・・・・・・
・), and each line of each group is in turn And Bn,
Specific bit information as Cn and Dn, A yn ,
B'm, C'111 and DW, X is AND, 10 is OR, T is the inverted signal of X, A n -
When 4 lines of D n are converted to 1 line of En, E zero = (Ane×Benge)X (B';+C))X(C'
! The method for reducing the number of lines of an image signal according to claim (4), wherein: (9) Each group is made up of four consecutive lines, n (1, 2, 3, 'l', ...), and the bit position in the main scanning direction is m (1, 2, 3, 4,...
) and °, and each line of each group is An,
Let specific bit information be Bn, Cn and Dn, and let X be the logical product, +
Let E'! be the logical sum, M be the inverted signal of X, and 4 lines A n - D n be converted to 1 line En. := (A':Xl13')+ (C'!:XD
(3) The method for reducing the number of lines of an image signal according to claim (3).