JPS59141835A - Phase synchronizing circuit for burst communication - Google Patents

Abstract

PURPOSE:To suppress the frequency drift by changing the contents of storage of a memory element of a loop filter only when a burst-shaped signal is supplied. CONSTITUTION:A multiplier 1 functions as a phase difference detector which detects the phase difference between the input signal of an input terminal 300 and the output of a voltage control oscillator 2. The output of the phase difference detector is sent to an adder 33 via a coefficient device 32 as well as to the same adder 33 via a switch 34 and a perfect integrator 30. The output of the adder 33 changes the output frequency of the oscillator 2. The switch 34 is opened by the information signal which shows the end of the burst applied to an input terminal 301. Therefore the output of the integrator 30 is kept constant as long as no burst signal is supplied. Then the drift is suppressed for the output frequency of the oscillator 30.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase locked circuit for burst signals.

Conventionally, phase-locked circuits have been widely used for carrier wave regeneration in wireless communications, regardless of whether the input signal is continuous or burst-like. If the input signal is continuously input, there is no particular problem because the synchronization state once established is stably maintained. -/ On the other hand, when the input signal is in the form of a burst, the synchronization state established over a certain period of time from the beginning of a certain burst will be disturbed as soon as the burst ends. In other words, reception noise will be input to the phase locked circuit,
An equivalent noise thick θn(1) caused by this noise appears in the output of the phase difference detector. Ideally, the average value E(θn(t)) of the same chic is zero, so it is smoothed by the loop filter, and the output frequency of the voltage controlled oscillator (VCO) maintains the value at the time of synchronization. However, in reality, short-term E
(θn(1)) is not zero, and in cases where there is a DC offset in the loop filter, the loop filter
If the filter includes a perfect integrator, these DC imbalances will cause a drift in the loop filter output. This drift directly appears as an output frequency drift of the voltage controlled oscillator. Therefore, when the next burst signal is received, a large frequency difference will occur between the input signal and the voltage controlled oscillator frequency, and a long pull-in time will be required again.

An object of the present invention is to suppress the frequency drift of a voltage controlled oscillator when there is no signal between bursts.

This invention relates to a synchronization system in which the phase of a burst signal is synchronized using a second-order or higher phase synchronization circuit that includes a storage element in a loop filter. The phase synchronization for burst communication is characterized in that the voltage controlled oscillator is controlled by the fluctuating output of the phase difference detector and the fixed output of the storage element in the above-mentioned total. It is a circuit.

According to this invention, the frequency drift of the voltage controlled oscillator when there is no signal between bursts is suppressed, and when the next burst starts, only the phase difference is absorbed, so that it is possible to avoid the occurrence of a long unnecessary pull-in time. can.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a block diagram of a commonly used second-order phase-locked circuit. In the figure, 1' is a multiplier that functions as a phase difference detector, 2 is a voltage controlled oscillator, and 3 is a loop filter that includes a perfect integrator 30, and a coefficient circuit 31 that multiplies the inputs by α and -β.
, 32, together with the adder 33, the transfer function is F(s)2β
It consists of ten filters. Here, the average output frequency information of the voltage controlled oscillator is stored in this perfect integrator 30.

FIG. 2 shows the change in the contents of the perfect integrator 30, ie, the change in the output frequency of the voltage controlled oscillator, for a burst-like input. 100.101.1 in Figure (a)
02 and 103 are burst input signals.

FIG. 5B shows a change in the frequency difference Δ-f between the input signal and the output of the voltage controlled oscillator in an ideal case. In this case, as described above, the inter-burst no-signal periods 200, 201 and 20
2 also maintains the established synchronization state.

In other words, it remains at Δf-0.

On the other hand, in the actual case, due to various imperfections as described above, a frequency drift of the voltage controlled oscillator occurs in the inter-burst no-signal sections 200, 201 and 202 as shown in FIG. 3(C). Therefore, in this section, .DELTA.-( will move away from zero. Therefore, at the beginning of the burst 102, a very large .DELTA.f is generated, and a new long pull-in time is required.

FIG. 3 is a block diagram of an embodiment of the present invention. 1, 2.30, 31, 32.33 in the figures are identical to the same reference numbered elements in FIG.

Information indicating the end of the burst is input to the input terminal 301. This is, for example, the End of Message (ROM) if it is an Intelligent spade system.
Signal available. Therefore, by opening the switch 34 (9) when the same signal is input, the subsequent operation of the perfect integrator can be stopped. Since a large frequency change is not expected within a relatively short period of time between bursts, it is sufficiently applicable to water bursts as long as the synchronized state is maintained once. Although integrator 30 is at rest, its output continues to be applied to the voltage controlled oscillator input. With switch 34 open, the fuse lock loop operates as a primary system. During this operation, the phase difference can be quickly absorbed at the beginning of the next burst signal without significantly changing the frequency of the voltage controlled oscillator.

Information indicating that a new burst has been applied to the input is again applied to input terminal 301, causing switch 34 to close and continue phase-locked operation to the burst signal as a secondary fuse-locked loop. As the burst start information, for example, a start of message (SOM) signal can be used in Intelsat's spade system.

As explained above, according to the present invention, the frequency drift of the voltage controlled oscillator when there is no signal between bursts is suppressed, and the function of tracking only the phase difference as a second/lz-p during that period is suspended, and the next It is possible to construct a phase synchronization system that completes the phase pull-in at the beginning of the burst.

Although the example of the second-order fuse lock loop was explained in the embodiment shown in FIG. 3, all memory elements (integrators) other than the voltage-controlled oscillator are The same effect is expected by suspending the operation.

In addition, although we have explained only loop filters that include perfect integrators, loop filters that include leaky integrators made of ordinary CR circuits can also be used by retaining the contents of their memory elements between bursts. A similar effect can be obtained.

As something similar to the same invention, there is a gated 7-use loop that operates the phase locking system only when an input signal is present.
oop ), but this either halts all operations of Lo op when there is no input signal, or fixes the output of the phase difference detector, including the currently remaining phase difference. This is essentially different from the present invention because it attempts to keep the behavior of the voltage controlled oscillator as close to its current state as possible.

In addition, there is an attempt to shorten the pull-in time by inputting separate memory contents for each station to be received by a TDMA receiving station into a memory element prior to synchronization operation, but between each TDM burst, This differs from the present invention because the phase synchronization system does not perform any meaningful synchronization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a secondary phase-locked circuit, FIG. 2 is a diagram for explaining the operation of the phase-locked circuit with respect to burst signals, and FIG. 3 is a block diagram of an embodiment of the present invention. Figure shown. In the figure, 1 is a multiplier 2 is a voltage controlled oscillator 3 is a loop filter 30 is a perfect integrator 34 as a storage element is a switch that stops the operation of the perfect integrator.
Old Figure 1, No. 3 (2)

Claims (1)

[Claims] In a synchronization circuit that synchronizes with the phase of a burst signal using a second-order or higher phase synchronization circuit that includes a storage element in a loop filter, the storage contents of the storage element are changed only when the burst signal is applied to the input. 1. A phase synchronized circuit for burst communication, characterized in that a voltage controlled oscillator is controlled by a variable output of a phase difference detector and a fixed output of a storage element of the above-mentioned parts except for the above-mentioned time.