JPS59139078A - Ic board for active panel - Google Patents

Ic board for active panel

Info

Publication number
JPS59139078A
JPS59139078A JP58014231A JP1423183A JPS59139078A JP S59139078 A JPS59139078 A JP S59139078A JP 58014231 A JP58014231 A JP 58014231A JP 1423183 A JP1423183 A JP 1423183A JP S59139078 A JPS59139078 A JP S59139078A
Authority
JP
Japan
Prior art keywords
circuit
signal
pixel
display
panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58014231A
Other languages
Japanese (ja)
Inventor
望 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suwa Seikosha KK
Original Assignee
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suwa Seikosha KK filed Critical Suwa Seikosha KK
Priority to JP58014231A priority Critical patent/JPS59139078A/en
Publication of JPS59139078A publication Critical patent/JPS59139078A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857Static memory circuit, e.g. flip-flop

Landscapes

  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明に、画素に入力された侶号葡デコードすることに
より、画素電極に印加される信号2制御し、選択的に画
像勿構成することのできる幽累會有するアクティブマト
リックスパネルに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides an active system having an active interface that can control the signals applied to the pixel electrodes and selectively configure the image by decoding the signals input to the pixels. It concerns matrix panels.

近年\表示体への期待に大きくなって来ており特に表示
体の艮し怒しが製品全体の付加価ilN、lNボケる狭
因の一つともなって来ている。
In recent years, expectations for display materials have been increasing, and in particular, the controversy over display materials has become one of the reasons why the added value of the entire product is blurred.

脣に、表示内容の自由性、表示容量の増大に、最終製品
の性能の向上を補助する役割pケ果たし、多くの機能の
付加音可能とし、また表示品質の向上に、デザイン的に
も優れたものとなり、新しい製品を生み出す切っ掛けと
もなるものである。
In addition, it provides freedom of display contents, increases display capacity, plays a role in helping to improve the performance of the final product, enables many functions to be added, and also improves display quality and has an excellent design. It also serves as a starting point for creating new products.

これらの背景刀)ら、現在表示体の性能の向上を目指し
、多くの研究が行なわれている。
Many studies are currently being conducted with the aim of improving the performance of display devices.

表示の自由化、容量の増大に敢も適しているのは、ドン
トマトリックスパネルである。しかし、ドツトマトリッ
クスr従米のマルチプレックス駆動による表示方式によ
り実現しようとすると、その表示容量に不質的限界が存
在し、液晶の特注の改嵜、あるいは多重マトリックス方
式等が検討されているが、1だまた満足の行くものでは
ない。
Don't Matrix panels are ideally suited for liberalizing display and increasing capacity. However, if an attempt is made to realize a display system using a dot matrix r-based multiplex drive, there is an inherent limit to its display capacity, and custom-made modifications to the liquid crystal or a multiplex matrix system are being considered. 1 is still not satisfactory.

これに対し、記憶型アクティブマトリックスパネル(特
願昭57、整理& 17592に相当)は、   −上
記の不質的な限界がなく、ドツトマトリックスパネルに
に最適の方式であると言える。
On the other hand, the memory type active matrix panel (corresponding to Japanese Patent Application No. 1757/17592) does not have the above-mentioned inherent limitations and can be said to be the most suitable system for dot matrix panels.

第1図に記憶型アク゛テイブパ不ルの画素の回路の一例
?示した。1がひとつの画素であり、これは画素の表示
内容を記憶する記憶回路2とこの情報ケ用いて画素電惨
へ印加される信号七制御即する制御回wr3によって構
成されている。画素の表示内容のデータ4に、画素選択
信号5により、クロックドインバータ6.7及びインバ
ータ8によって構成されるランチ回路に書き込まれ保持
される。
Figure 1 shows an example of the pixel circuit of a memory-type active panel. Indicated. 1 is one pixel, and this is constituted by a memory circuit 2 that stores the display contents of the pixel, and a control circuit wr3 that uses this information to control a signal that is applied to the pixel current. The pixel selection signal 5 is written into the data 4 of the display content of the pixel in a launch circuit constituted by a clocked inverter 6.7 and an inverter 8, and is held there.

液晶駆動用の低周波数の信号9〔以下00MM0N信号
〕は、このラッチ回路からの信号10.11により2つ
のクロックドインバータ12.13’i開閉することに
工す制御され、画素電極14に印加される。パネルの上
ガラス上に形成され′rC透明電極には9と同し00M
M0N信号15が印加されている。ランチ回路カムらの
信号10.11によりクロックドインバータ12がON
状態で、16がOFF状態のときは、画素電極14には
00MM0N偏号が反転した14号が印力■され、液晶
には実効的に電圧がか刀・る。逆にクロックドインバー
タ13がON状態で、12がOF”F状態のときは、画
素電極14にはOOM M ON信号が印加され、液晶
にに芙効的に電圧はか刀Sらない。この2つの差音利用
し、液晶に表示tさせる。
A low frequency signal 9 (hereinafter referred to as 00MM0N signal) for driving the liquid crystal is controlled to open and close two clocked inverters 12 and 13'i by a signal 10 and 11 from this latch circuit, and is applied to the pixel electrode 14. be done. The 'rC transparent electrode formed on the top glass of the panel has the same 00M as 9.
A M0N signal 15 is applied. Clocked inverter 12 is turned on by signals 10 and 11 from the launch circuit cams.
When 16 is in the OFF state, 14 with the polarization of 00MM0N reversed is applied to the pixel electrode 14, and a voltage is effectively applied to the liquid crystal. Conversely, when the clocked inverter 13 is in the ON state and the clocked inverter 12 is in the OFF state, the OOM ON signal is applied to the pixel electrode 14, and no voltage is effectively applied to the liquid crystal. The two difference tones are used and displayed on the LCD.

不万弐μ、低電圧駆動が可能、低消費電流である、画素
密度が高く表示品質が優れている等の特徴があるが、−
万ひとつの画素に8袂とされる素子数が多く、画面全体
ではカニなりの素子数に及び歩留V)’v上げるのがむ
つかしい等の欠点がある。
However, it has features such as low voltage drive, low current consumption, high pixel density and excellent display quality.
There are a large number of elements, eight in each pixel, and there are disadvantages such as the number of elements in the entire screen being large, making it difficult to increase the yield.

実際にこの言己憶凰アクテイフ゛マトリックスパネルに
用いる場合、この画面内のある部分では数株類の画像し
か表示しないことも多い。たとえば、時計表示において
、午前・午後表示7行なう部分でばPM 、AMの2つ
の画像しか表示しない。
When actually used in this self-memory activa- tion matrix panel, only a few images of a few stocks are often displayed in a certain part of the screen. For example, in a clock display, in a portion where seven AM and PM displays are displayed, only two images, PM and AM, are displayed.

このような仕様において、画面内のすべてを第1図のよ
うな機能勿待った画素で構成するのはもつ窺いない。こ
の小数の画像しか表示しないような部分は、外s〃λら
の信号で直接制御する万が、回路が簡略化できる。本発
明に数種の%定パターンの表示のみ7行なう部分をより
簡略化された画素で置き換えることにエフ、素子数の低
減を計ることr目的とする。
With such specifications, it is impossible to construct the entire screen from pixels with no functions as shown in FIG. This portion where only a small number of images are displayed can be directly controlled by external signals such as s〃λ, and the circuit can be simplified. The purpose of the present invention is to replace the portion where only several types of percentage constant patterns are displayed with more simplified pixels, and to reduce the number of elements.

第2図に、不発明による画素の回路を示す。16にひと
つの画素であシ、これは、信号tデコードするデコード
回路1zと、このデコードされた信号Vr−より画素電
極に印加される信号上制御する制御回路18によって構
成されている。この例では2つの信号19.20(K、
j)により、4つの画面を選択する場合について掲げた
。2つの信号K 、LHデコード回路によりデコードさ
れ、この信号21 vcよジ、2つのクロックドインバ
ータ22.23を開閉することによって、画素′電極へ
印加される信号上制御する。24は液晶ケ駆動する低周
波数の駆動信号(OOMMON信号〕で、信号口の回路
と同様に制御され画素電極25に印加される。26はパ
ネルの上ガラス上に形成され′fc透明を極に印〃口さ
れるO 0MM0N倍号である。
FIG. 2 shows a pixel circuit according to the invention. There is one pixel in 16, which is composed of a decoding circuit 1z that decodes the signal t, and a control circuit 18 that controls the signal applied to the pixel electrode based on the decoded signal Vr-. In this example we have two signals 19.20(K,
j), we have listed the case where four screens are selected. Two signals K, which are decoded by the LH decoding circuit, control the signals applied to the pixel' electrodes by opening and closing two clocked inverters 22, 23. 24 is a low-frequency drive signal (OOMMON signal) for driving the liquid crystal, which is controlled in the same way as the signal port circuit and applied to the pixel electrode 25. 26 is formed on the upper glass of the panel, and 'fc' is transparent. The number to be stamped is O0MM0N.

さて、6′?第1表に示すようにに、L、2つの選択信
号により、A、B、0.Dの4つの画素が選択可能であ
る。各画素はこの4つの画面において、白又に黒の表示
ケ行なうので、これら4つの画面に対応して変化する画
素の種類は第2表に提げるP1〜P16の16通りであ
る。6“をここにおいて、2 、OH白、1rc黒を示
すものとする。
Now, 6′? As shown in Table 1, depending on L, two selection signals, A, B, 0 . Four pixels of D are selectable. Since each pixel displays either white or black on these four screens, there are 16 types of pixels P1 to P16 listed in Table 2 that change corresponding to these four screens. 6" here indicates 2, OH white, and 1rc black.

たとえば、P6で示された画素は、Aと0のときすなわ
ちKがO(’LH0,1のどちらでもよい〕のときに白
で、Kが1 (Lrl0 、1のどちらでもよい)のと
きに黒となるように、第2図のデコード回W&17が構
成される。
For example, the pixel indicated by P6 is white when A and 0, that is, when K is O (can be either 'LH0 or 1), and is white when K is 1 (can be either Lrl0 or 1). The decoding circuit W&17 in FIG. 2 is configured so that the color becomes black.

この例でげ、4つ以下の画像し刀)変化しないような部
分について適用することができる。第5図に9個の画素
によって構成される部分についての例を掲げた。4つの
画面は、[1) 、 +21 、 +3) 、 [4)
のように変化するものとし、これら’i5A、B、O,
Dとする。たとえば図(1)内の画素27ば、A、B。
In this example, it can be applied to parts that do not change (with four or fewer images). FIG. 5 shows an example of a portion composed of nine pixels. The four screens are [1), +21, +3), [4]
These 'i5A, B, O,
Let it be D. For example, pixels 27, A, and B in Figure (1).

0、Dの4つの画面で常に黒であるので第2表のPI3
に対応したデコード回路を形成し、また28で示した画
素H1A、Bで白、0.、Dで黒であるので、第2表の
P4に対応したデコード回路笛画素内に形成することで
表示2行なわせることができる。
Since it is always black on the four screens of 0 and D, PI3 in Table 2
A decoding circuit corresponding to 28 is formed, and the pixels H1A and B indicated by 28 are white, 0 . , D are black, so by forming the decoding circuit in the whistle pixel corresponding to P4 in Table 2, it is possible to display two lines.

上述のP1〜P16の各画素に、それぞれ異なった数の
半導体素子によって構成されている。たとえば、Plは
制御回路への信号?遡源に固定して行なうことができる
が、P2のと@は1個のANDゲート(またはN A 
N Dゲート)が必要となり、Pl等でrLより複雑な
回路が必要となる。
Each of the pixels P1 to P16 described above is configured with a different number of semiconductor elements. For example, is Pl a signal to the control circuit? It can be done by fixing the trace source, but P2 and @ are one AND gate (or N A
(ND gate) is required, and a more complicated circuit than rL is required for Pl etc.

したがって、画像の種類によっては、第1図の回路に比
べて大幅な素子数の低減を計ることが不可能な場合も生
ずるが、多くの場合、第1表の画面り、B、c、D2う
まく選択することにより素子数の低減を酎ることができ
る。
Therefore, depending on the type of image, it may be impossible to significantly reduce the number of elements compared to the circuit shown in Figure 1, but in many cases, the screen circuits shown in Table 1, B, c, D2 By making a good selection, the number of elements can be reduced.

以上述べたように、不発明による画素ケ、少ない変化し
〃1しない画面の部分に形成することにょシ、回路の簡
略化を行なうことができる。
As described above, the circuit can be simplified by forming the pixel according to the invention in a portion of the screen that does not change much.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、記憶型アタテイブマトリックスパネルの画素
の回路図。 第2図に、不発明による構成ヶ持つ画素の回路図。 第6図は、本発明の適用例である画面の部分葡示す囚で
ある。 以   上 第  −1Ci、、、、1 第2図 C 第3 図
FIG. 1 is a circuit diagram of a pixel in a storage type attritive matrix panel. FIG. 2 is a circuit diagram of a pixel having a configuration according to the invention. FIG. 6 shows a partial screen of an example of application of the present invention. That's all for -1Ci...1 Figure 2C Figure 3

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上に形成された半導体素子によって構成さ
れる回路によって液晶に印加される駆動信号全制瞬し、
表示させるアクティブマトリックスパネルにおいて、外
部カニらの信号すデコードするデコード回路と当該回路
刀島らのデコードされた信号により画素電極に印〃口さ
れる信号葡制御する制御回路を待つ画素葡、パネル内に
有することを特徴とするアクティブパネル用集積回路基
板。
A drive signal applied to the liquid crystal by a circuit made up of semiconductor elements formed on a silicon substrate,
In the active matrix panel to be displayed, there is a decoding circuit that decodes the signal from the external circuit, and a control circuit that controls the signal printed on the pixel electrode by the decoded signal of the circuit. An integrated circuit board for an active panel, comprising:
JP58014231A 1983-01-31 1983-01-31 Ic board for active panel Pending JPS59139078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58014231A JPS59139078A (en) 1983-01-31 1983-01-31 Ic board for active panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58014231A JPS59139078A (en) 1983-01-31 1983-01-31 Ic board for active panel

Publications (1)

Publication Number Publication Date
JPS59139078A true JPS59139078A (en) 1984-08-09

Family

ID=11855294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58014231A Pending JPS59139078A (en) 1983-01-31 1983-01-31 Ic board for active panel

Country Status (1)

Country Link
JP (1) JPS59139078A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000008626A1 (en) * 1998-08-03 2000-02-17 Seiko Epson Corporation Electrooptic device, substrate therefor, electronic device, and projection display
US7268777B2 (en) 1996-09-27 2007-09-11 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device and method of fabricating the same
US7408534B2 (en) 1998-06-17 2008-08-05 Semiconductor Energy Laboratory Co., Ltd. Reflective type semiconductor display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268777B2 (en) 1996-09-27 2007-09-11 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device and method of fabricating the same
US7489291B2 (en) 1996-09-27 2009-02-10 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device and method of fabricating the same
US7408534B2 (en) 1998-06-17 2008-08-05 Semiconductor Energy Laboratory Co., Ltd. Reflective type semiconductor display device
WO2000008626A1 (en) * 1998-08-03 2000-02-17 Seiko Epson Corporation Electrooptic device, substrate therefor, electronic device, and projection display
US6628258B1 (en) 1998-08-03 2003-09-30 Seiko Epson Corporation Electrooptic device, substrate therefor, electronic device, and projection display
KR100517398B1 (en) * 1998-08-03 2005-09-28 세이코 엡슨 가부시키가이샤 Electrooptic device, substrate therefor, electronic device, and projection display

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