JPS59138344A - Method for detecting strain of semiconductor material - Google Patents
Method for detecting strain of semiconductor materialInfo
- Publication number
- JPS59138344A JPS59138344A JP1144383A JP1144383A JPS59138344A JP S59138344 A JPS59138344 A JP S59138344A JP 1144383 A JP1144383 A JP 1144383A JP 1144383 A JP1144383 A JP 1144383A JP S59138344 A JPS59138344 A JP S59138344A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor material
- strain
- thin plate
- thickness
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Abstract
Description
【発明の詳細な説明】 [発明の技術分野] 本発明は半導体材料の結晶歪検出方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for detecting crystal strain in semiconductor materials.
[発明の技術的背景とその問題点]
一般に集積回路は半導体基板上に作られるが、この半導
体基板には、結晶構造の転位や歪がないことが必要であ
る。々′ぜならば、転位がある場合は、製造された集積
回路にリーク電流の増大、耐圧の低下等の問題が生じ、
また歪がある場合は所望の集積回路製造プロセスを施す
ことが難しくなるだめである。さらに歪は転位の原因と
なることもある。[Technical Background of the Invention and Problems thereof] Generally, integrated circuits are fabricated on a semiconductor substrate, and this semiconductor substrate must be free of dislocations and distortions in its crystal structure. Therefore, if there are dislocations, problems such as an increase in leakage current and a decrease in breakdown voltage will occur in the manufactured integrated circuit.
Further, if there is distortion, it becomes difficult to carry out the desired integrated circuit manufacturing process. Furthermore, strain can also cause dislocations.
転位や歪は生成時期によシ大きく3つに分けることがで
きる。まず1番目は半導体単結晶のインゴットを作る時
点で結晶内に生じるものである。Dislocations and strains can be roughly divided into three types depending on when they are formed. The first is what occurs within the crystal when a semiconductor single crystal ingot is made.
2番目はインゴットからウェハーを作シ出す際、すなわ
ちダイヤモンドブレードによるウエノ・−の切シ出し時
と、ラッピング時である。この時点で主に生じるのは表
面層の歪みであるためその大部分はその後エツチングを
施すことによシ除去するこきができるが、内部に生じた
歪等はそのまま残る。さらに3番目は集積回路の製造プ
ロセスにおいて生成されるものであシ、主に熱処理時の
温度の不均一によシ生成される。The second step is when a wafer is produced from an ingot, that is, when the wafer is cut out using a diamond blade, and when it is wrapped. At this point, distortions mainly occur in the surface layer, and most of them can be removed by subsequent etching, but the distortions that occur inside remain as they are. The third type is generated during the manufacturing process of integrated circuits, and is mainly generated due to non-uniform temperature during heat treatment.
このように集積回路の製造工程には半導体材料に歪や転
位が生じる工程が多いため、所望の性能を持った集積回
路を得るためには、インゴットやウェー・−の品質評価
及び集積回路製造プロセスの評価が不可欠である。転位
は歪みよシ生成されることが多いため、これらの評価は
一般に歪を検出することによシ行われる。そして歪は反
りを伴うことが多いことから、これらの評価は実際には
ウェハーの反りを検出して行われる。しかし反りが検出
できない場合でも、その半導体材料に内包されている歪
みや転位によυ製造されだ集積回路に不良が生じること
があシ、従来の方法では製品の歩留りの点で問題があっ
た。さらに最近ではウェハーの直径が大きくなるにつれ
、その厚さも厚くなる傾向がある。ウェハーが厚くなる
につn、歪は反りとして現われにくくなるため、ます捷
す歪を検出するのが難しくなってきている。In this way, the manufacturing process of integrated circuits involves many steps that cause distortion and dislocation in semiconductor materials, so in order to obtain integrated circuits with the desired performance, it is necessary to evaluate the quality of ingots and wafers and to evaluate the integrated circuit manufacturing process. evaluation is essential. Since dislocations are often generated by strain, these evaluations are generally performed by detecting strain. Since distortion is often accompanied by warpage, these evaluations are actually performed by detecting warpage of the wafer. However, even if warpage cannot be detected, the distortion and dislocations contained in the semiconductor material can cause defects in the manufactured integrated circuits, and conventional methods have had problems in terms of product yield. . Furthermore, as the diameter of the wafer increases, the thickness of the wafer also tends to increase. As wafers become thicker, distortion becomes less likely to appear as warpage, making it increasingly difficult to detect distortion during chipping.
[発明の目的] 本発明は上記の事情を鑑みてなされたもので。[Purpose of the invention] The present invention has been made in view of the above circumstances.
精度のよい半導体材料の歪検出方法を提供することを目
的とする。The purpose of this invention is to provide a highly accurate strain detection method for semiconductor materials.
[発明の概要]
半導体材料の歪を半導体材料を加工してその厚さを30
0μm以下の薄板にしだ後、この薄板試料の反りを測定
することにより検出する。試料の厚さが薄いだめ、歪等
に起因する反シが鋭く現われ、精度の高い品質管理を行
うことができる。[Summary of the invention] The strain in the semiconductor material is reduced by processing the semiconductor material to a thickness of 30%.
After cutting into a thin plate of 0 μm or less, the warpage of the thin plate sample is measured and detected. Since the thickness of the sample is thin, cracks caused by distortion etc. appear sharply, allowing highly accurate quality control.
[発明の実施例]
実施例1
大きさが100φ、厚さが525μmのPタイプ、(1
00)方位のシリコンウェハーにバイポーラICを形成
するだめの諸工程を施す。その工程の中には、温度を1
000〜1200’Cとする熱処理工程も含まれている
。そして次にウエノ・−〇反シを測定したところ、反り
の値は加μm以内であった。ところがそれらのウエノ・
−から得られる製品の歩留は低かった。反シの量と製品
の良否にははりきシした相関関係は認められずどの工程
に問題があるのかは知ることができなかった。[Embodiments of the invention] Example 1 P type, (1
00) orientation is subjected to various steps to form a bipolar IC on a silicon wafer. During the process, the temperature is
A heat treatment step at 000 to 1200'C is also included. Then, when the Ueno-〇 warpage was measured, the warpage value was within 1 μm. However, those ueno・
The yield of products obtained from - was low. There was no clear correlation between the amount of waste and the quality of the product, and it was not possible to determine which process was causing the problem.
そこで、諸工程を施したウエノ・−の裏面をラッピング
し、次にエツチングを行ってラッピングによる表面の歪
みを除去し、ウニ・・−の厚さを150μmとしだ後に
、このウエノ・−の反りを測定したところその値は50
〜150μmになっていた。はじめの加μmの反シの中
には歪によるものではなく、ウェハーを切り出す際の切
9出しむらによるものも包まれているが、この場合の反
シの値の増加分はウェハーの歪等に起因するものである
と考えられ、この増加分の大小が歪の量の大小を示して
いるとみなすことができる。この反シの値が30μm以
内となるように工程を改良したところ、製品の歩留は約
20q6向上した。Therefore, we wrapped the back side of the Ueno that had been subjected to various processes, and then etched it to remove the distortion on the surface caused by the wrapping. When measured, the value was 50
It was ~150 μm. The initial increase in the value of μm is not due to distortion, but is also caused by uneven cutting when cutting out the wafer, but the increase in the value of μm in this case is due to distortion of the wafer, etc. This is considered to be due to the amount of distortion, and the magnitude of this increase can be considered to indicate the magnitude of the amount of distortion. When the process was improved so that the value of the anti-reflection value was within 30 μm, the yield of the product was improved by about 20q6.
実施例2
大きさが125φ、厚さが625μmのPタイプ、(1
00)方位のシリコンミラーウェハーをいくつかのメー
カーよシ購入し、その反如を測定したところ、全てのメ
ーカーのウェハーの反りが10μm以内であった。Example 2 P type, (1
When silicon mirror wafers with the 00) orientation were purchased from several manufacturers and their warpage was measured, the warpage of the wafers from all manufacturers was within 10 μm.
次に各メーカーのウェハーにラッピング、エツチングを
行い、厚さを250μmKLだ後、その反りを測定した
ところ、ある−社(A社)のウェハーには80μmの反
りが現われ、他社のウェハーの反りは20μm以内であ
りん。そこでA社のウェハーにつき微細な材料評価を行
ったところ、結晶構造に微小欠陥があることが明らかと
なシ、半導体基板としでは不適当であることがわかった
。Next, wafers from each manufacturer were lapped and etched to a thickness of 250μmKL, and the warpage was measured.The wafers from a certain company (Company A) had a warpage of 80μm, and the warpage of wafers from other companies It is within 20 μm. When we conducted a detailed material evaluation of Company A's wafers, we found that there were microscopic defects in the crystal structure, and that the wafers were unsuitable for use as semiconductor substrates.
なお上記の2つの実施例においては反シを測定する際、
半導体材料の厚さをそれぞれ150,250μmに加工
したが、その厚さは歪等に起因する反りが鋭く現われ始
める厚さである300μITI以下であればよく、15
0.250μm等に限らない。In addition, in the above two examples, when measuring the resistance,
The thickness of the semiconductor material was processed to 150 and 250 μm, respectively, but it is sufficient that the thickness is 300 μITI or less, which is the thickness at which warping due to strain etc. begins to appear sharply.
It is not limited to 0.250 μm, etc.
[発明の効果]
本発明は半導体材料を厚さ300μm以下の薄板に加工
した後、その薄板の反りを測定して半導体材料の歪を検
出するものであり、インゴットやウェハーの品質評価及
び集積回路製造プロセスの評価を簡便に、かつ精度よく
行うことができる。[Effects of the Invention] The present invention detects distortion of the semiconductor material by processing the semiconductor material into a thin plate with a thickness of 300 μm or less and measuring the warpage of the thin plate, and is useful for evaluating the quality of ingots and wafers and for integrated circuits. It is possible to easily and accurately evaluate manufacturing processes.
Claims (2)
た厚さ300μm以下の薄板の反りを測定することによ
シ検出することを特徴とする半導体材料の歪検出方法。(1) A method for detecting strain in a semiconductor material, characterized in that crystal strain in an ingot is detected by measuring warpage of a thin plate cut out from the ingot and having a thickness of 300 μm or less.
を300μm以下の薄板に加工してその薄板の反シを測
定することにより検出することを特徴とする半導体材料
の歪検出方法。(2) A method for detecting strain in a semiconductor material, characterized in that crystal strain in a semiconductor wafer is detected by processing the wafer into a thin plate with a thickness of 300 μm or less and measuring the warp of the thin plate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1144383A JPS59138344A (en) | 1983-01-28 | 1983-01-28 | Method for detecting strain of semiconductor material |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1144383A JPS59138344A (en) | 1983-01-28 | 1983-01-28 | Method for detecting strain of semiconductor material |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59138344A true JPS59138344A (en) | 1984-08-08 |
Family
ID=11778234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1144383A Pending JPS59138344A (en) | 1983-01-28 | 1983-01-28 | Method for detecting strain of semiconductor material |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59138344A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020027946A (en) * | 2018-08-17 | 2020-02-20 | 楊 泰和 | Outer frame device of iron core of stationary motor having radiating wing and/or radiating hole extending outward |
-
1983
- 1983-01-28 JP JP1144383A patent/JPS59138344A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020027946A (en) * | 2018-08-17 | 2020-02-20 | 楊 泰和 | Outer frame device of iron core of stationary motor having radiating wing and/or radiating hole extending outward |
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