JPS5913748B2 - Capacitive display element drive circuit - Google Patents

Capacitive display element drive circuit

Info

Publication number
JPS5913748B2
JPS5913748B2 JP52076091A JP7609177A JPS5913748B2 JP S5913748 B2 JPS5913748 B2 JP S5913748B2 JP 52076091 A JP52076091 A JP 52076091A JP 7609177 A JP7609177 A JP 7609177A JP S5913748 B2 JPS5913748 B2 JP S5913748B2
Authority
JP
Japan
Prior art keywords
display element
capacitive display
equivalent capacitance
drive circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52076091A
Other languages
Japanese (ja)
Other versions
JPS5411643A (en
Inventor
隆彦 久樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP52076091A priority Critical patent/JPS5913748B2/en
Publication of JPS5411643A publication Critical patent/JPS5411643A/en
Publication of JPS5913748B2 publication Critical patent/JPS5913748B2/en
Expired legal-status Critical Current

Links

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  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

【発明の詳細な説明】 本発明はEL、PDP等の容量性表示素子のエレメント
に効率良く交番電圧を印加する駆動回路に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit that efficiently applies alternating voltage to elements of capacitive display elements such as EL and PDP.

EL、、PDP等の表示素子は容量性の負荷となり、ま
た印加電圧と発光輝度の関係にはあるしきい値電圧Vt
hが存在し、急峻な立上がり特性を有している。
Display elements such as EL, PDP, etc. are capacitive loads, and there is a certain threshold voltage Vt in the relationship between applied voltage and luminance.
h exists and has a steep rise characteristic.

このような容量性表示素子に効率良く交番電圧を印加す
る方法として容量性表示素子の容量成分とインダクタン
スにより共振回路を構成し、スイッチング素子を用いて
前記容量性表示素子の容量成分の電位を保持する方法が
提案されている。第1図はこの方法による従来の駆動回
路であつて、Cは容量性表示素子の等価容量、D、、D
2はダイオード、SW4、SW2はスイッチ、Eは電源
である。この回路において、まずスイッチSWIをオン
、スイッチSW2をオフにすると電源Eよりの充電電流
icが流れる。この場合インダクタンスLiと等価容量
Cによる共振周波数の51/2周期を経過した時の等価
容量Cの端子間電位は電源電圧Eよりも高い電位V1と
なりダイオードD0が逆バイアスとなりこの電圧V1に
ホールドされる。次にスイッチSWIをオフ、SW2を
オンにすると等価格量Cに充電されていた電荷が放10
電され、放電電流idが流れ、インダクタンスL2と等
価容量Cによる共振周波数の1/2周期を経過した時ダ
イオードD2は逆バイアスとなり等価容量Cはその時の
電圧V2に保持される。この等価容量Cに保持される電
圧V、、V2の値は動15作開始後しだいに大きくなる
が、等価容量C、ダイオードD、、D2、スイッチSW
I、S%等の抵抗等のためある一定の値となり定常状態
となる。この時のV4、V2の値は電源電圧Eの数倍の
値となる。しかしこの回路はスイッチSW、SW2の2
0−方しか接地できないためスイッチSWI、SW2の
制御部の構成が複雑になるほか、等価容量に流れる電流
の向きにより別のインダクタンスを用いるため、必要な
インダクタンスが2個必要であるという欠点があつた。
25本発明はこれらの欠点を除去するためになされたも
ので、回路に使用するスイッチを接地可能にするととも
に、使用するインダクタンスを1個で構成したことを特
徴とし、その目的は容量性表示素子の駆動回路の簡素化
にある。
As a method of efficiently applying an alternating voltage to such a capacitive display element, a resonant circuit is formed by the capacitive component and inductance of the capacitive display element, and a switching element is used to maintain the potential of the capacitive component of the capacitive display element. A method has been proposed. Figure 1 shows a conventional drive circuit using this method, where C is the equivalent capacitance of the capacitive display element, D, ,D
2 is a diode, SW4 and SW2 are switches, and E is a power supply. In this circuit, first, when the switch SWI is turned on and the switch SW2 is turned off, a charging current ic from the power source E flows. In this case, the potential between the terminals of the equivalent capacitor C after 51/2 periods of the resonant frequency due to the inductance Li and the equivalent capacitor C becomes a potential V1 higher than the power supply voltage E, and the diode D0 becomes reverse biased and held at this voltage V1. Ru. Next, when switch SWI is turned off and SW2 is turned on, the charge charged in equivalent quantity C is released 10
When a discharge current id flows and 1/2 period of the resonant frequency due to the inductance L2 and the equivalent capacitance C has passed, the diode D2 becomes reverse biased and the equivalent capacitance C is held at the voltage V2 at that time. The values of the voltages V, , V2 held in the equivalent capacitance C gradually increase after the start of operation.
Due to resistance such as I, S%, etc., it becomes a certain constant value and becomes a steady state. The values of V4 and V2 at this time are several times the power supply voltage E. However, this circuit has two switches SW and SW2.
Since only the 0- side can be grounded, the configuration of the control section for switches SWI and SW2 becomes complicated. In addition, different inductances are used depending on the direction of the current flowing through the equivalent capacitance, so there is a drawback that two inductances are required. Ta.
25 The present invention has been made to eliminate these drawbacks, and is characterized in that the switch used in the circuit can be grounded, and only one inductance is used, and its purpose is to The reason lies in the simplification of the drive circuit.

30第2図は本発明の実施例を示すもので、図中、Eは
直流電源、SWI、SW2は交互に開閉される2個のス
イッチ、D、、D2は前記電源に対して順方向となる向
きの2個のダイオードであり、前記スイッチSW、、S
W2の接続中点と前記ダィオー35ドD1、D2の接続
中点との間に、容量性表示素子CとインダクタンスLと
の直列回路が接続されている。
30 Figure 2 shows an embodiment of the present invention. In the figure, E is a DC power supply, SWI and SW2 are two switches that are opened and closed alternately, and D, D2 are switches in the forward direction with respect to the power supply. The switches SW, , S
A series circuit of a capacitive display element C and an inductance L is connected between the connection midpoint of W2 and the connection midpoint of the diodes D1 and D2.

而して、この回路において、まずスイッチSWlをオン
、スイツチSW2をオフにすると、電源Eよりの充電電
流1cが流れる。
In this circuit, when the switch SWl is first turned on and the switch SW2 is turned off, a charging current 1c from the power source E flows.

この場合、インダクタンスLと容量性表示素子の等価容
量Cによる共振周波数の1/2周期を経過すると等価容
量Cの充電電荷量は最大となり、端子間電圧は最高値V
1となる。その後等価容量Cは放電の過程に入るが、こ
の電流の向きはIcと逆方向となるためダイオードD1
で阻止される。このためインダクタンスLに誘起されて
いた電圧はOとなり、等価容量Cの端子間電圧はV1に
保持される。次にスイツチSWlをオフ、スイツチSW
2をオンにすると等価容量Cに充電されていた電荷はL
Cの共振周波数の最初の1/4周期の間放電され、引き
継き次の1/4周期の間、放電と同じ方向の電流が流れ
る(第2図にIdで示す。)。したがつて等価容量Cの
端子間電位はLCの共振周波の1/2周期後に最高値V
2となる。その後等価容量Cは放電の過程に入るが、こ
この電流の向きはIdと逆方向となるためダイオードD
,により阻止され等価容量Cの端子間電位は2に保持さ
れる。次にスィツチSWlをオン、スィツチSW2をオ
フにするとLCの共振周波数の1/2周期の間第2図1
cで示す方向の電流が流れ、1/2周期経過後等価容量
Cの端子間電位は最高電位V3に保持される。この過程
では最初に等価容量Cの放電の過程があることが動作開
始時点の過程と異なる。以下同様にスイツチSWl,S
W2を交互にオン、オフさせると、同様の動作をくり返
し、等価容量Cの端子間電圧はVl,2,3,4,5,
V6・・・・・・の値に保持されていく。この時V1〈
V3くV5・・・・・・,V2〈V4〈V6・・・・・
・となるが、回路の抵抗等によりそれぞれ一定の値Vc
,Vdとなり定常状態となる。以上の説明から明らかな
ようにVc,dは逆方向の電位であり、等価容量Cの端
子間にはVC+Vdの電位差の交番電圧を印加すること
ができる。このC,dの値を正確に求めることは困難で
あるが、実験によればc+3E1d+1.5E程度が得
られ等価容量Cの端子間には電源電圧の約5倍程度の電
圧を印加することができた。第3図は本発明の他の実施
例を示す図である。
In this case, after 1/2 period of the resonant frequency due to the inductance L and the equivalent capacitance C of the capacitive display element has elapsed, the amount of charge in the equivalent capacitance C reaches its maximum, and the voltage between the terminals reaches its maximum value V
It becomes 1. After that, the equivalent capacitance C enters the process of discharging, but since the direction of this current is opposite to Ic, the diode D1
will be blocked. Therefore, the voltage induced in the inductance L becomes O, and the voltage between the terminals of the equivalent capacitance C is maintained at V1. Next, turn off switch SWl, switch SW
When 2 is turned on, the charge stored in the equivalent capacitance C becomes L.
It is discharged during the first 1/4 period of the resonant frequency of C, and a current flows in the same direction as the discharge during the next 1/4 period (indicated by Id in FIG. 2). Therefore, the potential between the terminals of the equivalent capacitance C reaches its maximum value V after 1/2 period of the resonant frequency of LC.
It becomes 2. After that, the equivalent capacitance C enters the process of discharging, but the direction of the current here is opposite to Id, so the diode D
, and the potential between the terminals of the equivalent capacitance C is held at 2. Next, when switch SWl is turned on and switch SW2 is turned off, the period shown in Fig. 2
A current flows in the direction shown by c, and after 1/2 period has elapsed, the potential between the terminals of the equivalent capacitance C is held at the highest potential V3. This process differs from the process at the start of operation in that there is first a process of discharging the equivalent capacitance C. Similarly, switches SWl, S
When W2 is turned on and off alternately, the same operation is repeated, and the voltage between the terminals of the equivalent capacitance C becomes Vl, 2, 3, 4, 5,
It is maintained at the value of V6... At this time V1
V3, V5..., V2〈V4〈V6...
・However, each has a certain value Vc depending on the resistance of the circuit etc.
, Vd, resulting in a steady state. As is clear from the above description, Vc and d are potentials in opposite directions, and an alternating voltage with a potential difference of VC+Vd can be applied between the terminals of the equivalent capacitance C. Although it is difficult to accurately determine the values of C and d, experiments have shown that approximately c+3E1d+1.5E can be obtained, and it is possible to apply a voltage approximately five times the power supply voltage between the terminals of the equivalent capacitance C. did it. FIG. 3 is a diagram showing another embodiment of the present invention.

すなわちトランジスタTrl,Tr2でスイツチSWl
,SW2を構成し、トランジスタTr4,Tr3で端子
2から入力された制御パルス1を+Vから−Vの間で変
化するパルスに変換するパルス変換回路を構成し、この
回路の出力でトランジスタTr,,Tr2を交互にオン
状態に制御するものである。他の動作は前記実施例と同
様である。このように、スイツチSWl,SW2の一方
を接地できるため、それぞれのスイツチをNPN,PN
Pのトランジスタで構成することによつて容量性表示素
子の駆動回路を容易に実現することができる。以上説明
したように本発明によれば、容量性表示素子とインダク
タンスの直列共振回路に流れる電流の方向を制御するス
イツチの一方の端子を接地することができるため、非常
に簡単な構成の容量性表示素子の駆動回路を実現するこ
とができる。また容量性表示素子と直列共振回路を構成
するために用いるインダクタンスを流れる電流のいかん
にかかわらず共用するため、使用するインダクタンスは
1個になるという利点がある。
In other words, the switch SWl is activated by the transistors Trl and Tr2.
, SW2, and the transistors Tr4 and Tr3 constitute a pulse conversion circuit that converts the control pulse 1 input from the terminal 2 into a pulse varying between +V and -V, and the output of this circuit is used to convert the control pulse 1 into a pulse that changes between +V and -V. Tr2 is controlled to be turned on alternately. Other operations are similar to those in the previous embodiment. In this way, one of the switches SWl and SW2 can be grounded, so the respective switches can be connected to NPN and PN.
By using P transistors, a drive circuit for a capacitive display element can be easily realized. As explained above, according to the present invention, one terminal of the switch that controls the direction of the current flowing in the series resonant circuit of the capacitive display element and the inductance can be grounded. A driving circuit for a display element can be realized. Further, since the inductance used to form the series resonant circuit with the capacitive display element is shared regardless of the current flowing, there is an advantage that only one inductance is used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従米の駆動回路の結線図、第2図は本発明の実
施例を示す回路図、第3図は本発明の他の実施例を示す
回路図である。 C:容量性表示素子の等価容量、Dl,D2:ダイオー
ド、Ll,L2,L:インダクタンス、SWl,SW2
:スイツチ、E:直流電源、Trl〜Tr4:トランジ
スタ、1:制御パルス。
FIG. 1 is a wiring diagram of a conventional drive circuit, FIG. 2 is a circuit diagram showing an embodiment of the invention, and FIG. 3 is a circuit diagram showing another embodiment of the invention. C: equivalent capacitance of capacitive display element, Dl, D2: diode, Ll, L2, L: inductance, SWl, SW2
: switch, E: DC power supply, Trl to Tr4: transistor, 1: control pulse.

Claims (1)

【特許請求の範囲】[Claims] 1 直流電源と2個のスイッチング素子と前記電源に対
して順方向となる向きの2個のダイオードとを前記の順
にサークル状に接続し、前記のスイッチング素子の中間
と前記2個のダイオードの中間との間に、容量性表示素
子とインダクタンスの直列回路を接続し、前記2個のス
イッチング素子を交互に開閉するようにしてなる容量性
表示素子の駆動回路。
1 A DC power source, two switching elements, and two diodes oriented in the forward direction with respect to the power source are connected in a circle in the above order, and the middle of the switching element and the middle of the two diodes are connected in the above order. A drive circuit for a capacitive display element, wherein a series circuit of a capacitive display element and an inductance is connected between the two switching elements, and the two switching elements are alternately opened and closed.
JP52076091A 1977-06-28 1977-06-28 Capacitive display element drive circuit Expired JPS5913748B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52076091A JPS5913748B2 (en) 1977-06-28 1977-06-28 Capacitive display element drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52076091A JPS5913748B2 (en) 1977-06-28 1977-06-28 Capacitive display element drive circuit

Publications (2)

Publication Number Publication Date
JPS5411643A JPS5411643A (en) 1979-01-27
JPS5913748B2 true JPS5913748B2 (en) 1984-03-31

Family

ID=13595160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52076091A Expired JPS5913748B2 (en) 1977-06-28 1977-06-28 Capacitive display element drive circuit

Country Status (1)

Country Link
JP (1) JPS5913748B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323305A (en) * 1990-02-07 1994-06-21 Daichi Co., Ltd. Light emitting power supply circuit

Also Published As

Publication number Publication date
JPS5411643A (en) 1979-01-27

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