JPH01321723A - Fet series circuit - Google Patents
Fet series circuitInfo
- Publication number
- JPH01321723A JPH01321723A JP15353488A JP15353488A JPH01321723A JP H01321723 A JPH01321723 A JP H01321723A JP 15353488 A JP15353488 A JP 15353488A JP 15353488 A JP15353488 A JP 15353488A JP H01321723 A JPH01321723 A JP H01321723A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- fet
- voltage
- capacitance
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 14
- 230000007423 decrease Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、高電圧回路のスイッチング素子として用い
られるFETを複数個直列接続したFET直列回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FET series circuit in which a plurality of FETs used as switching elements in a high voltage circuit are connected in series.
第5図は例えば「電子技術J(1987年11月号)の
第44ページに掲載された従来のFET直列回路を示す
回路図であり、図において、(1a)〜(1d)は複数
個例えば4個直列接続されたFET、(2a)〜(2d
)は各FET(1a)〜(ld)のドレイン(DJと接
続され、そのドレイン(D)、ソース(S)間印加電圧
を各FET(la)〜(1d)の耐圧以下にクランプす
る通電圧クランプ用ツェナーダイオード。FIG. 5 is a circuit diagram showing a conventional FET series circuit published, for example, on page 44 of "Electronic Technology J (November 1987 issue). In the figure, (1a) to (1d) indicate a plurality of Four FETs connected in series, (2a) to (2d
) is connected to the drain (DJ) of each FET (1a) to (ld), and is a conducting voltage that clamps the voltage applied between the drain (D) and source (S) below the withstand voltage of each FET (la) to (1d). Zener diode for clamp.
(3a)〜(3d)は各FET(la)〜(1d)のド
レイン(I))とゲート(Qの間で各ツェナーダイオー
ド(2a)〜(2d)と直列に接続され、各FET (
1a )〜(ld)のオン時にゲート(G)からドレイ
ン(D)に流れる電流を防止する逆流防止用ダイオード
、(4a)〜(4C)は各FET (1b )〜(1d
)のゲート(G)とソース(S)の間に接続され、各F
ET (1b )〜(ld)のオフ時にゲート(G)と
ソース(S)の間に充電されている電荷を放出する放′
α抵抗、(5a)〜(5C)はFET (1a )と(
1b)、(1b)と(1c)、(IC)と(1d)のゲ
−ト(G)間に接続され、各FET (1b )〜(1
d)の電圧を固定する電位固定用ダイオード、(6)は
上述したFET (1a )のゲート(G)並びにダイ
オード(3a)および(5a)に接続されたゲート駆動
回路、(7) i’!このゲート駆動回路(6)の電源
、(8)はFET(la)〜(ld’lと直列に接続さ
れた負荷、(9)はFET (1a )〜(1d)を介
して負荷(8)に電力を供給する主電源である。(3a) to (3d) are connected in series with each Zener diode (2a) to (2d) between the drain (I)) and gate (Q) of each FET (la) to (1d), and each FET (
1a ) to (ld) are reverse current prevention diodes that prevent current flowing from the gate (G) to the drain (D) when turned on, (4a) to (4C) are the respective FETs (1b) to (1d).
) is connected between the gate (G) and source (S) of each F
When ET (1b) to (ld) are turned off, the charge that is stored between the gate (G) and the source (S) is released.
α resistance, (5a) to (5C) are FET (1a) and (
1b), (1b) and (1c), and (IC) and (1d), each FET (1b) to (1
d) a potential fixing diode for fixing the voltage; (6) a gate drive circuit connected to the gate (G) of the above-mentioned FET (1a) and diodes (3a) and (5a); (7) i'! The power supply for this gate drive circuit (6), (8) is a load connected in series with FETs (la) to (ld'l), and (9) is a load (8) connected through FETs (1a) to (1d). This is the main power supply that supplies power to the
第6図は第5図のFET(1a)〜(1d)を等制約に
スイッチとコンデンサで竹き換えた等価回路図であり、
(10a)〜(10d)は各FET (1a )〜(l
d)のドレイン(D)とソース(S)の間の等価スイッ
チ、(11a)〜(11b)は各FET(1a)〜(l
cl)のゲート(G)−ソース(S1間キャパシタンス
、(12a)〜(12d)は各FET(la)〜(ld
)のゲート(G)−ドレイン(D)間キャパシタンスで
ある。Figure 6 is an equivalent circuit diagram in which the FETs (1a) to (1d) in Figure 5 are replaced with switches and capacitors with equal constraints.
(10a) to (10d) are each FET (1a) to (l
Equivalent switches between the drain (D) and source (S) of d), (11a) to (11b) are each FET (1a) to (l
cl) gate (G)-source (S1 capacitance, (12a) to (12d) are each FET (la) to (ld
) is the gate (G)-drain (D) capacitance.
従来のFET直列回路は上述したように構成されており
、その動作をまず第5図について説明する。第5図のF
ET直列回路において、ゲート駆動回路(6)からゲー
ト電圧VOがFET (1a )のゲート(G)とソー
ス(S)の間に印加されると、FET (1a )1!
オンすなわちドレイン(Dlとソース(S)間がショー
トする。このことにより、続いてFET(1b)のグー
ト(G)とソース(S)間にはダイオード(5a)を
介してゲート電圧vOが印加され、FET (1b )
はオンする。同様にして、残りのFET(lc)、(1
d)も順次オンする。この時負荷(8)には主電源(9
)の電圧が印加される。ツェナーダイオード(2a)〜
(2d)は、ツェナー電圧を各FET(la)〜(1d
)の耐電以下に選ぶことにより、各FET(la)〜(
1d)がターンオンする前にドレイン(Dlとソース(
S1間に印加される電圧なツェナー電圧以下に抑え、各
FET(1a)〜(1d)の耐圧劣化を防止することが
できる。The conventional FET series circuit is constructed as described above, and its operation will first be explained with reference to FIG. F in Figure 5
In the ET series circuit, when the gate voltage VO is applied from the gate drive circuit (6) between the gate (G) and source (S) of FET (1a), FET (1a)1!
In other words, the drain (Dl) and the source (S) are shorted.As a result, the gate voltage vO is subsequently applied between the gate (G) and the source (S) of the FET (1b) via the diode (5a). applied, FET (1b)
turns on. Similarly, the remaining FETs (lc), (1
d) is also turned on sequentially. At this time, the load (8) is connected to the main power supply (9
) voltage is applied. Zener diode (2a) ~
(2d) is the Zener voltage of each FET (la) to (1d
), each FET (la) to (
1d) before turning on, the drain (Dl) and source (
The voltage applied between S1 can be suppressed to a Zener voltage or less, and deterioration of the withstand voltage of each FET (1a) to (1d) can be prevented.
次にこの動作の詳細を第6図の等価回路図および第7図
の波形図について説明する。第7図(a) K示すゲー
ト電圧VC)がFET(la’)のゲート(G)とソー
ス(S)の間に印加されると、第7図(b)に示すゲー
トへゲート電流i0が流れ、ゲート(G)・ソース(S
)間キャパシタンス(lla)に充電fiii1が流ね
る。この期間は第6図のTlで表わされる。次にゲート
電圧V□がゲートしきい値電圧vc’rをこえた時点で
、等価スイッチ(10a’)が閉じる。この過程で第7
図(c)に示すドレーン電圧’Vlが減少していき、こ
のVlがグー)を圧VOより小さくなったとき、ゲート
(G)・ソース(S)間キャパシタンス(lla)に流
れていた充t!ff1itはゲート(G)・ドレイン(
D)間キャパシタンス(12a)の方へ流れを変える。Next, details of this operation will be explained with reference to the equivalent circuit diagram of FIG. 6 and the waveform diagram of FIG. 7. When a gate voltage VC) shown in Fig. 7(a) is applied between the gate (G) and source (S) of the FET (la'), a gate current i0 flows to the gate shown in Fig. 7(b). Flow, gate (G), source (S
) A charge fiii1 flows through the capacitance (lla) between. This period is represented by Tl in FIG. Next, when the gate voltage V□ exceeds the gate threshold voltage vc'r, the equivalent switch (10a') closes. In this process, the seventh
When the drain voltage 'Vl shown in figure (c) decreases and this Vl becomes smaller than the voltage VO, the charge flowing in the capacitance (lla) between the gate (G) and the source (S) decreases. ! ff1it is the gate (G)/drain (
D) diverts the flow towards the capacitance (12a).
同時にFET (1b )のゲート(G)−ソース(8
1間キャパシタンス(1lb)にも充電電流12が流れ
る。このことによりグー) (G)・ソース(S)間キ
ャパシタンス(11b)の両端電圧が上昇し、この電圧
がゲートしきい値電圧vc’rを超えた時点、つまりド
レイン電圧Vl<VGVC)Tどなった時点で等価スイ
ッチ(10b)が閉じ、ドレイン直圧v2が減少し始め
る。以後上述したのと同様にして、グー) (G)・ド
レイン(D)間キャパシタンス(12b)に充電′電流
12が転流する。次いでゲート(G)・ソースC31間
キャパシタンス(11C)とゲート(G)eドレイン(
D1間キャパシタンス(12C’)に充電電流i3が流
れ、次いでグー ) (G)・ソース(S)間キャパシ
タンス(lld)トケート(G)11ドレイン(D)間
キャパシタンス(12d)に充1!電流i4が流れる。At the same time, the gate (G)-source (8) of FET (1b)
The charging current 12 also flows through the 1 lb capacitance (1 lb). As a result, the voltage across the capacitance (11b) between (G) and source (S) increases, and at the point when this voltage exceeds the gate threshold voltage vc'r, that is, the drain voltage Vl<VGVC)T At the point in time, the equivalent switch (10b) closes and the drain direct pressure v2 begins to decrease. Thereafter, in the same manner as described above, the charging current 12 is commutated to the capacitance (12b) between the drain (G) and the drain (D). Next, the capacitance (11C) between the gate (G) and the source C31 and the gate (G) e drain (
A charging current i3 flows through the capacitance (12C') between D1, and then charges the capacitance (12d) between the drain (D) and the drain (G)11! Current i4 flows.
以上、充電電流i1がゲート(G)・ソース(S1間キ
ャパシタンス(12a)に転流し始めてから充電電流r
4が流れ終るまでは第7図の期間T2で表わされる。As described above, after the charging current i1 starts commutating to the gate (G) and source (S1 capacitance (12a)), the charging current r
The period until the end of the flow of 4 is represented by a period T2 in FIG.
上述したような従来のFET直列回路では、ゲート駆動
回路が直列接続された全てのFETのゲートキャパシタ
ンスへ充電電流を供給しなければならず、ゲート駆動回
路の損失が大きくなる。すなわち、その損失はFETの
直列接続数が多い程、またスイッチング周波数が高い程
増大するという問題点があった。In the conventional FET series circuit as described above, the gate drive circuit must supply charging current to the gate capacitances of all the FETs connected in series, resulting in large losses in the gate drive circuit. That is, there is a problem in that the loss increases as the number of FETs connected in series increases and as the switching frequency increases.
この発明は、上述したような問題点を解決するためにな
されたもので、FETの直列接続数が多くなり、またス
イッチング周波数が高くなっても、ゲート駆動回路によ
る損失を少なくするFET直列回路を得ることを目的と
する。This invention was made to solve the above-mentioned problems, and it provides a FET series circuit that reduces loss caused by the gate drive circuit even when the number of series-connected FETs increases and the switching frequency increases. The purpose is to obtain.
この発明に係るFET直列回路は、最下段のFETだけ
にゲート電流を供給するゲート駆動回路と、このゲート
駆動回路の入力側に在って最下段以外のFETKゲート
電流を供給する手段とを設けたものである。The FET series circuit according to the present invention includes a gate drive circuit that supplies gate current only to the lowest stage FET, and means that is located on the input side of this gate drive circuit and supplies gate current to the FETs other than the lowest stage. It is something that
この発明においては、ゲート駆動回路は最下段のFET
のみにゲート電流を供給し、従ってゲートキャパシタン
スへ素子分の充電へゲート電流だけを流し、他のFET
には電源からゲート電流を供給する。In this invention, the gate drive circuit is the lowest stage FET.
Therefore, only the gate current flows to charge the element to the gate capacitance, and the other FETs
A gate current is supplied from the power supply.
第1図は、この発明によるFET直列回路の一実施例の
回路図である。(la)〜(ld)、(2a)〜(2d
)、(3a)〜(3d)、(4a)〜(4c)l(5b
)(5c)、(7)〜(9)は従来装置におけるのと全
く同一のものである。(13)は第5図に示したように
ゲート駆動回路(6)の出力側に接続されるのではなく
、後述するゲート駆動回路の入力側にある電源(71に
接続され、この電源(7)からFET (1b )〜(
1d)のゲート(G)へゲート電流を流出させるゲート
用ダイオード、(14)は最下段FET(la)のゲ−
) (G)とソース(Slの間にのみゲート電圧VOを
供 −給する最下段用ゲート駆動回路である。第2図は
第1図のFET (1a)〜(1d)を等測的にスイッ
チとコンデンサで置き換えた等価回路図である。FIG. 1 is a circuit diagram of an embodiment of a FET series circuit according to the present invention. (la) ~ (ld), (2a) ~ (2d
), (3a) to (3d), (4a) to (4c)l (5b
) (5c) and (7) to (9) are exactly the same as in the conventional device. (13) is not connected to the output side of the gate drive circuit (6) as shown in FIG. ) to FET (1b)~(
1d) is a gate diode that drains the gate current to the gate (G), and (14) is the gate diode of the bottom stage FET (la).
) This is a gate drive circuit for the lowest stage that supplies gate voltage VO only between the source (G) and the source (Sl). It is an equivalent circuit diagram replaced with a switch and a capacitor.
次に上記実施例の動作を第3図の波形図も参照しながら
説明する。第3図(a)のゲート電圧weがFET (
1a )のゲート((2)に与えられると、ゲート(G
)・ソース(S)間キャパシタンス(lla)に第3図
(b)のゲート電流すなわち充電電流11が流れ込み、
ゲート電圧vGは上昇し始める。このゲート電圧VGが
ゲートしきい値電圧vo’rを超えると等価スイッチ(
10a)が閉じ、ドレイン電圧Mlが下降する。Next, the operation of the above embodiment will be explained with reference to the waveform diagram in FIG. The gate voltage we in FIG. 3(a) is FET (
1a) is given to the gate ((2)), the gate (G
) and the source (S) capacitance (lla), the gate current shown in FIG. 3(b), that is, the charging current 11 flows,
Gate voltage vG begins to rise. When this gate voltage VG exceeds the gate threshold voltage vo'r, the equivalent switch (
10a) is closed, and the drain voltage M1 decreases.
このドレイン電圧v1がゲート電圧VQ以下になると、
ゲート(G)・ソース(S)間キャパシタンス(lla
)K流れていた充電電流ilはグー) (G)−ドレイ
ン(D) 間キャパシタンス(12a)へ転流する。こ
コマでの状態が第3図6c’rtで表わされる。さらに
FET(la)のドレイン電圧vlが電源(7)の出力
電圧E以下になると、F’ET (1b )のゲート(
G)・ソース(4)間キャパシタンス(11b)に充電
電流i2が電源(7)よりダイオード(13)を通して
供給され・ゲート(G)・ソース(S)間キャパシタン
ス(llb)の両端電圧は上昇し始め、この値が、ゲー
トしきい値電圧YGTを超えたとき、すなわち、 Ml
<E −VGTとなったとき、等価スイッチ(10b
)は閉じ、ドレイン電圧v2は下降し始める。vl +
V2 < Eになったとき充電電流12はゲート(G
)・ドレイン(D)間キャパシタンス(12b)へ転流
する。同時K FET(1c)のグー) (G)・ソー
ス(S)間キャパシタンス(llc)への充電電流i3
が電源(7)からダイオード(13)および(5b)を
通して供給され、その゛グー ) (G)・ソース(S
)間キャパシタンス(11c)の両端の電圧は上昇し始
める。等価スイッチ(10b”1のときと同様にして、
等価スイッチ(10c)および(10d)は閉じ、これ
で等価スイッチが全部閉じたことになり、FET直列回
路はターンオン終了となる。When this drain voltage v1 becomes less than the gate voltage VQ,
Gate (G)-source (S) capacitance (lla
) The charging current il flowing through K is commutated to the capacitance (12a) between (G) and drain (D). The state at this frame is represented by 6c'rt in FIG. Furthermore, when the drain voltage vl of FET (la) becomes lower than the output voltage E of power supply (7), the gate (
A charging current i2 is supplied from the power supply (7) to the capacitance (11b) between the gate (G) and the source (4) through the diode (13), and the voltage across the capacitance (llb) between the gate (G) and the source (S) increases. Initially, when this value exceeds the gate threshold voltage YGT, that is, Ml
<E - VGT, the equivalent switch (10b
) closes and the drain voltage v2 begins to fall. vl +
When V2 < E, the charging current 12 becomes the gate (G
) and the drain (D) capacitance (12b). Charging current i3 to capacitance (llc) between (G) and source (S) of simultaneous K FET (1c)
is supplied from the power supply (7) through the diodes (13) and (5b), and its
) the voltage across the capacitance (11c) begins to rise. Equivalent switch (10b” in the same way as 1,
The equivalent switches (10c) and (10d) are closed, which means that all the equivalent switches are closed, and the FET series circuit is turned on.
なお、上記実施例では、最下段以外のFETのゲート電
流をゲート駆動回路(14)の電源(7)の代りに、主
電源(9)の出力電圧を分圧した電圧を用いてもよい。In the above embodiment, instead of the power source (7) of the gate drive circuit (14), a voltage obtained by dividing the output voltage of the main power source (9) may be used for the gate current of the FETs other than the lowest stage.
この場合の実施例を第4図に示す。図において、(15
)は分圧器である。An example in this case is shown in FIG. In the figure, (15
) is a voltage divider.
以上、詳述したように、この発明は、最下段のFETの
ゲートにのみゲート電流を供給するゲート駆動回路、お
よびこのゲート駆動回路の入力側に在って上記最下段の
PET以外のFETのゲートヘゲ−)へゲート電流を供
給する手段を備えているので、ゲート駆動回路から流出
されるゲート電流が1個のFETのゲートキャパシタン
スを充電する電流分だけですみ、FETの直列数の増大
や高周波化に対してゲート駆動回路の損失を極端に低減
することができるという効果を奏する。As described in detail above, the present invention provides a gate drive circuit that supplies gate current only to the gate of the bottom-stage FET, and a gate drive circuit that supplies gate current only to the gate of the bottom-stage FET, and a gate drive circuit that supplies gate current to only the gate of the bottom-stage FET, and Since the gate drive circuit is equipped with a means for supplying gate current to the gate drive circuit, the gate current flowing out from the gate drive circuit is only enough to charge the gate capacitance of one FET. This has the effect that the loss of the gate drive circuit can be extremely reduced compared to the above.
第1図はこの発明の一実施例の回路図、第2図は第1図
の実施例の等価回路図、第3図は8g2図の回路の動作
説明用波形図、第4図は第5図は従来のFET直列回路
の回路図、第6図は第5図のFET直列回路の等価回路
図、第7図は第6図のFET直列回路の動作説明用波形
図である。
図において、(la)〜(ld)はFET、(2a)〜
(2d)はツェナーダイオード、(3a)〜(3d)は
ダイオード、C4a”)〜(4c)は抵抗、(13)。
(5b)、(5c)はダイオード、(7)はゲート駆動
回路用電源、(9)は主電源、(14)は最下段用ゲー
ト駆動回路、(15)は分圧器である。
なお、図中、同一符号は同一または相当部分を示す。
扇7図
9 主を源
15、分FL券
W)6図Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the embodiment of Fig. 1, Fig. 3 is a waveform diagram for explaining the operation of the circuit of Fig. 6 is a circuit diagram of a conventional FET series circuit, FIG. 6 is an equivalent circuit diagram of the FET series circuit of FIG. 5, and FIG. 7 is a waveform diagram for explaining the operation of the FET series circuit of FIG. 6. In the figure, (la) to (ld) are FETs, (2a) to
(2d) is a Zener diode, (3a) to (3d) are diodes, C4a'') to (4c) are resistors, (13). (5b) and (5c) are diodes, (7) is a power supply for the gate drive circuit. , (9) is the main power supply, (14) is the gate drive circuit for the lowest stage, and (15) is the voltage divider. In the figure, the same reference numerals indicate the same or equivalent parts. 15, minute FL ticket W) 6 diagram
Claims (1)
ジスタ)と、各FETのドレインとゲートの間に接続さ
れた過電圧クランプ回路と、最下段のFET以外の各F
ETのゲートとソースの間に接続された抵抗と、上記最
下段のFETから上段のFETへ各FETを順次オンさ
せるためのゲート回路手段とを備えたFET直列回路に
おいて、上記ゲート回路手段は、上記最下段のFETの
ゲートにのみゲート電流を供給するゲート駆動回路、お
よびこのゲート駆動回路の入力側に在つて上記最下段の
FET以外のFETのゲートへゲート電流を供給する手
段を含むことを特徴とするFET直列回路。(1) Multiple FETs (field effect transistors) connected in series, an overvoltage clamp circuit connected between the drain and gate of each FET, and each FET other than the bottom FET.
In the FET series circuit comprising a resistor connected between the gate and source of the ET, and gate circuit means for sequentially turning on each FET from the lowest stage FET to the upper stage FET, the gate circuit means comprises: A gate drive circuit that supplies gate current only to the gate of the FET at the lowest stage, and a means for supplying gate current to the gates of FETs other than the FET at the lowest stage, which is located on the input side of the gate drive circuit. Characteristic FET series circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15353488A JPH01321723A (en) | 1988-06-23 | 1988-06-23 | Fet series circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15353488A JPH01321723A (en) | 1988-06-23 | 1988-06-23 | Fet series circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01321723A true JPH01321723A (en) | 1989-12-27 |
Family
ID=15564621
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15353488A Pending JPH01321723A (en) | 1988-06-23 | 1988-06-23 | Fet series circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01321723A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008034688A1 (en) * | 2008-07-25 | 2010-01-28 | Siemens Aktiengesellschaft | Switching device for switching during high operating voltage, has controlled switching element with control port and two main connections for forming switching line |
JP2012039866A (en) * | 2011-11-04 | 2012-02-23 | Mitsubishi Electric Corp | Power semiconductor module, power conversion device, and rolling stock |
US8791662B2 (en) | 2010-07-01 | 2014-07-29 | Mitsubishi Electric Corporation | Power semiconductor module, electric-power conversion apparatus, and railway vehicle |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6093820A (en) * | 1983-10-28 | 1985-05-25 | Hitachi Ltd | Switch circuit |
-
1988
- 1988-06-23 JP JP15353488A patent/JPH01321723A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6093820A (en) * | 1983-10-28 | 1985-05-25 | Hitachi Ltd | Switch circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008034688A1 (en) * | 2008-07-25 | 2010-01-28 | Siemens Aktiengesellschaft | Switching device for switching during high operating voltage, has controlled switching element with control port and two main connections for forming switching line |
DE102008034688B4 (en) * | 2008-07-25 | 2010-08-12 | Siemens Aktiengesellschaft | Switching device for switching at a high operating voltage |
US8791662B2 (en) | 2010-07-01 | 2014-07-29 | Mitsubishi Electric Corporation | Power semiconductor module, electric-power conversion apparatus, and railway vehicle |
JP2012039866A (en) * | 2011-11-04 | 2012-02-23 | Mitsubishi Electric Corp | Power semiconductor module, power conversion device, and rolling stock |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8274450B2 (en) | Current sensing bi-directional switch and plasma display driver circuit | |
US5111375A (en) | Charge pump | |
US5559463A (en) | Low power clock circuit | |
WO2008069129A1 (en) | Drive circuit and semiconductor device using the same | |
CA2171765A1 (en) | Driver circuit for bridge circuit employing a bootstrap diode emulator | |
CN112567612B (en) | Driving circuit of switching element and switching circuit | |
US20160134272A1 (en) | Switch Driver With a Low-Cost Cross-Conduction-Preventing Circuit | |
WO2023134381A1 (en) | Switch power source circuit and terminal device | |
US5057721A (en) | Level shift circuit for controlling a driving circuit | |
EP0395146B1 (en) | Control circuit for at least one clock electrode of an integrated circuit | |
JPS631207A (en) | Trigger starting type oscillator | |
US5808884A (en) | Circuit and method for conserving energy in a boost regulator circuit | |
US9735678B2 (en) | Voltage converters with asymmetric gate voltages | |
US10461635B1 (en) | Low VIN high efficiency chargepump | |
US5459654A (en) | Apparatus for generating positive and negative supply rails from operating motor control circuit | |
US4106088A (en) | Current drive circuits | |
JPH01321723A (en) | Fet series circuit | |
US6813169B2 (en) | Inverter device capable of reducing through current | |
US6359500B1 (en) | Charge pump with efficient switching techniques | |
JPH0281090A (en) | Electric power recovery circuit | |
KR100745857B1 (en) | Electronic circuit provided with a digital driver for driving a capacitive load | |
CN1989582B (en) | Boosted switch drive with charge transfer | |
JP2003133926A (en) | Inrush current inhibiting circuit | |
US7319359B2 (en) | High current charge pump for intelligent power switch drive | |
US6177829B1 (en) | Device for improving the switching efficiency of an integrated circuit charge pump |