JPS59134915A - Amplitude limiting circuit - Google Patents

Abstract

PURPOSE:To set optionally a clipping level with simple constitution by providing a constant current supply circuit regulating the lower limit of the clipping level and a control transistor (TR) regulating the upper limit of the clipping level. CONSTITUTION:When an input signal is applied to a base of a TRQ1, an output of a differential circuit 11 drives a TRQ5 via a current mirror circuit 12 and an output signal corresponding to the input signal is generated at an output terminal 15. When a voltage level of the output signal is lower, a minimum value of a current flowing to resistors R1, R2 is regulated by a constant current source I2 and the lower limit of the output signal is clipped by a voltage level V2 being I2(R1+R2). On the other hand, when the voltage level of the output signal is high and the TRQ5 approaches nearly the saturating state, the TRQ6 is conductive, an output current of the current mirror circuit 12 is bypassed to ground and the upper limit of te output signal is clipped by a voltage level V1 being (I3-I2)(R1+R2).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The invention relates to an amplitude limiting circuit, and particularly to one in which the clipping level thereof can be arbitrarily set.

[Technical background of the invention]

As is well known, the conventionally used amplitude limiting circuit has a circuit between the signal line l and the grounding pin, as shown in FIG.
Diodes D,,D! so that the polarities are opposite to each other. are connected in parallel. In this case, the first diode D.

Assuming that D2 is silicon, for example, when an input signal as shown in FIG. Diode D.

D2 becomes conductive, and eventually the output terminal OUT has +0.7V or more and - as shown by the solid line in Fig. 2(b).
It is possible to obtain an output signal of 1.4 Vp-p in which a voltage level of 0.7 V or less (indicated by the dotted line in FIG. 2) is clipped.

Furthermore, Fig. 3 shows another conventional amplitude limiting circuit.
Return resistance R of an inverting amplifier circuit using an operational amplifier OP
In contrast, if diodes D3 and D4 are connected in parallel with opposite polarities, and the diodes D11+D4 are silicon, the output signal will be as shown in FIG. 2 (similar to the circuit shown in FIG. 1). It has 1.4Vp-p as shown in b).

[Problems with background technology]

However, in the conventional amplitude limiting circuit as described above,
Since the clipping voltage is determined by the characteristics of the diodes D to D4, the clipping voltage cannot be freely selected, and there is a problem in that it is particularly difficult to clip the voltage at a small amplitude.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide an extremely good amplitude limiting circuit that can arbitrarily set a clipping level with a simple configuration.

[Summary of the invention]

In other words, the present invention provides a differential circuit that is composed of a pair of transistors and an input signal is supplied to the control electrode of one of the transistors; a constant current supply circuit capable of supplying a constant current to the load when the output current of the output transistor is equal to or less than a predetermined value, and defining a lower limit of the clipping level; The present invention is characterized by comprising a control transistor that detects that the output current exceeds a certain value and bypasses the output current to define an upper limit of the clipping level.

[Embodiments of the invention]

Hereinafter, one practical example of the present invention will be explained in detail with reference to the drawings. In FIG. 4, Q.

Q is an NPN type transistor constituting the differential circuit 11, and its emitters are commonly connected. The collectors of these transistors Q+ and Qt are connected to the PNP type transistor QB+ that constitutes the current mirror circuit I2.
04 collectors, respectively. here,
The bases of the transistors Q3 and Q4 are commonly connected, and the connection point thereof is connected to the common connection point of the collectors of the transistors Q+ and Qs. In addition, the above transistor Q
The emitters of m and Qs are both connected to a power supply terminal 13 to which a DC voltage VCCO is applied.

Here, the base of the upper transistor Q is grounded via the input signal source 14. Further, the base of the transistor Q2 is grounded via a resistor R8 and connected to the output terminal 15 via a resistor R7.

Further, the emitter common connection point of the transistors Qs+Qt is connected to a power supply terminal 16 to which a DC voltage VSS is applied via a constant current source.

Further, a common connection point between the collectors of the transistors Qt and Q4 is connected to the base of an output NPN type transistor Q. Then, the resistor Rt and the output terminal I
5 is connected to the emitter of the transistor Qll, and is connected to the constant current source I! It is connected to the power supply terminal 16 via. Further, the collector of the trunk 4-star Q is connected to the power supply terminal 13 via the fixed line source 3.

Here, the transistor Q is parasitically associated with a control transistor Q6, which will be described in detail later. This transistor Q, is the transistor Q,
It is a PNP type having a polarity opposite to that of the transistor Q, and its emitter is common to the base of the transistor Q, and its base is common to the collector of the transistor Q, and the collector is a common transistor.

The operation of the above configuration will be explained below.

First, when an input signal from the power source 14 is supplied to the base of the transistor Q, the output of the differential circuit 11 is transmitted to the base of the transistor Qll through the current mirror circuit 12.
is driven, and an output signal corresponding to the input signal is generated at the output terminal 15.

Here, when the voltage level (amplitude) of the output signal becomes lower sequentially, that is, when the collector current of the transistor Qs decreases, the resistors R, , R.

The minimum value of the current flowing through is determined by the constant current source 2. Therefore, the output signal is I, (R, +R,):=V.

The lower limit is clipped at a voltage level of (see FIG. 5).

On the other hand, if the voltage level of the output signal increases sequentially, that is, the collector current of transistor aS increases,
Until the transistor Q reaches the saturated state, the transistor Q6 is in a non-conducting state, so an output signal corresponding to the input signal is generated at the output terminal 15. However, when the transistor Qs approaches the saturated state, , transistor Q6
becomes conductive, and the output current of the current mirror circuit I2 is diverted to the ground terminal. Therefore, the upper limit of the output signal is clipped at the negative pressure level of (Is, It)(R++Rt)=V+ (see FIG. 5).

Here, the configuration of the transistors Q and Q6 will be explained. That is, as shown in FIGS. 6(a) and 6(b), an N-type substrate 18 is bonded onto a P-type substrate 17, and
A P shadow area 19 is formed on the N-shaped residue plate 18. Further, a P shadow area 20 is formed at a predetermined position on the N type substrate 180, and the P shadow area 20 is formed at a predetermined position on the N type substrate 180.
An N-shaped region 21 is formed within the shaped region III, 20. Furthermore, on each spray surface of the N-type substrate 18 and the P-type space 20,
Electrodes 22, 23 are provided respectively.

By using the N-type beam 21 as an emitter, the electrode 23 as a pace, and the electrode 22 as a collector, an NPN
A type of transistor Q is constructed. Also,
The above electrode 23 is the emitter, the city fijL22 is the pace, P
By using the shadow region 19 as a collector, the PNP type transistor Q is constructed.

Therefore, according to the configuration of the above embodiment, constant g!
By changing the output current value of the female sources I, , I and the value of the resistor RIIR1, the clipping voltage can be set arbitrarily. Also, since the transistor Q6, which is configured parasitically based on the transistor Qs, is used,
The configuration is extremely simple and can be realized organically.

Figure 7 (a) I (b) is the same as Figure 6 (a) l (b
) shows a modified example of the structure of the transistors Qs and Qa, in which the P shadow region 20 is surrounded two-dimensionally by a part 191 of the P shadow region I9 to form a PNP type transistor Q6. Accordingly, a PNP transistor Q having a lateral structure can be formed without significantly increasing the device area.

Next, FIGS. 8 and 9 (4) show other embodiments of the present invention. First, in the one shown in FIG. 8, the output of the current mirror circuit 12 is connected to a PNP type transistor Q?
The current is supplied to the output transistor Q through an emitter follower circuit consisting of a constant current source 4 and a constant current source 4. With such a configuration, the same effects as in the above embodiment can be obtained. Moreover, what is shown in FIG. 9 shows the circuit configuration when the polarity of each transistor 8-Q to Q in the circuit shown in FIG. 4 is reversed. In this case, the output transistor Q Since it is not possible to utilize the control transistor Q6 which is parasitic to the transistor Q6, a separate NPN type transistor Q is used in place of the transistor Q6.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, it is possible to provide an extremely good amplitude limiting circuit that can arbitrarily set the clippinder level with a benevolent configuration.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram showing a conventional amplitude limiting circuit, Figs. 2 (a) and (b) are waveform diagrams showing input and output signals for the circuit shown in Fig. 1, respectively, and Fig. 3 is a circuit diagram showing a conventional amplitude limiting circuit. FIG. 4 is a circuit configuration diagram showing a conventional amplitude limiting circuit; FIG. 4 is a circuit configuration diagram showing an embodiment of the amplitude limiting circuit according to the present invention; FIG.
The figure is a waveform diagram for explaining the same example, FIG. 6(a)
, (b) are top views and side sectional views showing the configurations of the output transistor and control piece transistor of the same embodiment, respectively, and M7 figures (a) and (b) are respectively FIG. 6 (a).
The top view and side sectional view showing a modified example of the structure of the output transistor and control transistor shown in l(b), and FIGS. 8 and 9 are circuit configuration diagrams showing other embodiments of the present invention, respectively. be. 11...Differential circuit, 12...Current mirror circuit,
13...Power terminal, 14...Input signal source, 15...
・Output terminal, 16...1jL# terminal, 17...P type board, 18...N type board, I9...P shadow area, 20
...P shadow area, 2I...N shadow area, 22.23...
·electrode. Applicant's agent Patent attorney Takehiko Suzue 1st al1 sentence 2nd! ! ! Figure 3 11 - Figure 4 6 Figure 5 Figure 8 Figure 9 Figure 3 12]b

Claims (1)

[Claims] a differential circuit consisting of a pair of transistors, in which an input signal is supplied to the control electrode of one transistor; an output transistor that is controlled by the current output from the differential circuit and supplies the output current to the load; A constant current supply circuit capable of supplying a constant current to the load in a state in which the output current of the transistor becomes a predetermined value or less and defining a lower limit of a clipping level; and a condition that the output current of the output transistor becomes a predetermined value or more. and a control transistor that detects the output current and bypasses the output current to define an upper limit of the clipping level.