JPS5913416A - Waveform shaping circuit - Google Patents

Waveform shaping circuit

Info

Publication number
JPS5913416A
JPS5913416A JP12356982A JP12356982A JPS5913416A JP S5913416 A JPS5913416 A JP S5913416A JP 12356982 A JP12356982 A JP 12356982A JP 12356982 A JP12356982 A JP 12356982A JP S5913416 A JPS5913416 A JP S5913416A
Authority
JP
Japan
Prior art keywords
output
frequency
transformer
rectified
diodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12356982A
Other languages
Japanese (ja)
Other versions
JPH0252888B2 (en
Inventor
Masayuki Yaguchi
正行 矢口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12356982A priority Critical patent/JPS5913416A/en
Publication of JPS5913416A publication Critical patent/JPS5913416A/en
Publication of JPH0252888B2 publication Critical patent/JPH0252888B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K12/00Producing pulses by distorting or combining sinusoidal waveforms

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain easily square waves having the frequency corresponding to twice or more the frequency of an input signal source by taking out prescribed- shaped outputs from an output terminal constituted so that the output is taken out by turning on/off a switching transistor (TR) by a rectified and composed output. CONSTITUTION:Diodes D1, D2, D3, D4 rectify outputs generated from both ends of the secondary winding of a transformer T1 and the output terminal of a phase turning circuit and diodes D5, D6 rectify the full wave of the voltage between both ends of the secondary winding of the transformer T1. Respective voltage waveforms V1, V2, V3, V4 are rectified at their half-waves by the diodes D1, D2, D3, D4 and composed with each other at their output terminals. The voltage waveforms V5, V6 are impressed to switching TRs Q1, Q2 respectively. Therefore, the TRs Q1, Q2 are controlled on/off by the composed voltages V1, V6 respectively, and only when both TRs Q1, Q2 are turned on simultaneously, the potential V7 of a connection point between a resistor R5 and a diode D7 is turned to the low level. Consequently, a square wave with the frequency corresponding to twice the frequency of the input signal source E1 is obtained.

Description

【発明の詳細な説明】 本発明は入力信号の周波数の2倍あるいは数倍の波形整
形された矩形波信号を得るだめの波形整形回路に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform shaping circuit for obtaining a rectangular wave signal whose waveform is twice or several times the frequency of an input signal.

一般に現在時刻表示用の表示器とアラーム時刻表示用の
表示器をそれぞれ別々に設け、これらの表示器を商用電
源の周波数で交互に動作状態にし、実質的に現在時刻と
アラーム時刻が同時にそれぞれの表示器で別々に表示さ
れるように構成したディジタル表示時計が知られている
。ところでこの種のディジタル表示時計ではそれぞれの
表示器を交互に動作させるため一定のクロック信号を必
要とするが、この場合、商用電源をその一!、ま波形整
形してクロック信号として使用すると時計回路の動作機
能等の関係で商用電源周波数の責の周波数でそれぞれの
表示器が交互に切換え動作状態になることになり、たと
えば国内の場合には商用電源周波数が60Hz又は60
Hzであるため表示器の切換え周波数は25H2又は3
0H2となり表示そのものに大きなちらつきが生じると
いう問題がある。
Generally, a display for displaying the current time and a display for displaying the alarm time are provided separately, and these displays are alternately activated at the frequency of the commercial power supply, so that the current time and alarm time are displayed at the same time. Digital display clocks are known that are configured to be displayed separately on a display. By the way, this type of digital display clock requires a constant clock signal to operate each display alternately, but in this case, the commercial power supply is one of them! If the waveform is shaped and used as a clock signal, each display will alternately switch to the operating state at the frequency of the commercial power supply frequency due to the operating function of the clock circuit. Commercial power frequency is 60Hz or 60
Hz, so the switching frequency of the display is 25H2 or 3
There is a problem in that the display becomes 0H2 and a large flicker occurs in the display itself.

本発明はこのようなことから簡単な構成で2倍または数
倍の周波数の波形整形された矩形波を容易に得ることの
できる優れた波形整形回路を提供するものである。
In view of the above, the present invention provides an excellent waveform shaping circuit that can easily obtain a shaped rectangular wave having a frequency twice or several times higher with a simple configuration.

以下、本発明の波形整形回路について一実施例の図面と
ともに説明する。第1図は本1発明の波形整形回路にお
ける一実施例の電気的結線図であり図中、Etはたとえ
ば商用電源等の入力信号源、TIは一次巻線が入力信号
源Elに接続され、二次巻線の中点がアースされたトラ
ンス、R1,CI及びR2,’C2はそれぞれ互に直列
に接続され両端がそれぞれトランスTlの二次巻線の両
端に接続された位相回転回路を構成する抵抗及びコンデ
ンサ、D+ 、D2 、D3 、D4はそれぞれトラン
スT1の二次巻線の両端及び上記位相回転回路の出力端
に現われた出力を整流するダイオード、D5.D6はト
ランスTIの二次巻線の両端間の電圧を余波整流するだ
めのダイオード、 C3はダイオードDs 、 D6に
よって余波整流された電圧を平滑する平滑用のコンデン
サI Ql 、 Q2は互に直列に接続され、ベースが
それぞれ抵抗R3,R4を介して上記ダイオードD+ 
、D2 、D3 、D4の出力端に接続されたスイッチ
ング用のトランジスタ、R5はトランジスタQlのコレ
クタ負荷として作用する負荷抵抗D7はトランジスタQ
lのコレ、フタと抵抗R5との間に接続されたダイオー
ド、&は電源端子Wooがダイオードさ。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A waveform shaping circuit according to the present invention will be described below with reference to drawings of an embodiment. FIG. 1 is an electrical connection diagram of an embodiment of the waveform shaping circuit of the present invention. In the figure, Et is an input signal source such as a commercial power supply, TI is a primary winding connected to an input signal source El, The transformer, R1, CI, and R2, 'C2, whose middle point of the secondary winding is grounded, are connected in series with each other, forming a phase rotation circuit in which both ends are respectively connected to both ends of the secondary winding of the transformer Tl. resistors and capacitors D+, D2, D3, and D4 are diodes and D5 for rectifying the output appearing at both ends of the secondary winding of the transformer T1 and the output end of the phase rotation circuit, respectively. D6 is a diode for rectifying the voltage across the secondary winding of the transformer TI, C3 is a diode Ds, a smoothing capacitor I Ql for smoothing the voltage rectified by D6, and Q2 are connected in series with each other. The bases are connected to the diode D+ through resistors R3 and R4, respectively.
, D2, D3, and D4 are connected to the output ends of switching transistors, R5 acts as a collector load of the transistor Ql, and a load resistor D7 is connected to the transistor Q.
This is the diode connected between the lid and the resistor R5, and the & is the diode at the power supply terminal Woo.

D6の出力端に接続され、クロック信号入力端子が抵抗
R5とダイオードD7 の接続点に接続されたたとえば
時計回路等の負荷回路である。
This is a load circuit, such as a clock circuit, which is connected to the output terminal of D6 and whose clock signal input terminal is connected to the connection point between resistor R5 and diode D7.

上記実施例において今、位相回転回路を構成する抵抗R
1,R2,コンデンサCI、02の交流インピーダンス
がすべて同一であるとする。そして、コンデンサO1,
(zの損失を無視してこの部分の等節回路を画くと第2
図に示すようになる。第2図において、抵抗R2、コン
デンサC2に流れる電流をI+ 、コンデンサCt 、
抵抗R1に流れる電流をI2  、抵抗R1の両端の電
圧をvR+コンデンサC1の両端の電圧をvcとすると
これらの電流。
In the above embodiment, the resistor R constituting the phase rotation circuit is now
Assume that the AC impedances of 1, R2, capacitor CI, and 02 are all the same. And capacitor O1,
(Ignoring the loss of z and drawing an equinodal circuit for this part, the second
The result will be as shown in the figure. In Fig. 2, the current flowing through resistor R2 and capacitor C2 is I+, capacitor Ct,
These currents are: I2 is the current flowing through resistor R1, vR is the voltage across resistor R1, and vc is the voltage across capacitor C1.

電圧の関係は第3図に示すベクトル図の通りになる。し
たがって、抵抗R2とコンデンサC1、抵抗R2とコン
デンサCz 、抵抗R1とコンデンサ01゜抵抗R1と
コンデンサC2の各接続点の電圧をそレ−t’れVl 
、V2 、Va 、V4とし、これをアース電位を中心
に表わすと第4図に示すベクトル図の通りになる。すな
わち、これらの電圧V+ 、 V2.V3゜v4はそれ
ぞれ大きさが等しく、位相が900(T )づつずれて
いる。
The voltage relationship is as shown in the vector diagram shown in FIG. Therefore, the voltage at each connection point of resistor R2 and capacitor C1, resistor R2 and capacitor Cz, resistor R1 and capacitor 01°, resistor R1 and capacitor C2 is -t'Vl
, V2, Va, and V4, and if these are expressed centering on the ground potential, the result will be as shown in the vector diagram shown in FIG. That is, these voltages V+, V2. V3 and v4 have the same magnitude and are shifted in phase by 900 (T).

第5図はこれらの電圧波形を示すものであり、各電圧波
形V+ 、V2 、V3 、V4はそれぞれダイオード
D1.D3 、D2 、D4によって半波整流されその
出力端で互に合成される。したがって合成された電圧V
s 、 V6はそれぞれ第6図V5.V6に示すように
なり、これらがそれぞれスイッチング用トランジスタQ
l、Q2に印加されることになる。そのためトランジス
タQl、Q2はそれぞれ上記合成された電圧vs、v6
によってオン、オフ制御されることになり、両トランジ
スタQ+−,Q2が共ニオンシたときのみ抵抗R5とダ
イオードD7との接続点の電位v7がローレベルになる
。すなわち、トランジスタQI、Q2  は互に直列に
接続されているためいわゆるアンド回路を構成しており
、両トランジスタQ+、Q2がオンしたときのみトラン
ジスタQtのコレクタ電位がローレベルになる。したが
って。
FIG. 5 shows these voltage waveforms, and each voltage waveform V+, V2, V3, V4 is connected to the diode D1. The signals are half-wave rectified by D3, D2, and D4, and are combined together at their output terminals. Therefore, the combined voltage V
s and V6 are respectively shown in FIG. 6 V5. V6, and these are the switching transistors Q
1, and will be applied to Q2. Therefore, the transistors Ql and Q2 are connected to the above-mentioned combined voltages vs and v6, respectively.
The potential v7 at the connection point between the resistor R5 and the diode D7 becomes low level only when both transistors Q+- and Q2 are turned on. That is, since transistors QI and Q2 are connected in series, they form a so-called AND circuit, and the collector potential of transistor Qt becomes low level only when both transistors Q+ and Q2 are turned on. therefore.

第6図に示すように抵抗R5とダイオードD7との接続
点の電位v7は入力信号源1ctの周波数の2@の周波
数の矩形波となる。
As shown in FIG. 6, the potential v7 at the connection point between the resistor R5 and the diode D7 becomes a rectangular wave with a frequency 2@ of the frequency of the input signal source 1ct.

尚、トランジスタQlのコレクタに接続したダイオード
D7はトランスT1によって減圧し整流平滑した電圧を
そのままトランジスタQl、 Q2の電源電圧として使
用しているため、ダイオードD5.D6コンデンサC3
によって整流平滑した電圧よりダイオードDl、D2 
、D3 、D4の出力端に現われる電圧の方が高くなり
電源に向って電流が逆流するのを防止するためのもので
あり、トランジスタQ+Q2  の電源として別の電源
を用いる場合には必ずしも必要としないものである。
Note that the diode D7 connected to the collector of the transistor Ql uses the voltage that has been reduced, rectified and smoothed by the transformer T1 as it is as the power supply voltage for the transistors Ql and Q2, so the diode D5. D6 capacitor C3
From the rectified and smoothed voltage, the diodes Dl and D2
, D3, and D4 are higher in voltage, which prevents the current from flowing backward toward the power supply, and is not necessarily necessary when using another power supply as the power supply for transistors Q+Q2. It is something.

また、実施例では位相回転回路を2つ設けただけである
が、これを更に多く設け、それぞれの出力端の位相差を
任意に選ぶことにより入力信号源の周波数の4倍あるい
はそれ以上の周波数の矩形波でも容易に得ることができ
る。
Although only two phase rotation circuits are provided in the embodiment, by providing more phase rotation circuits and arbitrarily selecting the phase difference between the respective output terminals, it is possible to obtain a frequency four times or more than the frequency of the input signal source. It is also easy to obtain a square wave.

以上、実施例より明らかなように本発明によれば入力信
号源の周波数の2倍又はそれ以上の周波数の矩形波を容
易に得ることができ、商用電源を電源とする時計回路等
に用いて特に効果の大きいものである。
As is clear from the above embodiments, according to the present invention, it is possible to easily obtain a rectangular wave with a frequency twice or more than the frequency of the input signal source, and it can be used in clock circuits etc. powered by commercial power. This is particularly effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の波形整形回路における一実施例の電気
的結線図、第2図は同要部の等価回路図、第3図、第4
図は同要部の電流、電圧を示すベクトル図、第5図は同
実施例の各部の波形図である。 E】・・・・・・入力信号源、TI・・・・・・トラン
ス、R1゜R2、Ox、 02・・・・・位相回転回路
を構成する抵抗コンデンサ、Dl−D7・・・・・・ダ
イオード、  R3〜R5・・・・・・抵抗、Ql、Q
2・・・・・・スイッチング用トランジスタ。
Fig. 1 is an electrical connection diagram of one embodiment of the waveform shaping circuit of the present invention, Fig. 2 is an equivalent circuit diagram of the same main part, Figs.
The figure is a vector diagram showing the current and voltage of the same main parts, and FIG. 5 is a waveform diagram of each part of the same embodiment. E]... Input signal source, TI... Transformer, R1゜R2, Ox, 02... Resistance capacitor that constitutes the phase rotation circuit, Dl-D7...・Diode, R3~R5...Resistance, Ql, Q
2...Switching transistor.

Claims (1)

【特許請求の範囲】[Claims] 中点がアースされたトランスの2次巻線の両端間に、抵
抗、コンデンサより成る複数の位相回転回路を接続し、
これらの位相回転回路の出力及び上記トランスの2次巻
線の両端に現われる出力をそれぞれ整流合成して別に設
けたスイッチング用トランジスタを上記整流合成された
出力によりオン、オフ制御し、上記トランジスタの出力
端よシ所要の波形整形された出力を取出すように構成し
た波形整形回路。
Multiple phase rotation circuits consisting of resistors and capacitors are connected between both ends of the secondary winding of a transformer whose center point is grounded.
The outputs of these phase rotation circuits and the outputs appearing at both ends of the secondary winding of the transformer are rectified and combined, and a separately provided switching transistor is controlled on and off by the rectified and combined output, and the output of the transistor is A waveform shaping circuit configured to output a waveform-shaped output as required.
JP12356982A 1982-07-14 1982-07-14 Waveform shaping circuit Granted JPS5913416A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12356982A JPS5913416A (en) 1982-07-14 1982-07-14 Waveform shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12356982A JPS5913416A (en) 1982-07-14 1982-07-14 Waveform shaping circuit

Publications (2)

Publication Number Publication Date
JPS5913416A true JPS5913416A (en) 1984-01-24
JPH0252888B2 JPH0252888B2 (en) 1990-11-15

Family

ID=14863822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12356982A Granted JPS5913416A (en) 1982-07-14 1982-07-14 Waveform shaping circuit

Country Status (1)

Country Link
JP (1) JPS5913416A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2669786A1 (en) * 1990-11-23 1992-05-29 Thomson Csf DOUBLE FREQUENCY DEVICE.
JPH05199704A (en) * 1991-08-08 1993-08-06 General Electric Co <Ge> Electric actuator motor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5029270A (en) * 1973-07-18 1975-03-25
JPS53146561A (en) * 1977-05-27 1978-12-20 Toshiba Corp Frequency multiplier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5029270A (en) * 1973-07-18 1975-03-25
JPS53146561A (en) * 1977-05-27 1978-12-20 Toshiba Corp Frequency multiplier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2669786A1 (en) * 1990-11-23 1992-05-29 Thomson Csf DOUBLE FREQUENCY DEVICE.
US5194820A (en) * 1990-11-23 1993-03-16 Thomson-Csf Frequency doubling device
JPH05199704A (en) * 1991-08-08 1993-08-06 General Electric Co <Ge> Electric actuator motor

Also Published As

Publication number Publication date
JPH0252888B2 (en) 1990-11-15

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